Educational 16-bit MIPS Processor

in file alu.v, first line in case is: "`ALU_NC: r = 16'bx"

ALU_NC is mapped to 3'bxxx, which a synthesizer will treat as "don't care". this might me mapped for example to 3'b000, which is the same opcode asALU_ADD. such a mapping will cause ADD commands not to work...

all X's should be unreachable in normal operation.

Hi RonD, thanks for reading the code and finding the bug. I agree with the first part that the ALU_NC will be treated as "don't care", but I didn't found a condition which will cause the ADD instructions not to work. Could you please make it more clear? Please notice this point in ID_stage, that ALU_NCs are generated only in NOP instructions, in which condition RF write and MEM write are all disabled. Thanks again for your effort of refining the code.