T51 mcu

The way this file is currently implemented means there can potentially be 3 active addresses on any one cycle (IntAddrA, IntAddrB and IntAddrA_r). This means an ASIC implementation requires a 3 port RAM, which is clearly less efficient than a dual port.

Is there really any cycle where all three addresses are active?

I dont beleive this is the case. I am guessing IntAddrB is never used during a write cycle (which is the only time IntAddrA_r is used) and therefore these 2 addresses could share the second port.

Yes there is a case. Whenever a opcode which writes to internal ram is followed by a opcode which reads from PortB all three ports are used in the same cycle. Example: mov dir,#data mov @r0,dir

I have a modified version of the T51 core which need only a dual ported ram. This version is a little bit slower (about 5 %) than the current one. I will merge this two versions in the near future (selectable by an package constant) and put it back to Opencores.