Wishbone LPC Host and Peripheral Bridge

The wishbone bus in the wb_lpc_host block is little endian, 32 bits wide with byte granularity. The code is written to assume all byte read/write data appears on wbs_dat7:0.

I believe it should be written such that byte data appears across all 4 byte lanes with appropriate wbs_sel_i values depending on the decode of the bottom 2 address bits (ie an access to address 0xf00b0003 would have wbs_sel_i == 4'b1000, wbs_adr_i == 0xf00b0000, and the data on wbs_dat_i31:24).