Wishbone LPC Host and Peripheral Bridge

The LPC peripheral should implement the abort mechanism. I think that a simple fix in all state (except LPC_ST_IDLE) could do the job:

case(state) 'LPC_ST_XXXX: begin if(lframe_i) begin lad_oe <= 1'b0; state <= `LPC_ST_IDLE; end else begin "actual code" end end