URL https://opencores.org/ocsvn/10_100m_ethernet-fifo_convertor/10_100m_ethernet-fifo_convertor/trunk

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[/] [10_100m_ethernet-fifo_convertor/] [verilog/] [tri_state.v] - Blame information for rev 10

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//author :gurenliang 
//Email: gurenliang@gmail.com
//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.
 
module tri_state(d_in, d_out, out_en, ioport);
        input d_out, out_en;                    //init_clk should be 10KHz
        output d_in;
        inout ioport;
 
        assign ioport = (out_en) ?  d_out:1'bz;
        assign d_in = ioport;
endmodule

Line No.	Rev	Author	Line
1	10	antiquity	`//author :gurenliang`
2			`//Email: gurenliang@gmail.com`
3			`//note: if there are some errors, you are welcome to contact me. It would be the best appreciation to me.`
4
5			`module tri_state(d_in, d_out, out_en, ioport);`
6			`input d_out, out_en; //init_clk should be 10KHz`
7			`output d_in;`
8			`inout ioport;`
9
10			`assign ioport = (out_en) ? d_out:1'bz;`
11			`assign d_in = ioport;`
12			`endmodule`

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Subversion Repositories 10_100m_ethernet-fifo_convertor

[/] [10_100m_ethernet-fifo_convertor/] [verilog/] [tri_state.v] - Blame information for rev 10