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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [src/] [rtl/] [mblite/] [core/] [decode.vhd] - Blame information for rev 7

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----------------------------------------------------------------------------------------------
--
--      Input file         : decode.vhd
--      Design name        : decode
--      Author             : Tamar Kranenburg
--      Company            : Delft University of Technology
--                         : Faculty EEMCS, Department ME&CE
--                         : Systems and Circuits group
--
--      Description        : This combined register file and decoder uses three Dual Port
--                           read after write Random Access Memory components. Every clock
--                           cycle three data values can be read (ra, rb and rd) and one value
--                           can be stored.
--
----------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
 
library mblite;
use mblite.config_Pkg.all;
use mblite.core_Pkg.all;
use mblite.std_Pkg.all;
 
entity decode is generic
(
    G_INTERRUPT  : boolean := CFG_INTERRUPT;
    G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;
    G_USE_BARREL : boolean := CFG_USE_BARREL;
    G_DEBUG      : boolean := CFG_DEBUG
);
port
(
    decode_o : out decode_out_type;
    gprf_o   : out gprf_out_type;
    decode_i : in decode_in_type;
    ena_i    : in std_logic;
    rst_i    : in std_logic;
    clk_i    : in std_logic
);
end decode;
 
architecture arch of decode is
 
    type decode_reg_type is record
        instruction          : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
        program_counter      : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
        immediate            : std_logic_vector(15 downto 0);
        is_immediate         : std_logic;
        msr_interrupt_enable : std_logic;
        interrupt            : std_logic;
        delay_interrupt      : std_logic;
    end record;
 
    signal r, rin     : decode_out_type;
    signal reg, regin : decode_reg_type;
 
    signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
begin
 
    decode_o.imm <= r.imm;
 
    decode_o.ctrl_ex <= r.ctrl_ex;
    decode_o.ctrl_mem <= r.ctrl_mem;
    decode_o.ctrl_wrb <= r.ctrl_wrb;
 
    decode_o.reg_a <= r.reg_a;
    decode_o.reg_b <= r.reg_b;
    decode_o.hazard <= r.hazard;
    decode_o.program_counter <= r.program_counter;
 
    decode_o.fwd_dec_result <= r.fwd_dec_result;
    decode_o.fwd_dec <= r.fwd_dec;
 
    decode_comb: process(decode_i,decode_i.ctrl_wrb,
                         decode_i.ctrl_mem_wrb,
                         decode_i.instruction,
                         decode_i.ctrl_mem_wrb.transfer_size,
                         r,r.ctrl_ex,r.ctrl_mem,
                         r.ctrl_mem.transfer_size,r.ctrl_wrb,
                         r.ctrl_wrb.reg_d,
                         r.fwd_dec,reg)
 
        variable v : decode_out_type;
        variable v_reg : decode_reg_type;
        variable opcode : std_logic_vector(5 downto 0);
        variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);
        variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);
        variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);
 
    begin
        v := r;
        v_reg := reg;
 
        -- Default register values (NOP)
        v_reg.immediate := (others => '0');
        v_reg.is_immediate := '0';
        v_reg.program_counter := decode_i.program_counter;
        v_reg.instruction := decode_i.instruction;
 
        if decode_i.ctrl_mem_wrb.mem_read = '1' then
            mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));
        else
            mem_result := decode_i.alu_result;
        end if;
 
        wb_dat_d <= mem_result;
 
        if G_INTERRUPT = true then
            v_reg.delay_interrupt := '0';
        end if;
 
        if CFG_REG_FWD_WRB = true then
            v.fwd_dec_result    := mem_result;
            v.fwd_dec           := decode_i.ctrl_wrb;
        else
            v.fwd_dec_result    := (others => '0');
            v.fwd_dec.reg_d     := (others => '0');
            v.fwd_dec.reg_write := '0';
        end if;
 
        if (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then
        -- A hazard occurred on register a or b
 
            -- set current instruction and program counter to 0
            instruction := (others => '0');
            program_counter := (others => '0');
 
            v.hazard := '1';
 
        elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then
        -- A hazard occurred on register d
 
            -- set current instruction and program counter to 0
            instruction := (others => '0');
            program_counter := (others => '0');
 
            v.hazard := '1';
 
        elsif r.hazard = '1' then
        -- Recover from hazard. Insert latched instruction
 
            instruction := reg.instruction;
            program_counter := reg.program_counter;
            v.hazard := '0';
 
        else
 
            instruction := decode_i.instruction;
            program_counter := decode_i.program_counter;
            v.hazard := '0';
 
        end if;
 
        v.program_counter := program_counter;
        opcode := instruction(31 downto 26);
        v.ctrl_wrb.reg_d := instruction(25 downto 21);
        v.reg_a := instruction(20 downto 16);
        v.reg_b := instruction(15 downto 11);
 
        -- SET IMM value
        if reg.is_immediate = '1' then
            v.imm := reg.immediate & instruction(15 downto 0);
        else
            v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);
        end if;
 
        -- Register if an interrupt occurs
        if G_INTERRUPT = true then
            if v_reg.msr_interrupt_enable = '1' and decode_i.interrupt = '1' then
                v_reg.interrupt := '1';
                v_reg.msr_interrupt_enable := '0';
            end if;
        end if;
 
        v.ctrl_ex.alu_op := ALU_ADD;
        v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
        v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
        v.ctrl_ex.operation := '0';
        v.ctrl_ex.carry := CARRY_ZERO;
        v.ctrl_ex.carry_keep := CARRY_KEEP;
        v.ctrl_ex.delay := '0';
        v.ctrl_ex.branch_cond := NOP;
        v.ctrl_mem.mem_write := '0';
        v.ctrl_mem.transfer_size := WORD;
        v.ctrl_mem.mem_read := '0';
        v.ctrl_wrb.reg_write := '0';
 
        if G_INTERRUPT = true and (v_reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then
        -- IF an interrupt occured
        --    AND the current instruction is not a branch or return instruction,
        --    AND the current instruction is not in a delay slot,
        --    AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.
            v_reg.msr_interrupt_enable := '0';
            v_reg.interrupt := '0';
 
            v.reg_a := (others => '0');
            v.reg_b := (others => '0');
 
            v.imm   := X"00000010";
            v.ctrl_wrb.reg_d := "01110";
 
            v.ctrl_ex.branch_cond := BNC;
            v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
            v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            v.ctrl_wrb.reg_write := '1';
 
        elsif (decode_i.flush_id or v.hazard) = '1' then
            -- clearing these registers is not necessary, but facilitates debugging.
            -- On the other hand performance improves when disabled.
            if G_DEBUG = true then
                v.program_counter := (others => '0');
                v.ctrl_wrb.reg_d  := (others => '0');
                v.reg_a           := (others => '0');
                v.reg_b           := (others => '0');
                v.imm             := (others => '0');
            end if;
 
        elsif is_zero(opcode(5 downto 4)) = '1' then
        -- ADD, SUBTRACT OR COMPARE
 
            -- Alu operation
            v.ctrl_ex.alu_op := ALU_ADD;
 
            -- Source operand A
            if opcode(0) = '1' then
                v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;
            else
                v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
            end if;
 
            -- Source operand B
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            if (compare(opcode, "000101") and instruction(1)) = '1' then
                v.ctrl_ex.operation := '1';
            end if;
 
            -- Carry
            case opcode(1 downto 0) is
                when "00" => v.ctrl_ex.carry := CARRY_ZERO;
                when "01" => v.ctrl_ex.carry := CARRY_ONE;
                when others => v.ctrl_ex.carry := CARRY_ALU;
            end case;
 
            -- Carry keep
            if opcode(2) = '1' then
                v.ctrl_ex.carry_keep := CARRY_KEEP;
            else
                v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
            end if;
 
            -- Flag writeback if reg_d != 0
            v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
        elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then
        -- OR, AND, XOR, ANDN
        -- ORI, ANDI, XORI, ANDNI
            case opcode(1 downto 0) is
                when "00" => v.ctrl_ex.alu_op := ALU_OR;
                when "10" => v.ctrl_ex.alu_op := ALU_XOR;
                when others => v.ctrl_ex.alu_op := ALU_AND;
            end case;
 
            if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;
            elsif opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            -- Flag writeback if reg_d != 0
            v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
        elsif compare(opcode, "101100") = '1' then
        -- IMM instruction
            v_reg.immediate := instruction(15 downto 0);
            v_reg.is_immediate := '1';
 
        elsif compare(opcode, "100100") = '1' then
        -- SHIFT, SIGN EXTEND
            if compare(instruction(6 downto 5), "11") = '1' then
                if instruction(0) = '1' then
                    v.ctrl_ex.alu_op:= ALU_SEXT16;
                else
                    v.ctrl_ex.alu_op:= ALU_SEXT8;
                end if;
            else
                v.ctrl_ex.alu_op:= ALU_SHIFT;
                v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;
                case instruction(6 downto 5) is
                    when "10"   => v.ctrl_ex.carry := CARRY_ZERO;
                    when "01"   => v.ctrl_ex.carry := CARRY_ALU;
                    when others => v.ctrl_ex.carry := CARRY_ARITH;
                end case;
            end if;
 
            -- Flag writeback if reg_d != 0
            v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
        elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then
        -- BRANCH UNCONDITIONAL
 
            v.ctrl_ex.branch_cond := BNC;
 
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            -- WRITE THE RESULT ALSO TO REGISTER D
            if v.reg_a(2) = '1' then
                -- Flag writeback if reg_d != 0
                v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
            end if;
 
            if v.reg_a(3) = '1' then
                v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;
            else
                v.ctrl_ex.alu_src_a := ALU_SRC_PC;
            end if;
 
            if G_INTERRUPT = true then
                v_reg.delay_interrupt := '1';
            end if;
            v.ctrl_ex.delay := v.reg_a(4);
 
        elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then
        -- BRANCH CONDITIONAL
            v.ctrl_ex.alu_op := ALU_ADD;
            v.ctrl_ex.alu_src_a := ALU_SRC_PC;
 
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            case v.ctrl_wrb.reg_d(2 downto 0) is
                when "000"  => v.ctrl_ex.branch_cond := BEQ;
                when "001"  => v.ctrl_ex.branch_cond := BNE;
                when "010"  => v.ctrl_ex.branch_cond := BLT;
                when "011"  => v.ctrl_ex.branch_cond := BLE;
                when "100"  => v.ctrl_ex.branch_cond := BGT;
                when others => v.ctrl_ex.branch_cond := BGE;
            end case;
 
            if G_INTERRUPT = true then
                v_reg.delay_interrupt := '1';
            end if;
            v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);
 
        elsif compare(opcode, "101101") = '1' then
        -- RETURN
 
            v.ctrl_ex.branch_cond := BNC;
            v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            v.ctrl_ex.delay := '1';
 
            if G_INTERRUPT = true then
                if v.ctrl_wrb.reg_d(0) = '1' then
                    v_reg.msr_interrupt_enable := '1';
                end if;
                v_reg.delay_interrupt := '1';
            end if;
 
        elsif compare(opcode(5 downto 4), "11") = '1' then
            -- SW, LW
            v.ctrl_ex.alu_op := ALU_ADD;
            v.ctrl_ex.alu_src_a := ALU_SRC_REGA;
 
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            v.ctrl_ex.carry := CARRY_ZERO;
 
            if opcode(2) = '1' then
                -- Store
                v.ctrl_mem.mem_write := '1';
                v.ctrl_mem.mem_read  := '0';
                v.ctrl_wrb.reg_write := '0';
            else
                -- Load
                v.ctrl_mem.mem_write := '0';
                v.ctrl_mem.mem_read  := '1';
                v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
            end if;
 
            case opcode(1 downto 0) is
                when "00" => v.ctrl_mem.transfer_size := BYTE;
                when "01" => v.ctrl_mem.transfer_size := HALFWORD;
                when others => v.ctrl_mem.transfer_size := WORD;
            end case;
 
            v.ctrl_ex.delay := '0';
 
        elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then
 
            v.ctrl_ex.alu_op := ALU_MUL;
 
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
        elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then
 
            v.ctrl_ex.alu_op := ALU_BS;
 
            if opcode(3) = '1' then
                v.ctrl_ex.alu_src_b := ALU_SRC_IMM;
            else
                v.ctrl_ex.alu_src_b := ALU_SRC_REGB;
            end if;
 
            v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);
 
        else
            -- UNKNOWN OPCODE
            null;
        end if;
 
        rin <= v;
        regin <= v_reg;
 
    end process;
 
    decode_seq: process(clk_i)
        procedure proc_reset_decode is
        begin
            r.reg_a                  <= (others => '0');
            r.reg_b                  <= (others => '0');
            r.imm                    <= (others => '0');
            r.program_counter        <= (others => '0');
            r.hazard                 <= '0';
            r.ctrl_ex.alu_op         <= ALU_ADD;
            r.ctrl_ex.alu_src_a      <= ALU_SRC_REGA;
            r.ctrl_ex.alu_src_b      <= ALU_SRC_REGB;
            r.ctrl_ex.operation      <= '0';
            r.ctrl_ex.carry          <= CARRY_ZERO;
            r.ctrl_ex.carry_keep     <= CARRY_NOT_KEEP;
            r.ctrl_ex.delay          <= '0';
            r.ctrl_ex.branch_cond    <= NOP;
            r.ctrl_mem.mem_write     <= '0';
            r.ctrl_mem.transfer_size <= WORD;
            r.ctrl_mem.mem_read      <= '0';
            r.ctrl_wrb.reg_d          <= (others => '0');
            r.ctrl_wrb.reg_write      <= '0';
            r.fwd_dec_result         <= (others => '0');
            r.fwd_dec.reg_d          <= (others => '0');
            r.fwd_dec.reg_write      <= '0';
            reg.instruction          <= (others => '0');
            reg.program_counter      <= (others => '0');
            reg.immediate            <= (others => '0');
            reg.is_immediate         <= '0';
            reg.msr_interrupt_enable <= '1';
            reg.interrupt            <= '0';
            reg.delay_interrupt      <= '0';
        end procedure proc_reset_decode;
    begin
        if rising_edge(clk_i) then
            if rst_i = '1' then
                proc_reset_decode;
            elsif ena_i = '1' then
                r <= rin;
                reg <= regin;
            end if;
        end if;
    end process;
 
    gprf0 : gprf port map
    (
        gprf_o         => gprf_o,
        gprf_i.adr_a_i => rin.reg_a,
        gprf_i.adr_b_i => rin.reg_b,
        gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,
        gprf_i.dat_w_i => wb_dat_d,
        gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,
        gprf_i.wre_i   => decode_i.ctrl_wrb.reg_write,
        ena_i          => ena_i,
        clk_i          => clk_i
    );
end arch;

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Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [tags/] [vmblite_base/] [hw/] [src/] [rtl/] [mblite/] [core/] [decode.vhd] - Blame information for rev 7

Line No.	Rev	Author	Line
1	7	kuzmi4	`----------------------------------------------------------------------------------------------`
2			`--`
3			`-- Input file : decode.vhd`
4			`-- Design name : decode`
5			`-- Author : Tamar Kranenburg`
6			`-- Company : Delft University of Technology`
7			`-- : Faculty EEMCS, Department ME&CE`
8			`-- : Systems and Circuits group`
9			`--`
10			`-- Description : This combined register file and decoder uses three Dual Port`
11			`-- read after write Random Access Memory components. Every clock`
12			`-- cycle three data values can be read (ra, rb and rd) and one value`
13			`-- can be stored.`
14			`--`
15			`----------------------------------------------------------------------------------------------`
16
17			`library ieee;`
18			`use ieee.std_logic_1164.all;`
19			`use ieee.std_logic_unsigned.all;`
20
21			`library mblite;`
22			`use mblite.config_Pkg.all;`
23			`use mblite.core_Pkg.all;`
24			`use mblite.std_Pkg.all;`
25
26			`entity decode is generic`
27			`(`
28			`G_INTERRUPT : boolean := CFG_INTERRUPT;`
29			`G_USE_HW_MUL : boolean := CFG_USE_HW_MUL;`
30			`G_USE_BARREL : boolean := CFG_USE_BARREL;`
31			`G_DEBUG : boolean := CFG_DEBUG`
32			`);`
33			`port`
34			`(`
35			`decode_o : out decode_out_type;`
36			`gprf_o : out gprf_out_type;`
37			`decode_i : in decode_in_type;`
38			`ena_i : in std_logic;`
39			`rst_i : in std_logic;`
40			`clk_i : in std_logic`
41			`);`
42			`end decode;`
43
44			`architecture arch of decode is`
45
46			`type decode_reg_type is record`
47			`instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);`
48			`program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);`
49			`immediate : std_logic_vector(15 downto 0);`
50			`is_immediate : std_logic;`
51			`msr_interrupt_enable : std_logic;`
52			`interrupt : std_logic;`
53			`delay_interrupt : std_logic;`
54			`end record;`
55
56			`signal r, rin : decode_out_type;`
57			`signal reg, regin : decode_reg_type;`
58
59			`signal wb_dat_d : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);`
60
61			`begin`
62
63			`decode_o.imm <= r.imm;`
64
65			`decode_o.ctrl_ex <= r.ctrl_ex;`
66			`decode_o.ctrl_mem <= r.ctrl_mem;`
67			`decode_o.ctrl_wrb <= r.ctrl_wrb;`
68
69			`decode_o.reg_a <= r.reg_a;`
70			`decode_o.reg_b <= r.reg_b;`
71			`decode_o.hazard <= r.hazard;`
72			`decode_o.program_counter <= r.program_counter;`
73
74			`decode_o.fwd_dec_result <= r.fwd_dec_result;`
75			`decode_o.fwd_dec <= r.fwd_dec;`
76
77			`decode_comb: process(decode_i,decode_i.ctrl_wrb,`
78			`decode_i.ctrl_mem_wrb,`
79			`decode_i.instruction,`
80			`decode_i.ctrl_mem_wrb.transfer_size,`
81			`r,r.ctrl_ex,r.ctrl_mem,`
82			`r.ctrl_mem.transfer_size,r.ctrl_wrb,`
83			`r.ctrl_wrb.reg_d,`
84			`r.fwd_dec,reg)`
85
86			`variable v : decode_out_type;`
87			`variable v_reg : decode_reg_type;`
88			`variable opcode : std_logic_vector(5 downto 0);`
89			`variable instruction : std_logic_vector(CFG_IMEM_WIDTH - 1 downto 0);`
90			`variable program_counter : std_logic_vector(CFG_IMEM_SIZE - 1 downto 0);`
91			`variable mem_result : std_logic_vector(CFG_DMEM_WIDTH - 1 downto 0);`
92
93			`begin`
94			`v := r;`
95			`v_reg := reg;`
96
97			`-- Default register values (NOP)`
98			`v_reg.immediate := (others => '0');`
99			`v_reg.is_immediate := '0';`
100			`v_reg.program_counter := decode_i.program_counter;`
101			`v_reg.instruction := decode_i.instruction;`
102
103			`if decode_i.ctrl_mem_wrb.mem_read = '1' then`
104			`mem_result := align_mem_load(decode_i.mem_result, decode_i.ctrl_mem_wrb.transfer_size, decode_i.alu_result(1 downto 0));`
105			`else`
106			`mem_result := decode_i.alu_result;`
107			`end if;`
108
109			`wb_dat_d <= mem_result;`
110
111			`if G_INTERRUPT = true then`
112			`v_reg.delay_interrupt := '0';`
113			`end if;`
114
115			`if CFG_REG_FWD_WRB = true then`
116			`v.fwd_dec_result := mem_result;`
117			`v.fwd_dec := decode_i.ctrl_wrb;`
118			`else`
119			`v.fwd_dec_result := (others => '0');`
120			`v.fwd_dec.reg_d := (others => '0');`
121			`v.fwd_dec.reg_write := '0';`
122			`end if;`
123
124			`if (not decode_i.flush_id and r.ctrl_mem.mem_read and (compare(decode_i.instruction(20 downto 16), r.ctrl_wrb.reg_d) or compare(decode_i.instruction(15 downto 11), r.ctrl_wrb.reg_d))) = '1' then`
125			`-- A hazard occurred on register a or b`
126
127			`-- set current instruction and program counter to 0`
128			`instruction := (others => '0');`
129			`program_counter := (others => '0');`
130
131			`v.hazard := '1';`
132
133			`elsif CFG_MEM_FWD_WRB = false and (not decode_i.flush_id and r.ctrl_mem.mem_read and compare(decode_i.instruction(25 downto 21), r.ctrl_wrb.reg_d)) = '1' then`
134			`-- A hazard occurred on register d`
135
136			`-- set current instruction and program counter to 0`
137			`instruction := (others => '0');`
138			`program_counter := (others => '0');`
139
140			`v.hazard := '1';`
141
142			`elsif r.hazard = '1' then`
143			`-- Recover from hazard. Insert latched instruction`
144
145			`instruction := reg.instruction;`
146			`program_counter := reg.program_counter;`
147			`v.hazard := '0';`
148
149			`else`
150
151			`instruction := decode_i.instruction;`
152			`program_counter := decode_i.program_counter;`
153			`v.hazard := '0';`
154
155			`end if;`
156
157			`v.program_counter := program_counter;`
158			`opcode := instruction(31 downto 26);`
159			`v.ctrl_wrb.reg_d := instruction(25 downto 21);`
160			`v.reg_a := instruction(20 downto 16);`
161			`v.reg_b := instruction(15 downto 11);`
162
163			`-- SET IMM value`
164			`if reg.is_immediate = '1' then`
165			`v.imm := reg.immediate & instruction(15 downto 0);`
166			`else`
167			`v.imm := sign_extend(instruction(15 downto 0), instruction(15), 32);`
168			`end if;`
169
170			`-- Register if an interrupt occurs`
171			`if G_INTERRUPT = true then`
172			`if v_reg.msr_interrupt_enable = '1' and decode_i.interrupt = '1' then`
173			`v_reg.interrupt := '1';`
174			`v_reg.msr_interrupt_enable := '0';`
175			`end if;`
176			`end if;`
177
178			`v.ctrl_ex.alu_op := ALU_ADD;`
179			`v.ctrl_ex.alu_src_a := ALU_SRC_REGA;`
180			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
181			`v.ctrl_ex.operation := '0';`
182			`v.ctrl_ex.carry := CARRY_ZERO;`
183			`v.ctrl_ex.carry_keep := CARRY_KEEP;`
184			`v.ctrl_ex.delay := '0';`
185			`v.ctrl_ex.branch_cond := NOP;`
186			`v.ctrl_mem.mem_write := '0';`
187			`v.ctrl_mem.transfer_size := WORD;`
188			`v.ctrl_mem.mem_read := '0';`
189			`v.ctrl_wrb.reg_write := '0';`
190
191			`if G_INTERRUPT = true and (v_reg.interrupt = '1' and reg.delay_interrupt = '0' and decode_i.flush_id = '0' and v.hazard = '0' and r.ctrl_ex.delay = '0' and reg.is_immediate = '0') then`
192			`-- IF an interrupt occured`
193			`-- AND the current instruction is not a branch or return instruction,`
194			`-- AND the current instruction is not in a delay slot,`
195			`-- AND this is instruction is not preceded by an IMM instruction, than handle the interrupt.`
196			`v_reg.msr_interrupt_enable := '0';`
197			`v_reg.interrupt := '0';`
198
199			`v.reg_a := (others => '0');`
200			`v.reg_b := (others => '0');`
201
202			`v.imm := X"00000010";`
203			`v.ctrl_wrb.reg_d := "01110";`
204
205			`v.ctrl_ex.branch_cond := BNC;`
206			`v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;`
207			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
208			`v.ctrl_wrb.reg_write := '1';`
209
210			`elsif (decode_i.flush_id or v.hazard) = '1' then`
211			`-- clearing these registers is not necessary, but facilitates debugging.`
212			`-- On the other hand performance improves when disabled.`
213			`if G_DEBUG = true then`
214			`v.program_counter := (others => '0');`
215			`v.ctrl_wrb.reg_d := (others => '0');`
216			`v.reg_a := (others => '0');`
217			`v.reg_b := (others => '0');`
218			`v.imm := (others => '0');`
219			`end if;`
220
221			`elsif is_zero(opcode(5 downto 4)) = '1' then`
222			`-- ADD, SUBTRACT OR COMPARE`
223
224			`-- Alu operation`
225			`v.ctrl_ex.alu_op := ALU_ADD;`
226
227			`-- Source operand A`
228			`if opcode(0) = '1' then`
229			`v.ctrl_ex.alu_src_a := ALU_SRC_NOT_REGA;`
230			`else`
231			`v.ctrl_ex.alu_src_a := ALU_SRC_REGA;`
232			`end if;`
233
234			`-- Source operand B`
235			`if opcode(3) = '1' then`
236			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
237			`else`
238			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
239			`end if;`
240
241			`if (compare(opcode, "000101") and instruction(1)) = '1' then`
242			`v.ctrl_ex.operation := '1';`
243			`end if;`
244
245			`-- Carry`
246			`case opcode(1 downto 0) is`
247			`when "00" => v.ctrl_ex.carry := CARRY_ZERO;`
248			`when "01" => v.ctrl_ex.carry := CARRY_ONE;`
249			`when others => v.ctrl_ex.carry := CARRY_ALU;`
250			`end case;`
251
252			`-- Carry keep`
253			`if opcode(2) = '1' then`
254			`v.ctrl_ex.carry_keep := CARRY_KEEP;`
255			`else`
256			`v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;`
257			`end if;`
258
259			`-- Flag writeback if reg_d != 0`
260			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
261
262			`elsif (compare(opcode(5 downto 2), "1000") or compare(opcode(5 downto 2), "1010")) = '1' then`
263			`-- OR, AND, XOR, ANDN`
264			`-- ORI, ANDI, XORI, ANDNI`
265			`case opcode(1 downto 0) is`
266			`when "00" => v.ctrl_ex.alu_op := ALU_OR;`
267			`when "10" => v.ctrl_ex.alu_op := ALU_XOR;`
268			`when others => v.ctrl_ex.alu_op := ALU_AND;`
269			`end case;`
270
271			`if opcode(3) = '1' and compare(opcode(1 downto 0), "11") = '1' then`
272			`v.ctrl_ex.alu_src_b := ALU_SRC_NOT_IMM;`
273			`elsif opcode(3) = '1' then`
274			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
275			`elsif opcode(3) = '0' and compare(opcode(1 downto 0), "11") = '1' then`
276			`v.ctrl_ex.alu_src_b := ALU_SRC_NOT_REGB;`
277			`else`
278			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
279			`end if;`
280
281			`-- Flag writeback if reg_d != 0`
282			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
283
284			`elsif compare(opcode, "101100") = '1' then`
285			`-- IMM instruction`
286			`v_reg.immediate := instruction(15 downto 0);`
287			`v_reg.is_immediate := '1';`
288
289			`elsif compare(opcode, "100100") = '1' then`
290			`-- SHIFT, SIGN EXTEND`
291			`if compare(instruction(6 downto 5), "11") = '1' then`
292			`if instruction(0) = '1' then`
293			`v.ctrl_ex.alu_op:= ALU_SEXT16;`
294			`else`
295			`v.ctrl_ex.alu_op:= ALU_SEXT8;`
296			`end if;`
297			`else`
298			`v.ctrl_ex.alu_op:= ALU_SHIFT;`
299			`v.ctrl_ex.carry_keep := CARRY_NOT_KEEP;`
300			`case instruction(6 downto 5) is`
301			`when "10" => v.ctrl_ex.carry := CARRY_ZERO;`
302			`when "01" => v.ctrl_ex.carry := CARRY_ALU;`
303			`when others => v.ctrl_ex.carry := CARRY_ARITH;`
304			`end case;`
305			`end if;`
306
307			`-- Flag writeback if reg_d != 0`
308			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
309
310			`elsif (compare(opcode, "100110") or compare(opcode, "101110")) = '1' then`
311			`-- BRANCH UNCONDITIONAL`
312
313			`v.ctrl_ex.branch_cond := BNC;`
314
315			`if opcode(3) = '1' then`
316			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
317			`else`
318			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
319			`end if;`
320
321			`-- WRITE THE RESULT ALSO TO REGISTER D`
322			`if v.reg_a(2) = '1' then`
323			`-- Flag writeback if reg_d != 0`
324			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
325			`end if;`
326
327			`if v.reg_a(3) = '1' then`
328			`v.ctrl_ex.alu_src_a := ALU_SRC_ZERO;`
329			`else`
330			`v.ctrl_ex.alu_src_a := ALU_SRC_PC;`
331			`end if;`
332
333			`if G_INTERRUPT = true then`
334			`v_reg.delay_interrupt := '1';`
335			`end if;`
336			`v.ctrl_ex.delay := v.reg_a(4);`
337
338			`elsif (compare(opcode, "100111") or compare(opcode, "101111")) = '1' then`
339			`-- BRANCH CONDITIONAL`
340			`v.ctrl_ex.alu_op := ALU_ADD;`
341			`v.ctrl_ex.alu_src_a := ALU_SRC_PC;`
342
343			`if opcode(3) = '1' then`
344			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
345			`else`
346			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
347			`end if;`
348
349			`case v.ctrl_wrb.reg_d(2 downto 0) is`
350			`when "000" => v.ctrl_ex.branch_cond := BEQ;`
351			`when "001" => v.ctrl_ex.branch_cond := BNE;`
352			`when "010" => v.ctrl_ex.branch_cond := BLT;`
353			`when "011" => v.ctrl_ex.branch_cond := BLE;`
354			`when "100" => v.ctrl_ex.branch_cond := BGT;`
355			`when others => v.ctrl_ex.branch_cond := BGE;`
356			`end case;`
357
358			`if G_INTERRUPT = true then`
359			`v_reg.delay_interrupt := '1';`
360			`end if;`
361			`v.ctrl_ex.delay := v.ctrl_wrb.reg_d(4);`
362
363			`elsif compare(opcode, "101101") = '1' then`
364			`-- RETURN`
365
366			`v.ctrl_ex.branch_cond := BNC;`
367			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
368			`v.ctrl_ex.delay := '1';`
369
370			`if G_INTERRUPT = true then`
371			`if v.ctrl_wrb.reg_d(0) = '1' then`
372			`v_reg.msr_interrupt_enable := '1';`
373			`end if;`
374			`v_reg.delay_interrupt := '1';`
375			`end if;`
376
377			`elsif compare(opcode(5 downto 4), "11") = '1' then`
378			`-- SW, LW`
379			`v.ctrl_ex.alu_op := ALU_ADD;`
380			`v.ctrl_ex.alu_src_a := ALU_SRC_REGA;`
381
382			`if opcode(3) = '1' then`
383			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
384			`else`
385			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
386			`end if;`
387
388			`v.ctrl_ex.carry := CARRY_ZERO;`
389
390			`if opcode(2) = '1' then`
391			`-- Store`
392			`v.ctrl_mem.mem_write := '1';`
393			`v.ctrl_mem.mem_read := '0';`
394			`v.ctrl_wrb.reg_write := '0';`
395			`else`
396			`-- Load`
397			`v.ctrl_mem.mem_write := '0';`
398			`v.ctrl_mem.mem_read := '1';`
399			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
400			`end if;`
401
402			`case opcode(1 downto 0) is`
403			`when "00" => v.ctrl_mem.transfer_size := BYTE;`
404			`when "01" => v.ctrl_mem.transfer_size := HALFWORD;`
405			`when others => v.ctrl_mem.transfer_size := WORD;`
406			`end case;`
407
408			`v.ctrl_ex.delay := '0';`
409
410			`elsif G_USE_HW_MUL = true and (compare(opcode, "010000") or compare(opcode, "011000")) = '1' then`
411
412			`v.ctrl_ex.alu_op := ALU_MUL;`
413
414			`if opcode(3) = '1' then`
415			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
416			`else`
417			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
418			`end if;`
419
420			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
421
422			`elsif G_USE_BARREL = true and (compare(opcode, "010001") or compare(opcode, "011001")) = '1' then`
423
424			`v.ctrl_ex.alu_op := ALU_BS;`
425
426			`if opcode(3) = '1' then`
427			`v.ctrl_ex.alu_src_b := ALU_SRC_IMM;`
428			`else`
429			`v.ctrl_ex.alu_src_b := ALU_SRC_REGB;`
430			`end if;`
431
432			`v.ctrl_wrb.reg_write := is_not_zero(v.ctrl_wrb.reg_d);`
433
434			`else`
435			`-- UNKNOWN OPCODE`
436			`null;`
437			`end if;`
438
439			`rin <= v;`
440			`regin <= v_reg;`
441
442			`end process;`
443
444			`decode_seq: process(clk_i)`
445			`procedure proc_reset_decode is`
446			`begin`
447			`r.reg_a <= (others => '0');`
448			`r.reg_b <= (others => '0');`
449			`r.imm <= (others => '0');`
450			`r.program_counter <= (others => '0');`
451			`r.hazard <= '0';`
452			`r.ctrl_ex.alu_op <= ALU_ADD;`
453			`r.ctrl_ex.alu_src_a <= ALU_SRC_REGA;`
454			`r.ctrl_ex.alu_src_b <= ALU_SRC_REGB;`
455			`r.ctrl_ex.operation <= '0';`
456			`r.ctrl_ex.carry <= CARRY_ZERO;`
457			`r.ctrl_ex.carry_keep <= CARRY_NOT_KEEP;`
458			`r.ctrl_ex.delay <= '0';`
459			`r.ctrl_ex.branch_cond <= NOP;`
460			`r.ctrl_mem.mem_write <= '0';`
461			`r.ctrl_mem.transfer_size <= WORD;`
462			`r.ctrl_mem.mem_read <= '0';`
463			`r.ctrl_wrb.reg_d <= (others => '0');`
464			`r.ctrl_wrb.reg_write <= '0';`
465			`r.fwd_dec_result <= (others => '0');`
466			`r.fwd_dec.reg_d <= (others => '0');`
467			`r.fwd_dec.reg_write <= '0';`
468			`reg.instruction <= (others => '0');`
469			`reg.program_counter <= (others => '0');`
470			`reg.immediate <= (others => '0');`
471			`reg.is_immediate <= '0';`
472			`reg.msr_interrupt_enable <= '1';`
473			`reg.interrupt <= '0';`
474			`reg.delay_interrupt <= '0';`
475			`end procedure proc_reset_decode;`
476			`begin`
477			`if rising_edge(clk_i) then`
478			`if rst_i = '1' then`
479			`proc_reset_decode;`
480			`elsif ena_i = '1' then`
481			`r <= rin;`
482			`reg <= regin;`
483			`end if;`
484			`end if;`
485			`end process;`
486
487			`gprf0 : gprf port map`
488			`(`
489			`gprf_o => gprf_o,`
490			`gprf_i.adr_a_i => rin.reg_a,`
491			`gprf_i.adr_b_i => rin.reg_b,`
492			`gprf_i.adr_d_i => rin.ctrl_wrb.reg_d,`
493			`gprf_i.dat_w_i => wb_dat_d,`
494			`gprf_i.adr_w_i => decode_i.ctrl_wrb.reg_d,`
495			`gprf_i.wre_i => decode_i.ctrl_wrb.reg_write,`
496			`ena_i => ena_i,`
497			`clk_i => clk_i`
498			`);`
499			`end arch;`