| 1 |
4 |
kuzmi4 |
# clk
|
| 2 |
|
|
create_clock -name sys_clk_pin -period "5.0" [get_ports "sys_diff_clock_clk_p"]
|
| 3 |
|
|
set_input_jitter sys_clk_pin 0.050
|
| 4 |
|
|
|
| 5 |
|
|
# Associate the IDELAYCTRL in the support level to the I/Os in the core using IODELAYs
|
| 6 |
|
|
#set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells {trimac_fifo_block/trimac_sup_block/tri_mode_ethernet_mac_idelayctrl_common_i}]
|
| 7 |
|
|
set_property IODELAY_GROUP tri_mode_ethernet_mac_iodelay_grp [get_cells -hierarchical tri_mode_ethernet_mac_idelayctrl_common_i]
|
| 8 |
|
|
|
| 9 |
|
|
# Get auto-generated clock names
|
| 10 |
|
|
set axi_clk_name [get_clocks -of [get_pins example_clocks/clock_generator/mmcm_adv_inst/CLKOUT1]]
|
| 11 |
|
|
# => set MDC output delay
|
| 12 |
|
|
set_output_delay -clock $axi_clk_name 1 [get_ports mdc]
|
| 13 |
|
|
|
| 14 |
|
|
# PHY-RST cut-off
|
| 15 |
|
|
set_false_path -from [get_cells -hier -filter {name =~ *phy_resetn_int_reg}] -to [get_ports phy_resetn]
|
| 16 |
|
|
|
| 17 |
|
|
# Clock Crossing Constraints
|
| 18 |
|
|
set_false_path -from [get_cells -hier -filter {name =~ *phy_resetn_int_reg}] -to [get_cells -hier -filter {name =~ *axi_lite_reset_gen/reset_sync*}]
|
| 19 |
|
|
# +Ignore paths to resync flops
|
| 20 |
|
|
set_false_path -to [get_pins -hier -filter {NAME =~ */reset_sync*/PRE}]
|
| 21 |
|
|
set_false_path -to [get_pins -hier -filter {NAME =~ */*_sync*/D}]
|
| 22 |
|
|
|
| 23 |
|
|
# FIFO Clock Crossing Constraints: control signal is synched separately so this is a false path
|
| 24 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/rd_addr_reg[*]}] -to [get_cells -hier -filter {name =~ *fifo*wr_rd_addr_reg[*]}] 3.2 -datapath_only
|
| 25 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/wr_store_frame_tog_reg}] -to [get_cells -hier -filter {name =~ *fifo_i/resync_wr_store_frame_tog/data_sync_reg0}] 3.2 -datapath_only
|
| 26 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *rx_fifo_i/update_addr_tog_reg}] -to [get_cells -hier -filter {name =~ *rx_fifo_i/sync_rd_addr_tog/data_sync_reg0}] 3.2 -datapath_only
|
| 27 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_addr_txfer_reg[*]}] -to [get_cells -hier -filter {name =~ *fifo*wr_rd_addr_reg[*]}] 3.2 -datapath_only
|
| 28 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/wr_frame_in_fifo_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_wr_frame_in_fifo/data_sync_reg0}] 3.2 -datapath_only
|
| 29 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/wr_frames_in_fifo_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_wr_frames_in_fifo/data_sync_reg0}] 3.2 -datapath_only
|
| 30 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/frame_in_fifo_valid_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_fif_valid_tog/data_sync_reg0}] 3.2 -datapath_only
|
| 31 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_txfer_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_rd_txfer_tog/data_sync_reg0}] 3.2 -datapath_only
|
| 32 |
|
|
set_max_delay -from [get_cells -hier -filter {name =~ *tx_fifo_i/rd_tran_frame_tog_reg}] -to [get_cells -hier -filter {name =~ *tx_fifo_i/resync_rd_tran_frame_tog/data_sync_reg0}] 3.2 -datapath_only
|
