Subversion Repositories 1g_ethernet_dpi

//----------------------------------------------------------------------------

// File       : tri_mode_ethernet_mac_0_support_clocking.v

// Author     : Xilinx Inc.

// -----------------------------------------------------------------------------

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//

//----------------------------------------------------------------------------

// Output     Output      Phase    Duty Cycle   Pk-to-Pk     Phase

// Clock     Freq (MHz)  (degrees)    (%)     Jitter (ps)  Error (ps)

//----------------------------------------------------------------------------

// clk_out1   125.000      0.000      50.0       91.364     85.928 

// clk_out2   125.000     90.000      50.0       70.716     85.928

//

//----------------------------------------------------------------------------

// Input Clock   Input Freq (MHz)   Input Jitter (UI)

//----------------------------------------------------------------------------

// primary         125.000            0.010

`timescale 1ns / 1ps

//***************************** Entity Declaration ****************************

module tri_mode_ethernet_mac_0_support_clocking (

  // Clock in ports

  input         clk_in1,

  // Clock out ports

  output        clk_out1,

  output        clk_out2,

  // Status and control signals

  input         reset,

  output        locked

 );

// Clocking primitive

  //------------------------------------

  // Instantiation of the MMCM primitive

  //    * Unused inputs are tied off

  //    * Unused outputs are labeled unused

  wire [15:0] do_unused;

  wire        drdy_unused;

  wire        psdone_unused;

  wire        clkfbout;

  wire        clkfboutb_unused;

  wire        clkout0b_unused;

  wire        clkout1b_unused;

  wire        clkout2b_unused;

  wire        clkout3_unused;

  wire        clkout3b_unused;

  wire        clkout4_unused;

  wire        clkout5_unused;

  wire        clkout6_unused;

  wire        clkfbstopped_unused;

  wire        clkinstopped_unused;

    MMCME2_ADV

  #(.BANDWIDTH            ("OPTIMIZED"),

    .COMPENSATION         ("ZHOLD"),

    .DIVCLK_DIVIDE        (1),

    .CLKFBOUT_MULT_F      (5.000),

    .CLKFBOUT_PHASE       (0.000),

    .CLKOUT0_DIVIDE_F     (5.000),

    .CLKOUT0_PHASE        (0.000),

    .CLKOUT0_DUTY_CYCLE   (0.500),

    .CLKOUT1_DIVIDE       (5),

    .CLKOUT1_PHASE        (90.000),

    .CLKOUT1_DUTY_CYCLE   (0.500),

    .CLKOUT2_DIVIDE       (5),

    .CLKOUT2_PHASE        (0.000),

    .CLKOUT2_DUTY_CYCLE   (0.500),

    .CLKIN1_PERIOD        (8.000),

    .REF_JITTER1          (0.010))

  mmcm_adv_inst

    // Output clocks

   (.CLKFBOUT            (clkfbout),

    .CLKFBOUTB           (clkfboutb_unused),

    .CLKOUT0             (clkout0),

    .CLKOUT0B            (clkout0b_unused),

    .CLKOUT1             (clkout1),

    .CLKOUT1B            (clkout1b_unused),

    .CLKOUT2             (clkout2),

    .CLKOUT2B            (clkout2b_unused),

    .CLKOUT3             (clkout3_unused),

    .CLKOUT3B            (clkout3b_unused),

    .CLKOUT4             (clkout4_unused),

    .CLKOUT5             (clkout5_unused),

    .CLKOUT6             (clkout6_unused),

     // Input clock control

    .CLKFBIN             (clkfbout),

    .CLKIN1              (clk_in1),

    .CLKIN2              (1'b0),

     // Tied to always select the primary input clock

    .CLKINSEL            (1'b1),

    // Ports for dynamic reconfiguration

    .DADDR               (7'h0),

    .DCLK                (1'b0),

    .DEN                 (1'b0),

    .DI                  (16'h0),

    .DO                  (do_unused),

    .DRDY                (drdy_unused),

    .DWE                 (1'b0),

    // Ports for dynamic phase shift

    .PSCLK               (1'b0),

    .PSEN                (1'b0),

    .PSINCDEC            (1'b0),

    .PSDONE              (psdone_unused),

    // Other control and status signals

    .LOCKED              (locked),

    .CLKINSTOPPED        (clkinstopped_unused),

    .CLKFBSTOPPED        (clkfbstopped_unused),

    .PWRDWN              (1'b0),

    .RST                 (reset));

  // Output buffering

  //-----------------------------------

  BUFGCE clkout1_buf

   (.O   (clk_out1),

    .CE  (1'b1),

    .I   (clkout0));

  BUFGCE clkout2_buf

   (.O   (clk_out2),

    .CE  (1'b1),

    .I   (clkout1));

endmodule