Subversion Repositories 1g_ethernet_dpi

//------------------------------------------------------------------------------

// File       : tri_mode_ethernet_mac_0_fifo_block.v

// Author     : Xilinx Inc.

// -----------------------------------------------------------------------------

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// -----------------------------------------------------------------------------

// Description: This is the FIFO Block level vhdl wrapper for the Tri-Mode

//              Ethernet MAC core.  This wrapper enhances the standard MAC core

//              with an example FIFO.  The interface to this FIFO is

//              designed to the AXI-S specification.

//              Please refer to core documentation for

//              additional FIFO and AXI-S information.

//

//         _________________________________________________________

//        |                                                         |

//        |                 FIFO BLOCK LEVEL WRAPPER                |

//        |                                                         |

//        |   _____________________       ______________________    |

//        |  |  _________________  |     |                      |   |

//        |  | |                 | |     |                      |   |

//  -------->| |   TX AXI FIFO   | |---->| Tx               Tx  |--------->

//        |  | |                 | |     | AXI-S            PHY |   |

//        |  | |_________________| |     | I/F              I/F |   |

//        |  |                     |     |                      |   |

//  AXI   |  |     10/100/1G       |     |  TRI-MODE ETHERNET   |   |

// Stream |  |    ETHERNET FIFO    |     |          MAC         |   | PHY I/F

//        |  |                     |     |     SUPPORT LEVEL    |   |

//        |  |  _________________  |     |                      |   |

//        |  | |                 | |     |                      |   |

//  <--------| |   RX AXI FIFO   | |<----| Rx               Rx  |<---------

//        |  | |                 | |     | AXI-S            PHY |   |

//        |  | |_________________| |     | I/F              I/F |   |

//        |  |_____________________|     |______________________|   |

//        |                                                         |

//        |_________________________________________________________|

`timescale 1 ps/1 ps

//------------------------------------------------------------------------------

// The module declaration for the FIFO Block level wrapper.

//------------------------------------------------------------------------------

(* DowngradeIPIdentifiedWarnings = "yes" *)

module tri_mode_ethernet_mac_0_fifo_block (

      input         gtx_clk,

      // asynchronous reset

      input         glbl_rstn,

      input         rx_axi_rstn,

      input         tx_axi_rstn,

      // Reference clock for IDELAYCTRL's

      input         refclk,

/*

      // Receiver Statistics Interface

      //---------------------------------------

      output        rx_mac_aclk,

      output        rx_reset,

      output [27:0] rx_statistics_vector,

      output        rx_statistics_valid,

*/

      // Receiver (AXI-S) Interface

      //----------------------------------------

      input         rx_fifo_clock,

      input         rx_fifo_resetn,

      output [7:0]  rx_axis_fifo_tdata,

      output        rx_axis_fifo_tvalid,

      input         rx_axis_fifo_tready,

      output        rx_axis_fifo_tlast,

/*

      // Transmitter Statistics Interface

      //------------------------------------------

      output        tx_mac_aclk,

      output        tx_reset,

      input  [7:0]  tx_ifg_delay,

      output [31:0] tx_statistics_vector,

      output        tx_statistics_valid,

*/

      // Transmitter (AXI-S) Interface

      //-------------------------------------------

      input         tx_fifo_clock,

      input         tx_fifo_resetn,

      input  [7:0]  tx_axis_fifo_tdata,

      input         tx_axis_fifo_tvalid,

      output        tx_axis_fifo_tready,

      input         tx_axis_fifo_tlast,

/*

      // MAC Control Interface

      //------------------------

      input         pause_req,

      input  [15:0] pause_val,

*/

      // RGMII Interface

      //------------------

      output [3:0]  rgmii_txd,

      output        rgmii_tx_ctl,

      output        rgmii_txc,

      input  [3:0]  rgmii_rxd,

      input         rgmii_rx_ctl,

      input         rgmii_rxc,

      // RGMII Inband Status Registers

      //--------------------------------

      output        inband_link_status,

      output [1:0]  inband_clock_speed,

      output        inband_duplex_status,

      // MDIO Interface

      //---------------

      inout         mdio,

      output        mdc,

      // AXI-Lite Interface

      //---------------

      input         s_axi_aclk,

      input         s_axi_resetn,

      input  [11:0] s_axi_awaddr,

      input         s_axi_awvalid,

      output        s_axi_awready,

      input  [31:0] s_axi_wdata,

      input         s_axi_wvalid,

      output        s_axi_wready,

      output [1:0]  s_axi_bresp,

      output        s_axi_bvalid,

      input         s_axi_bready,

      input  [11:0] s_axi_araddr,

      input         s_axi_arvalid,

      output        s_axi_arready,

      output [31:0] s_axi_rdata,

      output [1:0]  s_axi_rresp,

      output        s_axi_rvalid,

      input         s_axi_rready

   );

  //----------------------------------------------------------------------------

  // Internal signals used in this fifo block level wrapper.

  //----------------------------------------------------------------------------

  wire       rx_mac_aclk_int;    // MAC Rx clock

  wire       tx_mac_aclk_int;    // MAC Tx clock

  wire       rx_reset_int;       // MAC Rx reset

  wire       tx_reset_int;       // MAC Tx reset

  // MAC receiver client I/F

  wire [7:0] rx_axis_mac_tdata;

  wire       rx_axis_mac_tvalid;

  wire       rx_axis_mac_tlast;

  wire       rx_axis_mac_tuser;

  // MAC transmitter client I/F

  wire [7:0] tx_axis_mac_tdata;

  wire       tx_axis_mac_tvalid;

  wire       tx_axis_mac_tready;

  wire       tx_axis_mac_tlast;

  wire       tx_axis_mac_tuser;

  //----------------------------------------------------------------------------

  // Connect the output clock signals

  //----------------------------------------------------------------------------

  assign rx_mac_aclk          = rx_mac_aclk_int;

  assign tx_mac_aclk          = tx_mac_aclk_int;

  assign rx_reset             = rx_reset_int;

  assign tx_reset             = tx_reset_int;

  //----------------------------------------------------------------------------

  // Instantiate the Tri-Mode Ethernet MAC Support Level wrapper

  //----------------------------------------------------------------------------

  tri_mode_ethernet_mac_0_support trimac_sup_block (

      .gtx_clk              (gtx_clk),

      .gtx_clk_out          (),

      .gtx_clk90_out        (),

      // asynchronous reset

      .glbl_rstn            (glbl_rstn),

      .rx_axi_rstn          (rx_axi_rstn),

      .tx_axi_rstn          (tx_axi_rstn),

      // Receiver Interface

      .rx_enable            (),

      .rx_statistics_vector (rx_statistics_vector),

      .rx_statistics_valid  (rx_statistics_valid),

      .rx_mac_aclk          (rx_mac_aclk_int),

      .rx_reset             (rx_reset_int),

      .rx_axis_mac_tdata    (rx_axis_mac_tdata),

      .rx_axis_mac_tvalid   (rx_axis_mac_tvalid),

      .rx_axis_mac_tlast    (rx_axis_mac_tlast),

      .rx_axis_mac_tuser    (rx_axis_mac_tuser),

      // Transmitter Interface

      .tx_enable             (),

      .tx_ifg_delay         (tx_ifg_delay),

      .tx_statistics_vector (tx_statistics_vector),

      .tx_statistics_valid  (tx_statistics_valid),

      .tx_mac_aclk          (tx_mac_aclk_int),

      .tx_reset             (tx_reset_int),

      .tx_axis_mac_tdata    (tx_axis_mac_tdata ),

      .tx_axis_mac_tvalid   (tx_axis_mac_tvalid),

      .tx_axis_mac_tlast    (tx_axis_mac_tlast),

      .tx_axis_mac_tuser    (tx_axis_mac_tuser ),

      .tx_axis_mac_tready   (tx_axis_mac_tready),

      // Flow Control

      .pause_req            (pause_req),

      .pause_val            (pause_val),

      // Reference clock for IDELAYCTRL's

      .refclk               (refclk),

      // Speed Control

      .speedis100           (),

      .speedis10100         (),

      // RGMII Interface

      .rgmii_txd            (rgmii_txd),

      .rgmii_tx_ctl         (rgmii_tx_ctl),

      .rgmii_txc            (rgmii_txc),

      .rgmii_rxd            (rgmii_rxd),

      .rgmii_rx_ctl         (rgmii_rx_ctl),

      .rgmii_rxc            (rgmii_rxc),

      .inband_link_status   (inband_link_status),

      .inband_clock_speed   (inband_clock_speed),

      .inband_duplex_status (inband_duplex_status),

      // MDIO Interface

      //---------------

      .mdio                 (mdio),

      .mdc                  (mdc),

      // AXI lite interface

      .s_axi_aclk           (s_axi_aclk),

      .s_axi_resetn         (s_axi_resetn),

      .s_axi_awaddr         (s_axi_awaddr),

      .s_axi_awvalid        (s_axi_awvalid),

      .s_axi_awready        (s_axi_awready),

      .s_axi_wdata          (s_axi_wdata),

      .s_axi_wvalid         (s_axi_wvalid),

      .s_axi_wready         (s_axi_wready),

      .s_axi_bresp          (s_axi_bresp),

      .s_axi_bvalid         (s_axi_bvalid),

      .s_axi_bready         (s_axi_bready),

      .s_axi_araddr         (s_axi_araddr),

      .s_axi_arvalid        (s_axi_arvalid),

      .s_axi_arready        (s_axi_arready),

      .s_axi_rdata          (s_axi_rdata),

      .s_axi_rresp          (s_axi_rresp),

      .s_axi_rvalid         (s_axi_rvalid),

      .s_axi_rready         (s_axi_rready),

      .mac_irq              ()

   );

   //----------------------------------------------------------------------------

   // Instantiate the user side FIFO

   //----------------------------------------------------------------------------

   // locally reset sync the mac generated resets - the resets are already fully sync

   // so adding a reset sync shouldn't change that

   tri_mode_ethernet_mac_0_reset_sync rx_mac_reset_gen (

      .clk                  (rx_mac_aclk_int),

      .enable               (1'b1),

      .reset_in             (rx_reset_int),

      .reset_out            (rx_mac_reset)

   );

   tri_mode_ethernet_mac_0_reset_sync tx_mac_reset_gen (

      .clk                  (tx_mac_aclk_int),

      .enable               (1'b1),

      .reset_in             (tx_reset_int),

      .reset_out            (tx_mac_reset)

   );

   // create inverted mac resets as the FIFO expects AXI compliant resets

   assign tx_mac_resetn = !tx_mac_reset;

   assign rx_mac_resetn = !rx_mac_reset;

   tri_mode_ethernet_mac_0_ten_100_1g_eth_fifo #

   (

      .FULL_DUPLEX_ONLY     (1)

   )

   user_side_FIFO

   (

      // Transmit FIFO MAC TX Interface

      .tx_fifo_aclk           (tx_fifo_clock),

      .tx_fifo_resetn         (tx_fifo_resetn),

      .tx_axis_fifo_tdata     (tx_axis_fifo_tdata),

      .tx_axis_fifo_tvalid    (tx_axis_fifo_tvalid),

      .tx_axis_fifo_tlast     (tx_axis_fifo_tlast),

      .tx_axis_fifo_tready    (tx_axis_fifo_tready),

      .tx_mac_aclk            (tx_mac_aclk_int),

      .tx_mac_resetn          (tx_mac_resetn),

      .tx_axis_mac_tdata      (tx_axis_mac_tdata),

      .tx_axis_mac_tvalid     (tx_axis_mac_tvalid),

      .tx_axis_mac_tlast      (tx_axis_mac_tlast),

      .tx_axis_mac_tready     (tx_axis_mac_tready),

      .tx_axis_mac_tuser      (tx_axis_mac_tuser),

      .tx_fifo_overflow       (),

      .tx_fifo_status         (),

      .tx_collision           (1'b0),

      .tx_retransmit          (1'b0),

      .rx_fifo_aclk           (rx_fifo_clock),

      .rx_fifo_resetn         (rx_fifo_resetn),

      .rx_axis_fifo_tdata     (rx_axis_fifo_tdata),

      .rx_axis_fifo_tvalid    (rx_axis_fifo_tvalid),

      .rx_axis_fifo_tlast     (rx_axis_fifo_tlast),

      .rx_axis_fifo_tready    (rx_axis_fifo_tready),

      .rx_mac_aclk            (rx_mac_aclk_int),

      .rx_mac_resetn          (rx_mac_resetn),

      .rx_axis_mac_tdata      (rx_axis_mac_tdata),

      .rx_axis_mac_tvalid     (rx_axis_mac_tvalid),

      .rx_axis_mac_tlast      (rx_axis_mac_tlast),

      .rx_axis_mac_tuser      (rx_axis_mac_tuser),

      .rx_fifo_status         (),

      .rx_fifo_overflow       ()

  );

endmodule