OpenCores
URL https://opencores.org/ocsvn/1g_ethernet_dpi/1g_ethernet_dpi/trunk

Subversion Repositories 1g_ethernet_dpi

[/] [1g_ethernet_dpi/] [trunk/] [sw/] [dev/] [test_main/] [src/] [_hdl/] [bsp/] [libsrc/] [axidma_v9_0/] [src/] [xaxidma_g.c] - Blame information for rev 4

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 kuzmi4
 
2
/*******************************************************************
3
*
4
* CAUTION: This file is automatically generated by HSI.
5
* Version:
6
* DO NOT EDIT.
7
*
8
* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
9
*Permission is hereby granted, free of charge, to any person obtaining a copy
10
*of this software and associated documentation files (the Software), to deal
11
*in the Software without restriction, including without limitation the rights
12
*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
13
*copies of the Software, and to permit persons to whom the Software is
14
*furnished to do so, subject to the following conditions:
15
*
16
*The above copyright notice and this permission notice shall be included in
17
*all copies or substantial portions of the Software.
18
*
19
* Use of the Software is limited solely to applications:
20
*(a) running on a Xilinx device, or
21
*(b) that interact with a Xilinx device through a bus or interconnect.
22
*
23
*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24
*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25
*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26
*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
27
*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
28
*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29
*
30
*Except as contained in this notice, the name of the Xilinx shall not be used
31
*in advertising or otherwise to promote the sale, use or other dealings in
32
*this Software without prior written authorization from Xilinx.
33
*
34
 
35
*
36
* Description: Driver configuration
37
*
38
*******************************************************************/
39
 
40
#include "xparameters.h"
41
#include "xaxidma.h"
42
 
43
/*
44
* The configuration table for devices
45
*/
46
 
47
XAxiDma_Config XAxiDma_ConfigTable[] =
48
{
49
        {
50
                XPAR_AXI_DMA_0_DEVICE_ID,
51
                XPAR_AXI_DMA_0_BASEADDR,
52
                XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM,
53
                XPAR_AXI_DMA_0_INCLUDE_MM2S,
54
                XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE,
55
                XPAR_AXI_DMA_0_M_AXI_MM2S_DATA_WIDTH,
56
                XPAR_AXI_DMA_0_INCLUDE_S2MM,
57
                XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE,
58
                XPAR_AXI_DMA_0_M_AXI_S2MM_DATA_WIDTH,
59
                XPAR_AXI_DMA_0_INCLUDE_SG,
60
                XPAR_AXI_DMA_0_NUM_MM2S_CHANNELS,
61
                XPAR_AXI_DMA_0_NUM_S2MM_CHANNELS,
62
                XPAR_AXI_DMA_0_MM2S_BURST_SIZE,
63
                XPAR_AXI_DMA_0_S2MM_BURST_SIZE,
64
                XPAR_AXI_DMA_0_MICRO_DMA,
65
                XPAR_AXI_DMA_0_ADDR_WIDTH
66
        }
67
};
68
 
69
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.