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/*******************************************************************
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*
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* CAUTION: This file is automatically generated by HSI.
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* Version:
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* DO NOT EDIT.
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*
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* Copyright (C) 2010-2016 Xilinx, Inc. All Rights Reserved.*
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*Permission is hereby granted, free of charge, to any person obtaining a copy
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*of this software and associated documentation files (the Software), to deal
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*in the Software without restriction, including without limitation the rights
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*to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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*copies of the Software, and to permit persons to whom the Software is
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*furnished to do so, subject to the following conditions:
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*
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*The above copyright notice and this permission notice shall be included in
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*all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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*(a) running on a Xilinx device, or
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*(b) that interact with a Xilinx device through a bus or interconnect.
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*
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*THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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*IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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*FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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*XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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*WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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*OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*Except as contained in this notice, the name of the Xilinx shall not be used
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*in advertising or otherwise to promote the sale, use or other dealings in
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*this Software without prior written authorization from Xilinx.
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*
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*
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* Description: Driver configuration
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*
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*******************************************************************/
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#include "xparameters.h"
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#include "xaxidma.h"
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/*
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* The configuration table for devices
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*/
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XAxiDma_Config XAxiDma_ConfigTable[] =
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{
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{
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XPAR_AXI_DMA_0_DEVICE_ID,
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XPAR_AXI_DMA_0_BASEADDR,
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XPAR_AXI_DMA_0_SG_INCLUDE_STSCNTRL_STRM,
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XPAR_AXI_DMA_0_INCLUDE_MM2S,
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XPAR_AXI_DMA_0_INCLUDE_MM2S_DRE,
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XPAR_AXI_DMA_0_M_AXI_MM2S_DATA_WIDTH,
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XPAR_AXI_DMA_0_INCLUDE_S2MM,
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XPAR_AXI_DMA_0_INCLUDE_S2MM_DRE,
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XPAR_AXI_DMA_0_M_AXI_S2MM_DATA_WIDTH,
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XPAR_AXI_DMA_0_INCLUDE_SG,
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XPAR_AXI_DMA_0_NUM_MM2S_CHANNELS,
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XPAR_AXI_DMA_0_NUM_S2MM_CHANNELS,
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XPAR_AXI_DMA_0_MM2S_BURST_SIZE,
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XPAR_AXI_DMA_0_S2MM_BURST_SIZE,
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XPAR_AXI_DMA_0_MICRO_DMA,
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XPAR_AXI_DMA_0_ADDR_WIDTH
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}
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};
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