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/******************************************************************************
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*
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* Copyright (C) 2010 - 2015 Xilinx, Inc. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* Use of the Software is limited solely to applications:
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* (a) running on a Xilinx device, or
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* (b) that interact with a Xilinx device through a bus or interconnect.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
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* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Except as contained in this notice, the name of the Xilinx shall not be used
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* in advertising or otherwise to promote the sale, use or other dealings in
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* this Software without prior written authorization from Xilinx.
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*
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******************************************************************************/
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/*****************************************************************************/
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/**
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* @file xaxidma_hw.h
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* @addtogroup axidma_v9_0
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* @{
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*
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* Hardware definition file. It defines the register interface and Buffer
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* Descriptor (BD) definitions.
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*
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* <pre>
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -------------------------------------------------------
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* 1.00a jz 05/18/10 First release
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* 2.00a jz 08/10/10 Second release, added in xaxidma_g.c, xaxidma_sinit.c,
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* updated tcl file, added xaxidma_porting_guide.h
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* 3.00a jz 11/22/10 Support IP core parameters change
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* 4.00a rkv 02/22/11 Added support for simple DMA mode
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* 6.00a srt 01/24/12 Added support for Multi-Channel DMA mode
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* 8.0 srt 01/29/14 Added support for Micro DMA Mode and Cyclic mode of
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* operations.
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*
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* </pre>
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*
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*****************************************************************************/
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#ifndef XAXIDMA_HW_H_ /* prevent circular inclusions */
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#define XAXIDMA_HW_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "xil_types.h"
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#include "xil_io.h"
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/************************** Constant Definitions *****************************/
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/** @name DMA Transfer Direction
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* @{
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*/
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#define XAXIDMA_DMA_TO_DEVICE 0x00
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#define XAXIDMA_DEVICE_TO_DMA 0x01
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/** @name Buffer Descriptor Alignment
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* @{
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*/
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#define XAXIDMA_BD_MINIMUM_ALIGNMENT 0x40 /**< Minimum byte alignment
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requirement for descriptors to
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satisfy both hardware/software
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needs */
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/*@}*/
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/** @name Micro DMA Buffer Address Alignment
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* @{
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*/
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#define XAXIDMA_MICROMODE_MIN_BUF_ALIGN 0xFFF /**< Minimum byte alignment
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requirement for buffer address
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in Micro DMA mode */
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/*@}*/
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/** @name Maximum transfer length
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* This is determined by hardware
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* @{
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*/
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#define XAXIDMA_MAX_TRANSFER_LEN 0x7FFFFF /* Max length hw supports */
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#define XAXIDMA_MCHAN_MAX_TRANSFER_LEN 0x00FFFF /* Max length MCDMA
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hw supports */
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/*@}*/
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/* Register offset definitions. Register accesses are 32-bit.
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*/
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/** @name Device registers
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* Register sets on TX and RX channels are identical
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* @{
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*/
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#define XAXIDMA_TX_OFFSET 0x00000000 /**< TX channel registers base
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* offset */
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#define XAXIDMA_RX_OFFSET 0x00000030 /**< RX channel registers base
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* offset */
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/* This set of registers are applicable for both channels. Add
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* XAXIDMA_TX_OFFSET to get to TX channel, and XAXIDMA_RX_OFFSET to get to RX
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* channel
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*/
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#define XAXIDMA_CR_OFFSET 0x00000000 /**< Channel control */
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#define XAXIDMA_SR_OFFSET 0x00000004 /**< Status */
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#define XAXIDMA_CDESC_OFFSET 0x00000008 /**< Current descriptor pointer */
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#define XAXIDMA_CDESC_MSB_OFFSET 0x0000000C /**< Current descriptor pointer */
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#define XAXIDMA_TDESC_OFFSET 0x00000010 /**< Tail descriptor pointer */
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#define XAXIDMA_TDESC_MSB_OFFSET 0x00000014 /**< Tail descriptor pointer */
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#define XAXIDMA_SRCADDR_OFFSET 0x00000018 /**< Simple mode source address
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pointer */
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#define XAXIDMA_SRCADDR_MSB_OFFSET 0x0000001C /**< Simple mode source address
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pointer */
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#define XAXIDMA_DESTADDR_OFFSET 0x00000018 /**< Simple mode destination address pointer */
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#define XAXIDMA_DESTADDR_MSB_OFFSET 0x0000001C /**< Simple mode destination address pointer */
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#define XAXIDMA_BUFFLEN_OFFSET 0x00000028 /**< Tail descriptor pointer */
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#define XAXIDMA_SGCTL_OFFSET 0x0000002c /**< SG Control Register */
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/** Multi-Channel DMA Descriptor Offsets **/
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#define XAXIDMA_RX_CDESC0_OFFSET 0x00000040 /**< Rx Current Descriptor 0 */
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#define XAXIDMA_RX_CDESC0_MSB_OFFSET 0x00000044 /**< Rx Current Descriptor 0 */
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#define XAXIDMA_RX_TDESC0_OFFSET 0x00000048 /**< Rx Tail Descriptor 0 */
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#define XAXIDMA_RX_TDESC0_MSB_OFFSET 0x0000004C /**< Rx Tail Descriptor 0 */
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#define XAXIDMA_RX_NDESC_OFFSET 0x00000020 /**< Rx Next Descriptor Offset */
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/*@}*/
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/** @name Bitmasks of XAXIDMA_CR_OFFSET register
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* @{
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*/
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#define XAXIDMA_CR_RUNSTOP_MASK 0x00000001 /**< Start/stop DMA channel */
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#define XAXIDMA_CR_RESET_MASK 0x00000004 /**< Reset DMA engine */
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#define XAXIDMA_CR_KEYHOLE_MASK 0x00000008 /**< Keyhole feature */
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#define XAXIDMA_CR_CYCLIC_MASK 0x00000010 /**< Cyclic Mode */
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/*@}*/
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/** @name Bitmasks of XAXIDMA_SR_OFFSET register
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*
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* This register reports status of a DMA channel, including
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* run/stop/idle state, errors, and interrupts (note that interrupt
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* masks are shared with XAXIDMA_CR_OFFSET register, and are defined
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* in the _IRQ_ section.
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*
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* The interrupt coalescing threshold value and delay counter value are
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* also shared with XAXIDMA_CR_OFFSET register, and are defined in a
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* later section.
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* @{
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*/
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#define XAXIDMA_HALTED_MASK 0x00000001 /**< DMA channel halted */
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#define XAXIDMA_IDLE_MASK 0x00000002 /**< DMA channel idle */
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#define XAXIDMA_ERR_INTERNAL_MASK 0x00000010 /**< Datamover internal
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* err */
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#define XAXIDMA_ERR_SLAVE_MASK 0x00000020 /**< Datamover slave err */
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#define XAXIDMA_ERR_DECODE_MASK 0x00000040 /**< Datamover decode
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* err */
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#define XAXIDMA_ERR_SG_INT_MASK 0x00000100 /**< SG internal err */
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#define XAXIDMA_ERR_SG_SLV_MASK 0x00000200 /**< SG slave err */
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#define XAXIDMA_ERR_SG_DEC_MASK 0x00000400 /**< SG decode err */
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#define XAXIDMA_ERR_ALL_MASK 0x00000770 /**< All errors */
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/** @name Bitmask for interrupts
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* These masks are shared by XAXIDMA_CR_OFFSET register and
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* XAXIDMA_SR_OFFSET register
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* @{
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*/
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#define XAXIDMA_IRQ_IOC_MASK 0x00001000 /**< Completion intr */
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#define XAXIDMA_IRQ_DELAY_MASK 0x00002000 /**< Delay interrupt */
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#define XAXIDMA_IRQ_ERROR_MASK 0x00004000 /**< Error interrupt */
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#define XAXIDMA_IRQ_ALL_MASK 0x00007000 /**< All interrupts */
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/*@}*/
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/** @name Bitmask and shift for delay and coalesce
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* These masks are shared by XAXIDMA_CR_OFFSET register and
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* XAXIDMA_SR_OFFSET register
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* @{
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*/
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#define XAXIDMA_DELAY_MASK 0xFF000000 /**< Delay timeout
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* counter */
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#define XAXIDMA_COALESCE_MASK 0x00FF0000 /**< Coalesce counter */
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#define XAXIDMA_DELAY_SHIFT 24
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#define XAXIDMA_COALESCE_SHIFT 16
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/*@}*/
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/* Buffer Descriptor (BD) definitions
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*/
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/** @name Buffer Descriptor offsets
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* USR* fields are defined by higher level IP.
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* setup for EMAC type devices. The first 13 words are used by hardware.
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* All words after the 13rd word are for software use only.
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* @{
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*/
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#define XAXIDMA_BD_NDESC_OFFSET 0x00 /**< Next descriptor pointer */
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#define XAXIDMA_BD_NDESC_MSB_OFFSET 0x04 /**< Next descriptor pointer */
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#define XAXIDMA_BD_BUFA_OFFSET 0x08 /**< Buffer address */
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#define XAXIDMA_BD_BUFA_MSB_OFFSET 0x0C /**< Buffer address */
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#define XAXIDMA_BD_MCCTL_OFFSET 0x10 /**< Multichannel Control Fields */
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#define XAXIDMA_BD_STRIDE_VSIZE_OFFSET 0x14 /**< 2D Transfer Sizes */
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#define XAXIDMA_BD_CTRL_LEN_OFFSET 0x18 /**< Control/buffer length */
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#define XAXIDMA_BD_STS_OFFSET 0x1C /**< Status */
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#define XAXIDMA_BD_USR0_OFFSET 0x20 /**< User IP specific word0 */
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#define XAXIDMA_BD_USR1_OFFSET 0x24 /**< User IP specific word1 */
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#define XAXIDMA_BD_USR2_OFFSET 0x28 /**< User IP specific word2 */
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#define XAXIDMA_BD_USR3_OFFSET 0x2C /**< User IP specific word3 */
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#define XAXIDMA_BD_USR4_OFFSET 0x30 /**< User IP specific word4 */
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#define XAXIDMA_BD_ID_OFFSET 0x34 /**< Sw ID */
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#define XAXIDMA_BD_HAS_STSCNTRL_OFFSET 0x38 /**< Whether has stscntrl strm */
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#define XAXIDMA_BD_HAS_DRE_OFFSET 0x3C /**< Whether has DRE */
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#define XAXIDMA_BD_ADDRLEN_OFFSET 0x40 /**< Check for BD Addr */
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#define XAXIDMA_BD_HAS_DRE_MASK 0xF00 /**< Whether has DRE mask */
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#define XAXIDMA_BD_WORDLEN_MASK 0xFF /**< Whether has DRE mask */
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#define XAXIDMA_BD_HAS_DRE_SHIFT 8 /**< Whether has DRE shift */
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#define XAXIDMA_BD_WORDLEN_SHIFT 0 /**< Whether has DRE shift */
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#define XAXIDMA_BD_START_CLEAR 8 /**< Offset to start clear */
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#define XAXIDMA_BD_BYTES_TO_CLEAR 48 /**< BD specific bytes to be
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* cleared */
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#define XAXIDMA_BD_NUM_WORDS 20U /**< Total number of words for
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* one BD*/
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#define XAXIDMA_BD_HW_NUM_BYTES 52 /**< Number of bytes hw used */
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/* The offset of the last app word.
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*/
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#define XAXIDMA_LAST_APPWORD 4
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/*@}*/
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#define XAXIDMA_DESC_LSB_MASK (0xFFFFFFC0U) /**< LSB Address mask */
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/** @name Bitmasks of XAXIDMA_BD_CTRL_OFFSET register
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* @{
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*/
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#define XAXIDMA_BD_CTRL_TXSOF_MASK 0x08000000 /**< First tx packet */
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#define XAXIDMA_BD_CTRL_TXEOF_MASK 0x04000000 /**< Last tx packet */
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#define XAXIDMA_BD_CTRL_ALL_MASK 0x0C000000 /**< All control bits */
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/*@}*/
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/** @name Bitmasks of XAXIDMA_BD_STS_OFFSET register
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* @{
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*/
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#define XAXIDMA_BD_STS_COMPLETE_MASK 0x80000000 /**< Completed */
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#define XAXIDMA_BD_STS_DEC_ERR_MASK 0x40000000 /**< Decode error */
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#define XAXIDMA_BD_STS_SLV_ERR_MASK 0x20000000 /**< Slave error */
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#define XAXIDMA_BD_STS_INT_ERR_MASK 0x10000000 /**< Internal err */
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#define XAXIDMA_BD_STS_ALL_ERR_MASK 0x70000000 /**< All errors */
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#define XAXIDMA_BD_STS_RXSOF_MASK 0x08000000 /**< First rx pkt */
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#define XAXIDMA_BD_STS_RXEOF_MASK 0x04000000 /**< Last rx pkt */
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#define XAXIDMA_BD_STS_ALL_MASK 0xFC000000 /**< All status bits */
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/*@}*/
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/** @name Bitmasks and shift values for XAXIDMA_BD_MCCTL_OFFSET register
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* @{
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*/
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#define XAXIDMA_BD_TDEST_FIELD_MASK 0x0000000F
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#define XAXIDMA_BD_TID_FIELD_MASK 0x00000F00
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#define XAXIDMA_BD_TUSER_FIELD_MASK 0x000F0000
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#define XAXIDMA_BD_ARCACHE_FIELD_MASK 0x0F000000
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#define XAXIDMA_BD_ARUSER_FIELD_MASK 0xF0000000
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#define XAXIDMA_BD_TDEST_FIELD_SHIFT 0
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#define XAXIDMA_BD_TID_FIELD_SHIFT 8
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#define XAXIDMA_BD_TUSER_FIELD_SHIFT 16
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#define XAXIDMA_BD_ARCACHE_FIELD_SHIFT 24
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#define XAXIDMA_BD_ARUSER_FIELD_SHIFT 28
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/** @name Bitmasks and shift values for XAXIDMA_BD_STRIDE_VSIZE_OFFSET register
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* @{
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*/
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#define XAXIDMA_BD_STRIDE_FIELD_MASK 0x0000FFFF
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#define XAXIDMA_BD_VSIZE_FIELD_MASK 0xFFF80000
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#define XAXIDMA_BD_STRIDE_FIELD_SHIFT 0
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#define XAXIDMA_BD_VSIZE_FIELD_SHIFT 19
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define XAxiDma_In32 Xil_In32
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#define XAxiDma_Out32 Xil_Out32
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/*****************************************************************************/
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/**
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*
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* Read the given register.
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*
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* @param BaseAddress is the base address of the device
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* @param RegOffset is the register offset to be read
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*
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* @return The 32-bit value of the register
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*
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* @note
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* C-style signature:
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* u32 XAxiDma_ReadReg(u32 BaseAddress, u32 RegOffset)
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315 |
|
|
*
|
316 |
|
|
******************************************************************************/
|
317 |
|
|
#define XAxiDma_ReadReg(BaseAddress, RegOffset) \
|
318 |
|
|
XAxiDma_In32((BaseAddress) + (RegOffset))
|
319 |
|
|
|
320 |
|
|
/*****************************************************************************/
|
321 |
|
|
/**
|
322 |
|
|
*
|
323 |
|
|
* Write the given register.
|
324 |
|
|
*
|
325 |
|
|
* @param BaseAddress is the base address of the device
|
326 |
|
|
* @param RegOffset is the register offset to be written
|
327 |
|
|
* @param Data is the 32-bit value to write to the register
|
328 |
|
|
*
|
329 |
|
|
* @return None.
|
330 |
|
|
*
|
331 |
|
|
* @note
|
332 |
|
|
* C-style signature:
|
333 |
|
|
* void XAxiDma_WriteReg(u32 BaseAddress, u32 RegOffset, u32 Data)
|
334 |
|
|
*
|
335 |
|
|
******************************************************************************/
|
336 |
|
|
#define XAxiDma_WriteReg(BaseAddress, RegOffset, Data) \
|
337 |
|
|
XAxiDma_Out32((BaseAddress) + (RegOffset), (Data))
|
338 |
|
|
|
339 |
|
|
#ifdef __cplusplus
|
340 |
|
|
}
|
341 |
|
|
#endif
|
342 |
|
|
|
343 |
|
|
#endif
|
344 |
|
|
/** @} */
|