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Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 14

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Line No. Rev Author Line
1 4 ale500
Changelong
2
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3 14 ale500
16.07.14
4
--------
5
- decoders.v : decode of some opcodes modified to improve size & speed
6
- MC6809_cpu.v : Removed dec_o_optype and added single wire signals for common opcodes
7 11 ale500
 
8 12 ale500
06.07.14
9
--------
10
- decoders.v : fixed missing left/dest paths for sex
11
- alu16.v : fixed sex, mul, c flag for shifts, ror
12
- MC6809_cpu.v : fixed indirect indexed
13 13 ale500
 
14 12 ale500
05.07.14
15
--------
16
- decoders.v : fixed missing left/dest paths for daa
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- alu16.v : fixed daa, h flag store and generation
18
 
19
04.07.14
20
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- decoders.v : fixed page 2&3 operands, jmp, cmp
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- MC6809_cpu.v : fixed jmp
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24
 
25 11 ale500
02.07.14
26
--------
27
- decoders.v : fixed dec, fixed inc (didn't read before write), fixed clr for ea direct, extended, indexed
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               added a path with the decoded sources/destination for the decode stage
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- MC6809_cpu.v : implemented two paths for source/dest from the decoder
30
- rumsim.bat : added batch file for simulation
31
 
32 10 ale500
22.06.14
33
--------
34 4 ale500
 
35 10 ale500
- decoders.v : fixed wrong left/right/dest paths for several extended, page 2, 3 opcodes.
36
- MC6809_cpu.v : fixed jsr extended, indexed
37
 
38
06.02.14
39
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40
 
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- regblock.v : dropped double write of PC
42
- MC6809_cpu.v : fixed loading of new PC from reset vector, rel8 displacement calculation.
43
 
44 9 ale500
06.01.14
45
--------
46
 
47
- decoders.v : added registered outputs for the source/destination address registers
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49 7 ale500
05.01.14
50
--------
51
 
52
- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC
53 9 ale500
- decoders.v : fixed destination for BIT
54
- defs.v : reduced the number of ALU opcodes
55
- alu16.v : reduced the number of ALU opcodes, fused BIT with AND, CMP with SUB
56 7 ale500
 
57 6 ale500
01.01.14
58
--------
59
 
60
- alu16.v : the alu has been bronken in two units
61
- MC6809_cpu.v : added CWAI states and decoding
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- decodres.v : added CWAI decoding
63
 
64 5 ale500
31.12.13
65
--------
66
 
67
- Implemented TFR/EXG
68
- MC6809_cpu.v: Added one more state to execute TFR or EXG
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- decoders.v: added source/dest for TFR and EXG
70
- regblock.v : added second write path to the registers for TFR&EXG
71
- defs.v defined new SEQ_TFREXG for tfr&exg execution
72
 
73 4 ale500
30.12.13
74
--------
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- Fixed increment/decrement of the stack pointer
77
 
78
- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states
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                Added eamem source to the left alu data path to check for zero in the ea (leax/leay)
80
 
81
29.12.13
82
--------
83
 
84
- Fixed wrong byte in SEQ_MEM_WRITE_H
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- Fixed unaffected Z flag for LEAX/LEAY
86
- Moved increment of pc from FETCH_2 to FETCH_1
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- Fixed CMPA/CMPB/CMPX, they don't write a register back
88
- Fixed late write of pc
89
 
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- decoders.v: Merged separated write_dest_x into one wire
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              Added a source_size wire to indicate the width of the source argument
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              Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY
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94
- MC6809_cpu.v: Dropped checks for source size from the individual states and moved
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                into SEQ_MEM_READ_H
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                Merged write flags into k_dest_write
97
 
98
- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected
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100
- defs.v : added a LEA define to the ALU section

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