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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 7

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Changelong
----------
 
05.01.14
--------
 
- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC
 
01.01.14
--------
 
- alu16.v : the alu has been bronken in two units
- MC6809_cpu.v : added CWAI states and decoding
- decodres.v : added CWAI decoding
 
31.12.13
--------
 
- Implemented TFR/EXG
- MC6809_cpu.v: Added one more state to execute TFR or EXG
- decoders.v: added source/dest for TFR and EXG
- regblock.v : added second write path to the registers for TFR&EXG
- defs.v defined new SEQ_TFREXG for tfr&exg execution
 
30.12.13
--------
 
- Fixed increment/decrement of the stack pointer
 
- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states
                Added eamem source to the left alu data path to check for zero in the ea (leax/leay)
 
29.12.13
--------
 
- Fixed wrong byte in SEQ_MEM_WRITE_H
- Fixed unaffected Z flag for LEAX/LEAY
- Moved increment of pc from FETCH_2 to FETCH_1
- Fixed CMPA/CMPB/CMPX, they don't write a register back
- Fixed late write of pc
 
- decoders.v: Merged separated write_dest_x into one wire
              Added a source_size wire to indicate the width of the source argument
              Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY
 
- MC6809_cpu.v: Dropped checks for source size from the individual states and moved
                into SEQ_MEM_READ_H
                Merged write flags into k_dest_write
 
- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected
 
- defs.v : added a LEA define to the ALU section

Line No.	Rev	Author	Line
1	4	ale500	`Changelong`
2			`----------`
3
4	7	ale500	`05.01.14`
5			`--------`
6
7			`- MC6809_cpu.v : fixed exg (wrong source), implemented SYNC`
8
9	6	ale500	`01.01.14`
10			`--------`
11
12			`- alu16.v : the alu has been bronken in two units`
13			`- MC6809_cpu.v : added CWAI states and decoding`
14			`- decodres.v : added CWAI decoding`
15
16	5	ale500	`31.12.13`
17			`--------`
18
19			`- Implemented TFR/EXG`
20			`- MC6809_cpu.v: Added one more state to execute TFR or EXG`
21			`- decoders.v: added source/dest for TFR and EXG`
22			`- regblock.v : added second write path to the registers for TFR&EXG`
23			`- defs.v defined new SEQ_TFREXG for tfr&exg execution`
24
25	4	ale500	`30.12.13`
26			`--------`
27
28			`- Fixed increment/decrement of the stack pointer`
29
30			`- MC6809_cpu.v: Push/pull increment/decrement the stack pointr in their own states`
31			`Added eamem source to the left alu data path to check for zero in the ea (leax/leay)`
32
33			`29.12.13`
34			`--------`
35
36			`- Fixed wrong byte in SEQ_MEM_WRITE_H`
37			`- Fixed unaffected Z flag for LEAX/LEAY`
38			`- Moved increment of pc from FETCH_2 to FETCH_1`
39			`- Fixed CMPA/CMPB/CMPX, they don't write a register back`
40			`- Fixed late write of pc`
41
42			`- decoders.v: Merged separated write_dest_x into one wire`
43			`Added a source_size wire to indicate the width of the source argument`
44			`Added the recognition of LEA as an alu mnemonic to modify the Z flag for LEAX/LEAY`
45
46			`- MC6809_cpu.v: Dropped checks for source size from the individual states and moved`
47			`into SEQ_MEM_READ_H`
48			`Merged write flags into k_dest_write`
49
50			`- alu.v: Added a LEA instruction for LEAX/LEAY where only the Z flag will be affected`
51
52			`- defs.v : added a LEA define to the ALU section`

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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [Changelog.txt] - Blame information for rev 7