URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Blame information for rev 10

Go to most recent revision | Details | Compare with Previous | View Log


/*
 * (c) 2013 Alejandro Paz
 *
 *
 * An alu core
 *
 * ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL
 *
 *
 *
 */
`include "defs.v"
 
 
module alu(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        input wire sz_in, /* size, low 8 bit, high 16 bit */
        output reg [15:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire [7:0] ccr8_out, q8_out;
wire [15:0] q16_out;
wire [3:0] ccr16_out;
 
reg [15:0] ra_in, rb_in;
reg [4:0] rop_in;
alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);
alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_out, ccr16_out);
 
always @(posedge clk_in)
        begin
                ra_in <= a_in;
                rb_in <= b_in;
                rop_in <= opcode_in;
        end
 
always @(*)
        begin
                if (sz_in)
                        begin
                                q_out = q16_out;
                                CCRo = { CCR[7:4], ccr16_out };
                        end
                else
                        begin
                                q_out = { 8'h0, q8_out };
                                CCRo = ccr8_out;
                        end
        end
 
 
endmodule
/**
 * Simple 3 functions logic
 *
 */
module logic8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out /* ALU result */
        );
 
always @(*)
        begin
                case (opcode_in)
                        2'b00: q_out = b_in;
                        2'b01: q_out = a_in & b_in;
                        2'b10: q_out = a_in | b_in;
                        2'b11: q_out = a_in ^ b_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire half_c_in,
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out,
        output reg half_c_out
        );
 
wire carry;
assign carry = opcode_in[1] ? carry_in:1'b0;
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry }; // ADD/ADC
                        1'b1: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry }; // SUB/SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) | ((~a_in[7]) & (~b_in[7]) & q_out[7]);
                        1'b1: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) | ((~a_in[7]) & b_in[7] & q_out[7]);
                endcase
        end
 
always @(*)
        begin
                case (opcode_in[0])
                        1'b0: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) | ((~a_in[3]) & (~b_in[3]) & q_out[3]);
                        1'b1: half_c_out = half_c_in;
                endcase
        end
 
endmodule
 
/**
 * Simple ADD/SUB module
 *
 */
module arith16(
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire carry_in, /* condition code register */
        input wire [1:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg carry_out,
        output reg overflow_out
        );
always @(*)
        begin
                case (opcode_in)
                        2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD
                        2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB
                        2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC
                        2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC
                endcase
        end
 
always @(*)
        begin
                case (opcode_in)
                        2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) | ((~a_in[15]) & (~b_in[15]) & q_out[7]);
                        2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) | ((~a_in[15]) & b_in[15] & q_out[7]);
                endcase
        end
 
endmodule
 
module shift8(
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire carry_in, /* condition code register */
        input wire overflow_in, /* condition code register */
        input wire [2:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output wire carry_out,
        output reg overflow_out
        );
 
always @(*)
        begin
                q_out = { a_in[7], a_in[7:1] }; // ASR
                case (opcode_in)
                        3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR
                        3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL
                        3'b010: q_out = { carry_in, a_in[7:1] }; // ROR
                        3'b011: q_out = { a_in[6:0], carry_in }; // ROL
                        3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR
                endcase
        end
 
always @(*)
        begin
                overflow_out = overflow_in;
                case (opcode_in)
                        3'b000: overflow_out = overflow_in; // LSR
                        3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL
                        3'b010: overflow_out = overflow_in; // ROR
                        3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL
                        3'b100: overflow_out = overflow_in; // ASR
                endcase
        end
 
assign carry_out = opcode_in[0] ? a_in[0]:a_in[7];
 
endmodule
 
 
module alu8(
        input wire clk_in,
        input wire [7:0] a_in,
        input wire [7:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [7:0] q_out, /* ALU result */
        output reg [7:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in, h_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
assign h_in = CCR[5]; /* halb-carry flag */
 
wire [7:0] com8_r, neg8_r;
wire [3:0] daa8l_r, daa8h_r;
wire daa_lnm9;
 
wire [7:0] com8_w, neg8_w;
 
wire ccom8_r, cneg8_r, cdaa8_r;
 
wire vcom8_r, vneg8_r;
 
assign com8_w = ~a_in[7:0];
assign neg8_w = 8'h0 - a_in[7:0];
                // COM
assign com8_r = com8_w;
assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;
assign vcom8_r = 1'b0;
                // NEG
assign neg8_r = neg8_w;
assign cneg8_r = neg8_w[7] | neg8_w[6] | neg8_w[5] | neg8_w[4] | neg8_w[3] | neg8_w[2] | neg8_w[1] | neg8_w[0];
assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);
                // DAA
assign daa_lnm9 = (a_in[3:0] > 9);
assign daa8l_r = (daa_lnm9 | h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];
assign daa8h_r = ((a_in[7:4] > 9) || (c_in == 1'b1) || (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];
assign cdaa8_r = daa8h_r < a_in[7:4];
 
reg c8, h8, n8, v8, z8;
reg [7:0] q8;
 
wire [7:0] logic_q, arith_q, shift_q;
wire arith_c, arith_v, arith_h;
wire shift_c, shift_v;
 
logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);
arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);
shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);
 
always @(*)
        begin
                q8 = 8'h0;
                c8 = c_in;
                h8 = h_in;
                v8 = v_in;
                case (opcode_in)
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q8 = arith_q;
                                        c8 = arith_c;
                                        v8 = arith_v;
                                        h8 = arith_h;
                                end
                        `COM:
                                begin
                                        q8 = com8_r;
                                        c8 = com8_r;
                                        v8 = vcom8_r;
                                end
                        `NEG:
                                begin
                                        q8 = neg8_r;
                                        c8 = cneg8_r;
                                        v8 = vneg8_r;
                                end
                        `LSR, `LSL, `ROL, `ROR,`ASR:
                                begin
                                        q8 = shift_q;
                                        c8 = shift_c;
                                        v8 = shift_v;
                                end
                        `AND, `OR, `EOR, `LD:
                                begin
                                        q8 = logic_q;
                                        v8 = 1'b0;
                                        end
                        `DAA:
                                begin // V is undefined, so we don't touch it
                                        q8 = { daa8h_r, daa8l_r };
                                        c8 = cdaa8_r;
                                end
                        `ST:
                                begin
                                        q8 = a_in[7:0];
                                end
                endcase
        end
 
reg [7:0] regq8;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq8 <= q8;
        end
 
always @(*)
        begin
                q_out[7:0] = q8; //regq8;
                case (opcode_in)
                        `ORCC:
                                CCRo = CCR | b_in[7:0];
                        `ANDCC:
                                CCRo = CCR & b_in[7:0];
                        default:
                                CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };
                endcase
        end
 
initial
        begin
        end
endmodule
 
/* ALU for 16 bit operations */
module alu16(
        input wire clk_in,
        input wire [15:0] a_in,
        input wire [15:0] b_in,
        input wire [7:0] CCR, /* condition code register */
        input wire [4:0] opcode_in, /* ALU opcode */
        output reg [15:0] q_out, /* ALU result */
        output reg [3:0] CCRo
        );
 
wire c_in, n_in, v_in, z_in;
assign c_in = CCR[0]; /* carry flag */
assign n_in = CCR[3]; /* neg flag */
assign v_in = CCR[1]; /* overflow flag */
assign z_in = CCR[2]; /* zero flag */
 
`ifdef HD6309
wire [15:0] com16_r, neg16_r;
wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;
 
wire [15:0] com16_w, neg16_w;
wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;
 
wire ccom16_r, cneg16_r;
wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;
 
wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;
wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;
 
assign com16_w = ~a_in[15:0];
assign neg16_w = 16'h0 - a_in[15:0];
assign asr16_w = { a_in[15], a_in[15:1] };
assign shr16_w = { 1'b0, a_in[15:1] };
assign shl16_w = { a_in[14:0], 1'b0 };
assign ror16_w = { c_in, a_in[15:1] };
assign rol16_w = { a_in[14:0], c_in };
assign and16_w = a_in[15:0] & b_in[15:0];
assign or16_w = a_in[15:0] | b_in[15:0];
assign eor16_w = a_in[15:0] ^ b_in[15:0];
 
// COM
assign com16_r = com16_w;
assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;
assign vcom16_r = 1'b0;
                // NEG
assign neg16_r = neg16_w;
assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);
assign cneg16_r = neg16_w[15] | neg16_w[14] | neg16_w[13] | neg16_w[12] | neg16_w[11] | neg16_w[10] | neg16_w[9] & neg16_w[8] | neg16_w[7] | neg16_w[6] | neg16_w[5] | neg16_w[4] | neg16_w[3] | neg16_w[2] | neg16_w[1] | neg16_w[0];
                // ASR
assign asr16_r = asr16_w;
assign casr16_r = a_in[0];
assign vasr16_r = a_in[0] ^ asr16_w[15];
                // SHR
assign shr16_r = shr16_w;
assign cshr16_r = a_in[0];
assign vshr16_r = a_in[0] ^ shr16_w[15];
                // SHL
assign shl16_r = shl16_w;
assign cshl16_r = a_in[15];
assign vshl16_r = a_in[15] ^ shl16_w[15];
                // ROR
assign ror16_r = ror16_w;
assign cror16_r = a_in[0];
assign vror16_r = a_in[0] ^ ror16_w[15];
                // ROL
assign rol16_r = rol16_w;
assign crol16_r = a_in[15];
assign vrol16_r = a_in[15] ^ rol16_w[15];
                // AND
assign and16_r = and16_w;
assign cand16_r = c_in;
assign vand16_r = 1'b0;
                // OR
assign or16_r = or16_w;
                // EOR
assign eor16_r = eor16_w;
`endif
 
wire [15:0] q16_mul;
 
mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);
 
reg c16, n16, v16, z16;
reg [15:0] q16;
 
wire [15:0] arith_q;
wire arith_c, arith_v, arith_h;
 
arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);
 
always @(*)
        begin
                q16 = 16'h0;
                c16 = c_in;
                v16 = v_in;
                case (opcode_in)
                        `ADD, `ADC, `SUB, `SBC:
                                begin
                                        q16 = arith_q;
                                        c16 = arith_c;
                                        v16 = arith_v;
                                end
`ifdef HD6309
                        `COM:
                                begin
                                        q16 = com16_r;
                                        c16 = ccom16_r;
                                        v16 = vcom16_r;
                                end
                        `NEG:
                                begin
                                        q16 = neg16_r;
                                        c16 = cneg16_r;
                                        v16 = vneg16_r;
                                end
                        `ASR:
                                begin
                                        q16 = asr16_r;
                                        c16 = casr16_r;
                                        v16 = vasr16_r;
                                end
                        `LSR:
                                begin
                                        q16 = shr16_r;
                                        c16 = cshr16_r;
                                        v16 = vshr16_r;
                                end
                        `LSL:
                                begin
                                        q16 = shl16_r;
                                        c16 = cshl16_r;
                                        v16 = vshl16_r;
                                end
                        `ROR:
                                begin
                                        q16 = ror16_r;
                                        c16 = cror16_r;
                                        v16 = vror16_r;
                                end
                        `ROL:
                                begin
                                        q16 = rol16_r;
                                        c16 = crol16_r;
                                        v16 = vrol16_r;
                                end
                        `AND:
                                begin
                                        q16 = and16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                        end
                        `OR:
                                begin
                                        q16 = or16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
                        `EOR:
                                begin
                                        q16 = eor16_r;
                                        c16 = cand16_r;
                                        v16 = vand16_r;
                                end
`endif
                        `MUL:
                                begin
                                        q16 = q16_mul;
                                        c16 = q16_mul[7];
                                end
                        `LD:
                                begin
                                        v16 = 0;
                                        q16 = b_in[15:0];
                                end
                        `ST:
                                begin
                                        q16 = a_in[15:0];
                                end
                        `SEXT: // sign extend
                                begin
                                        q16 = { b_in[7] ? 8'hff:8'h00, b_in[7:0] };
                                end
                        `LEA:
                                begin
                                        q16 = a_in[15:0];
                                end
                endcase
        end
 
reg [15:0] regq16;
reg reg_n_in, reg_z_in;
/* register before second mux */
always @(posedge clk_in)
        begin
                regq16 <= q16;
                reg_n_in <= n_in;
                reg_z_in <= z_in;
        end
 
/* Negative & zero flags */
always @(*)
        begin
                n16 = q16[15];
                z16 = q16 == 16'h0;
                case (opcode_in)
                        `ADD:
                                begin
                                end
                        `ADC:
                                begin
                                end
                        `SUB: // for CMP no register result is written back
                                begin
                                end
                        `SBC:
                                begin
                                end
                        `COM:
                                begin
                                end
                        `NEG:
                                begin
                                end
                        `ASR:
                                begin
                                end
                        `LSR:
                                begin
                                end
                        `LSL:
                                begin
                                end
                        `ROR:
                                begin
                                end
                        `ROL:
                                begin
                                end
                        `AND:
                                begin
                                end
                        `OR:
                                begin
                                end
                        `EOR:
                                begin
                                end
                        `MUL:
                                begin
                                        n16 = reg_n_in;
                                end
                        `LD:
                                begin
                                end
                        `ST:
                                begin
                                end
                        `SEXT: // sign extend
                                begin
                                        n16 = reg_n_in;
                                        z16 = reg_z_in;
                                end
                        `LEA: // only Z will be affected
                                begin
                                        n16 = reg_n_in;
                                end
                endcase
        end
 
 
always @(*)
        begin
                q_out = q16;
                CCRo = { n16, z16, v16, c16 };
        end
 
endmodule
 
module mul8x8(
        input wire clk_in,
        input wire [7:0] a,
        input wire [7:0] b,
        output wire [15:0] q
        );
 
reg [15:0] pipe0, pipe1;//, pipe2, pipe3;
assign q = pipe1;
 
always @(posedge clk_in)
        begin
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0) +
                         (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0);
                pipe1 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) +
                         (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe0;
                /*
                pipe0 <= (a[0] ? {8'h0, b}:16'h0) + (a[1] ? { 7'h0, b, 1'h0}:16'h0);
                pipe1 <= (a[2] ? {6'h0, b, 2'h0}:16'h0) + (a[3] ? { 5'h0, b, 3'h0}:16'h0) + pipe0;
                pipe2 <= (a[4] ? {4'h0, b, 4'h0}:16'h0) + (a[5] ? { 3'h0, b, 5'h0}:16'h0) + pipe1;
                pipe3 <= (a[6] ? {2'h0, b, 6'h0}:16'h0) + (a[7] ? { 1'h0, b, 7'h0}:16'h0) + pipe2;
                */
        end
 
endmodule

Line No.	Rev	Author	Line
1	4	ale500	`/*`
2			`* (c) 2013 Alejandro Paz`
3			`*`
4			`*`
5			`* An alu core`
6			`*`
7			`* ADD, ADC, DAA, SUB, SBC, COM, NEG, CMP, ASR, ASL, ROR, ROL, RCR, RCL`
8			`*`
9			`*`
10			`*`
11			`*/`
12			`include "defs.v"
13	6	ale500
14
15			`module alu(`
16			`input wire clk_in,`
17	4	ale500	`input wire [15:0] a_in,`
18			`input wire [15:0] b_in,`
19			`input wire [7:0] CCR, /* condition code register */`
20			`input wire [4:0] opcode_in, /* ALU opcode */`
21			`input wire sz_in, /* size, low 8 bit, high 16 bit */`
22			`output reg [15:0] q_out, /* ALU result */`
23			`output reg [7:0] CCRo`
24			`);`
25	2	ale500
26	6	ale500	`wire [7:0] ccr8_out, q8_out;`
27			`wire [15:0] q16_out;`
28			`wire [3:0] ccr16_out;`
29
30			`reg [15:0] ra_in, rb_in;`
31	9	ale500	`reg [4:0] rop_in;`
32			`alu8 alu8(clk_in, ra_in[7:0], rb_in[7:0], CCR, rop_in, q8_out, ccr8_out);`
33			`alu16 alu16(clk_in, ra_in, rb_in, CCR, rop_in, q16_out, ccr16_out);`
34	6	ale500
35			`always @(posedge clk_in)`
36			`begin`
37			`ra_in <= a_in;`
38			`rb_in <= b_in;`
39	9	ale500	`rop_in <= opcode_in;`
40	6	ale500	`end`
41
42			`always @(*)`
43			`begin`
44			`if (sz_in)`
45			`begin`
46			`q_out = q16_out;`
47			`CCRo = { CCR[7:4], ccr16_out };`
48			`end`
49			`else`
50			`begin`
51			`q_out = { 8'h0, q8_out };`
52			`CCRo = ccr8_out;`
53			`end`
54			`end`
55	9	ale500
56	6	ale500
57			`endmodule`
58	9	ale500	`/**`
59			`* Simple 3 functions logic`
60			`*`
61			`*/`
62			`module logic8(`
63			`input wire [7:0] a_in,`
64			`input wire [7:0] b_in,`
65			`input wire [1:0] opcode_in, /* ALU opcode */`
66			`output reg [7:0] q_out /* ALU result */`
67			`);`
68	6	ale500
69	9	ale500	`always @(*)`
70			`begin`
71			`case (opcode_in)`
72			`2'b00: q_out = b_in;`
73			`2'b01: q_out = a_in & b_in;`
74			`2'b10: q_out = a_in \| b_in;`
75			`2'b11: q_out = a_in ^ b_in;`
76			`endcase`
77			`end`
78
79			`endmodule`
80
81			`/**`
82			`* Simple ADD/SUB module`
83			`*`
84			`*/`
85			`module arith8(`
86			`input wire [7:0] a_in,`
87			`input wire [7:0] b_in,`
88			`input wire carry_in, /* condition code register */`
89			`input wire half_c_in,`
90			`input wire [1:0] opcode_in, /* ALU opcode */`
91			`output reg [7:0] q_out, /* ALU result */`
92			`output reg carry_out,`
93			`output reg overflow_out,`
94			`output reg half_c_out`
95			`);`
96	10	ale500
97			`wire carry;`
98			`assign carry = opcode_in[1] ? carry_in:1'b0;`
99	9	ale500
100			`always @(*)`
101			`begin`
102	10	ale500	`case (opcode_in[0])`
103			`1'b0: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry }; // ADD/ADC`
104			`1'b1: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry }; // SUB/SBC`
105	9	ale500	`endcase`
106			`end`
107
108			`always @(*)`
109			`begin`
110	10	ale500	`case (opcode_in[0])`
111			`1'b0: overflow_out = (a_in[7] & b_in[7] & (~q_out[7])) \| ((~a_in[7]) & (~b_in[7]) & q_out[7]);`
112			`1'b1: overflow_out = (a_in[7] & (~b_in[7]) & (~q_out[7])) \| ((~a_in[7]) & b_in[7] & q_out[7]);`
113	9	ale500	`endcase`
114			`end`
115
116			`always @(*)`
117			`begin`
118	10	ale500	`case (opcode_in[0])`
119			`1'b0: half_c_out = (a_in[3] & b_in[3] & (~q_out[3])) \| ((~a_in[3]) & (~b_in[3]) & q_out[3]);`
120			`1'b1: half_c_out = half_c_in;`
121	9	ale500	`endcase`
122			`end`
123
124			`endmodule`
125
126			`/**`
127			`* Simple ADD/SUB module`
128			`*`
129			`*/`
130			`module arith16(`
131			`input wire [15:0] a_in,`
132			`input wire [15:0] b_in,`
133			`input wire carry_in, /* condition code register */`
134			`input wire [1:0] opcode_in, /* ALU opcode */`
135			`output reg [15:0] q_out, /* ALU result */`
136			`output reg carry_out,`
137			`output reg overflow_out`
138			`);`
139			`always @(*)`
140			`begin`
141			`case (opcode_in)`
142			`2'b00: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in }; // ADD`
143			`2'b01: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in }; // SUB`
144			`2'b10: { carry_out, q_out } = { 1'b0, a_in } + { 1'b0, b_in } + { 8'h0, carry_in }; // ADC`
145			`2'b11: { carry_out, q_out } = { 1'b0, a_in } - { 1'b0, b_in } - { 8'h0, carry_in }; // SBC`
146			`endcase`
147			`end`
148
149			`always @(*)`
150			`begin`
151			`case (opcode_in)`
152			`2'b00, 2'b10: overflow_out = (a_in[15] & b_in[15] & (~q_out[15])) \| ((~a_in[15]) & (~b_in[15]) & q_out[7]);`
153			`2'b01, 2'b11: overflow_out = (a_in[15] & (~b_in[15]) & (~q_out[15])) \| ((~a_in[15]) & b_in[15] & q_out[7]);`
154			`endcase`
155			`end`
156
157			`endmodule`
158
159			`module shift8(`
160			`input wire [7:0] a_in,`
161			`input wire [7:0] b_in,`
162			`input wire carry_in, /* condition code register */`
163			`input wire overflow_in, /* condition code register */`
164			`input wire [2:0] opcode_in, /* ALU opcode */`
165			`output reg [7:0] q_out, /* ALU result */`
166			`output wire carry_out,`
167			`output reg overflow_out`
168			`);`
169
170			`always @(*)`
171			`begin`
172			`q_out = { a_in[7], a_in[7:1] }; // ASR`
173			`case (opcode_in)`
174			`3'b000: q_out = { 1'b0, a_in[7:1] }; // LSR`
175			`3'b001: q_out = { a_in[6:0], 1'b0 }; // LSL`
176			`3'b010: q_out = { carry_in, a_in[7:1] }; // ROR`
177			`3'b011: q_out = { a_in[6:0], carry_in }; // ROL`
178			`3'b100: q_out = { a_in[7], a_in[7:1] }; // ASR`
179			`endcase`
180			`end`
181
182			`always @(*)`
183			`begin`
184			`overflow_out = overflow_in;`
185			`case (opcode_in)`
186			`3'b000: overflow_out = overflow_in; // LSR`
187			`3'b001: overflow_out = a_in[7] ^ a_in[6]; // LSL`
188			`3'b010: overflow_out = overflow_in; // ROR`
189			`3'b011: overflow_out = a_in[7] ^ a_in[6]; // ROL`
190			`3'b100: overflow_out = overflow_in; // ASR`
191			`endcase`
192			`end`
193
194			`assign carry_out = opcode_in[0] ? a_in[0]:a_in[7];`
195
196			`endmodule`
197
198
199	6	ale500	`module alu8(`
200			`input wire clk_in,`
201	9	ale500	`input wire [7:0] a_in,`
202			`input wire [7:0] b_in,`
203	6	ale500	`input wire [7:0] CCR, /* condition code register */`
204			`input wire [4:0] opcode_in, /* ALU opcode */`
205			`output reg [7:0] q_out, /* ALU result */`
206			`output reg [7:0] CCRo`
207			`);`
208
209			`wire c_in, n_in, v_in, z_in, h_in;`
210			`assign c_in = CCR[0]; /* carry flag */`
211			`assign n_in = CCR[3]; /* neg flag */`
212			`assign v_in = CCR[1]; /* overflow flag */`
213			`assign z_in = CCR[2]; /* zero flag */`
214			`assign h_in = CCR[5]; /* halb-carry flag */`
215
216	9	ale500	`wire [7:0] com8_r, neg8_r;`
217	6	ale500	`wire [3:0] daa8l_r, daa8h_r;`
218			`wire daa_lnm9;`
219
220	9	ale500	`wire [7:0] com8_w, neg8_w;`
221	6	ale500
222	9	ale500	`wire ccom8_r, cneg8_r, cdaa8_r;`
223	6	ale500
224	9	ale500	`wire vcom8_r, vneg8_r;`
225	6	ale500
226			`assign com8_w = ~a_in[7:0];`
227			`assign neg8_w = 8'h0 - a_in[7:0];`
228			`// COM`
229			`assign com8_r = com8_w;`
230			`assign ccom8_r = com8_w != 8'h0 ? 1'b1:1'b0;`
231			`assign vcom8_r = 1'b0;`
232			`// NEG`
233			`assign neg8_r = neg8_w;`
234			`assign cneg8_r = neg8_w[7] \| neg8_w[6] \| neg8_w[5] \| neg8_w[4] \| neg8_w[3] \| neg8_w[2] \| neg8_w[1] \| neg8_w[0];`
235			`assign vneg8_r = neg8_w[7] & (~neg8_w[6]) & (~neg8_w[5]) & (~neg8_w[4]) & (~neg8_w[3]) & (~neg8_w[2]) & (~neg8_w[1]) & (~neg8_w[0]);`
236			`// DAA`
237			`assign daa_lnm9 = (a_in[3:0] > 9);`
238			`assign daa8l_r = (daa_lnm9 \| h_in ) ? a_in[3:0] + 4'h6:a_in[3:0];`
239			`assign daa8h_r = ((a_in[7:4] > 9) \|\| (c_in == 1'b1) \|\| (a_in[7] & daa_lnm9)) ? a_in[7:4] + 4'h6:a_in[7:4];`
240			`assign cdaa8_r = daa8h_r < a_in[7:4];`
241
242			`reg c8, h8, n8, v8, z8;`
243			`reg [7:0] q8;`
244	9	ale500
245			`wire [7:0] logic_q, arith_q, shift_q;`
246			`wire arith_c, arith_v, arith_h;`
247			`wire shift_c, shift_v;`
248
249			`logic8 l8(a_in, b_in, opcode_in[1:0], logic_q);`
250			`arith8 a8(a_in, b_in, c_in, h_in, opcode_in[1:0], arith_q, arith_c, arith_v, arith_h);`
251			`shift8 s8(a_in, b_in, c_in, v_in, opcode_in[2:0], shift_q, shift_c, shift_v);`
252
253	6	ale500	`always @(*)`
254			`begin`
255			`q8 = 8'h0;`
256			`c8 = c_in;`
257			`h8 = h_in;`
258			`v8 = v_in;`
259			`case (opcode_in)`
260	9	ale500	`ADD, `ADC, `SUB, `SBC:
261	6	ale500	`begin`
262	9	ale500	`q8 = arith_q;`
263			`c8 = arith_c;`
264			`v8 = arith_v;`
265			`h8 = arith_h;`
266	6	ale500	`end`
267			`COM:
268			`begin`
269			`q8 = com8_r;`
270			`c8 = com8_r;`
271			`v8 = vcom8_r;`
272			`end`
273			`NEG:
274			`begin`
275			`q8 = neg8_r;`
276			`c8 = cneg8_r;`
277			`v8 = vneg8_r;`
278			`end`
279	9	ale500	`LSR, `LSL, `ROL, `ROR,`ASR:
280	6	ale500	`begin`
281	9	ale500	`q8 = shift_q;`
282			`c8 = shift_c;`
283			`v8 = shift_v;`
284	6	ale500	`end`
285	9	ale500	`AND, `OR, `EOR, `LD:
286	6	ale500	`begin`
287	9	ale500	`q8 = logic_q;`
288			`v8 = 1'b0;`
289	6	ale500	`end`
290			`DAA:
291			`begin // V is undefined, so we don't touch it`
292			`q8 = { daa8h_r, daa8l_r };`
293			`c8 = cdaa8_r;`
294			`end`
295			`ST:
296			`begin`
297			`q8 = a_in[7:0];`
298			`end`
299			`endcase`
300			`end`
301
302			`reg [7:0] regq8;`
303			`/* register before second mux */`
304			`always @(posedge clk_in)`
305			`begin`
306			`regq8 <= q8;`
307			`end`
308
309			`always @(*)`
310			`begin`
311			`q_out[7:0] = q8; //regq8;`
312			`case (opcode_in)`
313			`ORCC:
314			`CCRo = CCR \| b_in[7:0];`
315			`ANDCC:
316			`CCRo = CCR & b_in[7:0];`
317			`default:`
318			`CCRo = { CCR[7:6], CCR[5], h8, q8[7], (q8 == 8'h0), v8, c8 };`
319			`endcase`
320			`end`
321
322			`initial`
323			`begin`
324			`end`
325			`endmodule`
326
327			`/* ALU for 16 bit operations */`
328			`module alu16(`
329			`input wire clk_in,`
330			`input wire [15:0] a_in,`
331			`input wire [15:0] b_in,`
332			`input wire [7:0] CCR, /* condition code register */`
333			`input wire [4:0] opcode_in, /* ALU opcode */`
334			`output reg [15:0] q_out, /* ALU result */`
335			`output reg [3:0] CCRo`
336			`);`
337
338			`wire c_in, n_in, v_in, z_in;`
339	2	ale500	`assign c_in = CCR[0]; /* carry flag */`
340			`assign n_in = CCR[3]; /* neg flag */`
341			`assign v_in = CCR[1]; /* overflow flag */`
342			`assign z_in = CCR[2]; /* zero flag */`
343
344	9	ale500	`ifdef HD6309
345			`wire [15:0] com16_r, neg16_r;`
346			`wire [15:0] asr16_r, shr16_r, shl16_r, ror16_r, rol16_r, and16_r, or16_r, eor16_r;`
347	2	ale500
348	9	ale500	`wire [15:0] com16_w, neg16_w;`
349	6	ale500	`wire [15:0] asr16_w, shr16_w, shl16_w, ror16_w, rol16_w, and16_w, or16_w, eor16_w;`
350	2	ale500
351	9	ale500	`wire ccom16_r, cneg16_r;`
352			`wire casr16_r, cshr16_r, cshl16_r, cror16_r, crol16_r, cand16_r;`
353	2	ale500
354			`wire vadd16_r, vadc16_r, vsub16_r, vsbc16_r, vcom16_r, vneg16_r;`
355			`wire vasr16_r, vshr16_r, vshl16_r, vror16_r, vrol16_r, vand16_r;`
356
357			`assign com16_w = ~a_in[15:0];`
358			`assign neg16_w = 16'h0 - a_in[15:0];`
359			`assign asr16_w = { a_in[15], a_in[15:1] };`
360			`assign shr16_w = { 1'b0, a_in[15:1] };`
361			`assign shl16_w = { a_in[14:0], 1'b0 };`
362			`assign ror16_w = { c_in, a_in[15:1] };`
363			`assign rol16_w = { a_in[14:0], c_in };`
364			`assign and16_w = a_in[15:0] & b_in[15:0];`
365			`assign or16_w = a_in[15:0] \| b_in[15:0];`
366			`assign eor16_w = a_in[15:0] ^ b_in[15:0];`
367
368	9	ale500	`// COM`
369	2	ale500	`assign com16_r = com16_w;`
370			`assign ccom16_r = com16_w != 16'h0 ? 1'b1:1'b0;`
371			`assign vcom16_r = 1'b0;`
372			`// NEG`
373			`assign neg16_r = neg16_w;`
374			`assign vneg16_r = neg16_w[15] & (~neg16_w[14]) & (~neg16_w[13]) & (~neg16_w[12]) & (~neg16_w[11]) & (~neg16_w[10]) & (~neg16_w[9]) & (~neg16_w[8]) & (~neg16_w[7]) & (~neg16_w[6]) & (~neg16_w[5]) & (~neg16_w[4]) & (~neg16_w[3]) & (~neg16_w[2]) & (~neg16_w[1]) & (~neg16_w[0]);`
375			`assign cneg16_r = neg16_w[15] \| neg16_w[14] \| neg16_w[13] \| neg16_w[12] \| neg16_w[11] \| neg16_w[10] \| neg16_w[9] & neg16_w[8] \| neg16_w[7] \| neg16_w[6] \| neg16_w[5] \| neg16_w[4] \| neg16_w[3] \| neg16_w[2] \| neg16_w[1] \| neg16_w[0];`
376			`// ASR`
377			`assign asr16_r = asr16_w;`
378			`assign casr16_r = a_in[0];`
379			`assign vasr16_r = a_in[0] ^ asr16_w[15];`
380			`// SHR`
381			`assign shr16_r = shr16_w;`
382			`assign cshr16_r = a_in[0];`
383			`assign vshr16_r = a_in[0] ^ shr16_w[15];`
384			`// SHL`
385			`assign shl16_r = shl16_w;`
386			`assign cshl16_r = a_in[15];`
387			`assign vshl16_r = a_in[15] ^ shl16_w[15];`
388			`// ROR`
389			`assign ror16_r = ror16_w;`
390			`assign cror16_r = a_in[0];`
391			`assign vror16_r = a_in[0] ^ ror16_w[15];`
392			`// ROL`
393			`assign rol16_r = rol16_w;`
394			`assign crol16_r = a_in[15];`
395			`assign vrol16_r = a_in[15] ^ rol16_w[15];`
396			`// AND`
397			`assign and16_r = and16_w;`
398			`assign cand16_r = c_in;`
399			`assign vand16_r = 1'b0;`
400			`// OR`
401			`assign or16_r = or16_w;`
402			`// EOR`
403			`assign eor16_r = eor16_w;`
404	9	ale500	`endif
405	6	ale500
406			`wire [15:0] q16_mul;`
407
408	9	ale500	`mul8x8 mulu(clk_in, a_in[7:0], b_in[7:0], q16_mul);`
409	2	ale500
410	6	ale500	`reg c16, n16, v16, z16;`
411	2	ale500	`reg [15:0] q16;`
412
413	9	ale500	`wire [15:0] arith_q;`
414			`wire arith_c, arith_v, arith_h;`
415
416			`arith16 a16(a_in, b_in, c_in, opcode_in[1:0], arith_q, arith_c, arith_v);`
417
418	2	ale500	`always @(*)`
419			`begin`
420			`q16 = 16'h0;`
421			`c16 = c_in;`
422			`v16 = v_in;`
423			`case (opcode_in)`
424	9	ale500	`ADD, `ADC, `SUB, `SBC:
425	2	ale500	`begin`
426	9	ale500	`q16 = arith_q;`
427			`c16 = arith_c;`
428			`v16 = arith_v;`
429	2	ale500	`end`
430	6	ale500	`ifdef HD6309
431	2	ale500	`COM:
432			`begin`
433			`q16 = com16_r;`
434			`c16 = ccom16_r;`
435			`v16 = vcom16_r;`
436			`end`
437			`NEG:
438			`begin`
439			`q16 = neg16_r;`
440			`c16 = cneg16_r;`
441			`v16 = vneg16_r;`
442			`end`
443			`ASR:
444			`begin`
445			`q16 = asr16_r;`
446			`c16 = casr16_r;`
447			`v16 = vasr16_r;`
448			`end`
449			`LSR:
450			`begin`
451			`q16 = shr16_r;`
452			`c16 = cshr16_r;`
453			`v16 = vshr16_r;`
454			`end`
455			`LSL:
456			`begin`
457			`q16 = shl16_r;`
458			`c16 = cshl16_r;`
459			`v16 = vshl16_r;`
460			`end`
461			`ROR:
462			`begin`
463			`q16 = ror16_r;`
464			`c16 = cror16_r;`
465			`v16 = vror16_r;`
466			`end`
467			`ROL:
468			`begin`
469			`q16 = rol16_r;`
470			`c16 = crol16_r;`
471			`v16 = vrol16_r;`
472			`end`
473			`AND:
474			`begin`
475			`q16 = and16_r;`
476			`c16 = cand16_r;`
477			`v16 = vand16_r;`
478			`end`
479			`OR:
480			`begin`
481			`q16 = or16_r;`
482			`c16 = cand16_r;`
483			`v16 = vand16_r;`
484			`end`
485			`EOR:
486			`begin`
487			`q16 = eor16_r;`
488			`c16 = cand16_r;`
489			`v16 = vand16_r;`
490			`end`
491	6	ale500	`endif
492	2	ale500	`MUL:
493			`begin`
494	9	ale500	`q16 = q16_mul;`
495			`c16 = q16_mul[7];`
496	2	ale500	`end`
497			`LD:
498			`begin`
499			`v16 = 0;`
500			`q16 = b_in[15:0];`

Browse

Tools

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [alu16.v] - Blame information for rev 10