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/*
 * Signals which registers have to be read/written for the current opcode
 *
 *
 *
 */
`include "defs.v"
module decode_regs(
        input wire cpu_clk,
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output wire [3:0] path_left_addr_o,
        output wire [3:0] path_right_addr_o,
        output wire [3:0] dest_reg_o,
        output reg [3:0] path_left_addr_lo,
        output reg [3:0] path_right_addr_lo,
        output reg [3:0] dest_reg_lo,
        output wire write_dest,
        output wire source_size,
        output wire result_size
        );
reg [3:0] path_left_addr, path_right_addr, dest_reg;
// for registers, memory writes are handled differently
assign write_dest = (dest_reg != `RN_INV);
assign source_size = (path_left_addr < `RN_ACCA);
// result size is used to determine the size of the argument
// to load, compare has no result, thus the source is used instead,
// why do we need the result size ?... because of tfr&exg 
assign result_size = (dest_reg == `RN_INV) ? (path_left_addr < `RN_ACCA):
                     (dest_reg < `RN_IMM16) ? 1:0;
 
assign path_right_addr_o = path_right_addr;
assign path_left_addr_o = path_left_addr;
assign dest_reg_o = dest_reg;
 
 
always @(opcode, postbyte0, page2_valid, page3_valid)
        begin
                path_left_addr = `RN_INV;
                path_right_addr = `RN_INV;
                dest_reg = `RN_INV;
                if (page2_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
                                        8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
                                        8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
                                        8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
                                        8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
                                        8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy
                                        8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
                                        8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
                                        8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
                                        8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
                                endcase
                        end
                if (page3_valid)
                        begin
                                casex(postbyte0)
                                        8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
                                endcase
                                casex (postbyte0) // right arm
                                        8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
                                        8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
                                        8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
                                endcase
                                casex(postbyte0) // dest
                                        8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu
                                        8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps
                                endcase
                        end
                // destination
                casex(opcode)
                        8'h1a, 8'h1c: begin path_left_addr = `RN_CC; path_right_addr = `RN_IMM8; dest_reg = `RN_CC; end // ANDCC, ORCC
                        8'h19: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end // DAA
                        8'h1d: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCA; end // SEX
                        8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg
                        8'h30: dest_reg = `RN_IX;
                        8'h31: dest_reg = `RN_IY;
                        8'h32: dest_reg = `RN_S;
                        8'h33: dest_reg = `RN_U;
                        8'h39: dest_reg = `RN_PC; // rts
                        8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
                        8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                        8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                        8'h0x, 8'h6x, 8'h7x:
                                case (opcode[3:0])
                                        4'he: begin end // no source or dest for jmp
                                        4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
                                        default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
                                endcase
                        8'h8x, 8'h9x, 8'hax, 8'hbx:
                                case (opcode[3:0]) // default A->A
                                        4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
                                        4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
                                        4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
                                        4'hc: path_left_addr = `RN_IX; // cmpx
                                        4'hd: begin end // nothing active, jsr
                                        4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
                                        4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
                                        default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
                                endcase
                        8'hcx, 8'hdx, 8'hex, 8'hfx:
                                case (opcode[3:0])
                                        4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
                                        4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // addd
                                        4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // stb
                                        4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // ldd
                                        4'hd: begin path_left_addr = `RN_ACCD; dest_reg = `RN_MEM16; end // STD
                                        4'he: begin dest_reg = `RN_U; end // LDU
                                        4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
                                        default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
                                endcase
                endcase
                casex (opcode) // right arm
                        // 8x and Cx
                        8'b1x00_000x, 8'b1x00_0010, // sub, cmp, scb
                        8'b1x00_010x, 8'b1x00_0110,     8'b1x00_10xx: path_right_addr = `RN_IMM8;
                        // 83, C3, 8C, CC, 8E, CE
            8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
                        // 9, A, B, D, E, F
                        8'b1x01_000x, 8'b1x01_0010, // x0, x1, x2: sub cmp, scb
                        8'b1x01_010x, 8'b1x01_0110,     8'b1x01_10xx,
                        8'b1x1x_000x, 8'b1x1x_0010,
                        8'b1x1x_010x, 8'b1x1x_0110,     8'b1x1x_10xx: path_right_addr = `RN_MEM8;
            // 9x, Ax, Bx, Dx, Ex, Fx
            8'h93, 8'ha3, 8'hb3, // subd
            8'hd3, 8'he3, 8'hf3, // addd
            8'h9c, 8'hac, 8'hbc, // cmpx
            8'hdc, 8'hec, 8'hfc, // ldd
            //8'hdd, 8'hed, 8'hfd, // std
            8'h9e, 8'hae, 8'hbe, // ldx
            8'hde, 8'hee, 8'hfe, // ldu
            //8'h9f, 8'haf, 8'hbf, // stx
            8'hdf, 8'hef, 8'hff: path_right_addr = `RN_MEM16;// stu
                endcase
        end
// latched versions are used to fetch regsiters
// not-latched version in the decoder
always @(posedge cpu_clk)
        begin
                path_right_addr_lo <= path_right_addr;
                path_left_addr_lo <= path_left_addr;
                dest_reg_lo <= dest_reg;
        end
 
endmodule
 
/* Decodes module and addressing mode for page 1 opcodes */
module decode_op(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)
        output reg [2:0] mode,
        output reg [2:0] optype,
        output reg op_SYNC,
        output reg op_EXG,
        output reg op_TFR,
        output reg op_RTS,
        output reg op_RTI,
        output reg op_CWAI,
        output reg op_MUL,
        output reg op_SWI,
        output reg op_PUSH,
        output reg op_PULL,
        output reg op_LEA,
        output reg op_JMP,
        output reg op_JSR,
        output reg use_s
        );
 
wire [3:0] oplo;
reg size;
assign oplo = opcode[3:0];
 
always @(opcode, postbyte0, page2_valid, page3_valid, oplo)
        begin
                //dsize = `DSZ_8; // data operand size
                //msize = `MSZ_8; // memory operand size
                use_s = 1;
                mode = `NONE;
                size = 0;
                op_SYNC = 0;
                op_EXG = 0;
                op_TFR = 0;
                op_RTS = 0;
                op_RTI = 0;
                op_CWAI = 0;
                op_MUL = 0;
                op_SWI = 0;
                op_PUSH = 0;
                op_PULL = 0;
                op_LEA = 0;
                op_JMP = 0;
                op_JSR = 0;
                // Addressing mode
                casex(opcode)
                        8'h0x: begin mode = `DIRECT; end
                        //8'h0e: begin optype = `OP_JMP; end
                        8'h12, 8'h13, 8'h19: mode = `INHERENT;
                        8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
                        8'h16: mode = `REL16;
                        8'h17: begin mode = `REL16; op_JSR = 1; end
                        8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
                        8'h1e: op_EXG = 1;
                        8'h1f: op_TFR = 1;
                        8'h2x: mode = `REL8;
                        8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
                        8'h34: op_PUSH = 1;
                        8'h35: op_PULL = 1;
                        8'h36: begin op_PUSH = 1; use_s = 0; end
                        8'h37: begin op_PULL = 1; use_s = 0; end
                        8'h38, 8'h3e: mode = `NONE;
                        // don't change to inh because SEQ_MEM_READ_x would not use register S as address
                        8'h39: begin op_RTS = 1; mode = `INHERENT; end
                        8'h3b: begin op_RTI = 1; mode = `INHERENT; end
                        8'h3a, 8'h3c: mode = `INHERENT;
                        8'h3d: begin op_MUL = 1; mode = `INHERENT; end
                        8'h3f: begin op_SWI = 1; mode = `INHERENT; end
                        8'h4x: begin mode = `INHERENT; end
                        8'h5x: begin mode = `INHERENT; end
                        8'h6x: begin mode = `INDEXED; end
                        //8'h6e: begin optype = `OP_JMP; end
                        8'h7x: begin mode = `EXTENDED; end
                        //8'h7e: begin optype = `OP_JMP; end
                        8'h8x:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                4'hd: mode = `REL8; // bsr
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'hcx:
                                begin
                                        case (oplo)
                                                4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
                                                default: mode = `IMMEDIATE;
                                        endcase
                                end
                        8'h9x, 8'hdx: begin mode = `DIRECT; end
                        8'hax, 8'hex: begin mode = `INDEXED; end
                        8'hbx, 8'hfx: begin mode = `EXTENDED; end
                endcase
                // Opcode type
                casex(opcode)
                        8'h0e, 8'h6e, 8'h7e: op_JMP = 1;
                        8'b10xx1101: op_JSR = 1; // bsr & jsr
                endcase
                if (page2_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h2x: mode = `REL16;
                                        8'h3f: op_SWI = 1;
                                        8'h83: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end
                                        8'h8c: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin  mem16 = 1; size = 1; end
                                        8'hce: begin  mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                        end
                if (page3_valid == 1'b1)
                        begin
                                casex(postbyte0)
                                        8'h3f: op_SWI = 1;
                                        8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
                                        //8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD
                                        8'h8c: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end
                                        8'h8e: begin mode = `IMMEDIATE; size = 1; end
                                        //8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end
                                        //8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end
                                        8'hce: begin mode = `IMMEDIATE; size = 1; end
                                        //8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end
                                        //8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end
                                endcase
                                casex( postbyte0)
                                        8'h9x, 8'hdx: mode = `DIRECT;
                                        8'hax, 8'hex: mode = `INDEXED;
                                        8'hbx, 8'hfx: mode = `EXTENDED;
                                endcase
                        end
        end
 
endmodule
 
/* Decodes the Effective Address postbyte
   to recover size of offset to load and post-incr/pre-decr info
 */
module decode_ea(
        input wire [7:0] eapostbyte,
        output reg noofs,
        output reg ofs8, // needs an 8 bit offset
        output reg ofs16, // needs an 16 bit offset
        output reg write_post, // needs to write back a predecr or post incr
        output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address
        );
 
assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;
always @(*)
        begin
                noofs = 0;
                ofs8 = 0;
                ofs16 = 0;
                write_post = 0;
                casex (eapostbyte)
                        8'b0xxxxxxx, 8'b1xx00100: noofs = 1;
                        8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;
                        8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;
                        8'b1xx11111: ofs16 = 1; // extended indirect
                        8'b1xxx00xx: write_post = 1;
                endcase
        end
endmodule
 
module decode_alu(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode
        input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode
        output reg [4:0] alu_opcode,
        output reg [1:0] dec_alu_right_path_mod,
        output wire dest_flags
        );
// flags are written for alu opcodes as long as the opcode is not ANDCC or ORCC
assign dest_flags = (alu_opcode != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
always @(*)
        begin
                alu_opcode = `NOP;
                dec_alu_right_path_mod = `MOD_DEFAULT;
                casex (opcode)
                        8'b1xxx_0000: alu_opcode = `SUB;
                        8'b1xxx_0001: alu_opcode = `SUB; // CMP
                        8'b1xxx_0010: alu_opcode = `SBC;
                        8'b10xx_0011: alu_opcode = `SUB;
                        8'b11xx_0011: alu_opcode = `ADD;
                        8'b1xxx_0100: alu_opcode = `AND;
                        8'b1xxx_0101: alu_opcode = `AND; // BIT
                        8'b1xxx_0110: alu_opcode = `LD;
                        8'b1xxx_0111: alu_opcode = `ST;
                        8'b1xxx_1000: alu_opcode = `EOR;
                        8'b1xxx_1001: alu_opcode = `ADC;
                        8'b1xxx_1010: alu_opcode = `OR;
                        8'b1xxx_1011: alu_opcode = `ADD;
                        8'b10xx_1100: alu_opcode = `SUB; // CMP
                        8'b11xx_1100: alu_opcode = `LD;
                        8'b11xx_1101: alu_opcode = `ST;
                        8'b1xxx_1110: alu_opcode = `LD;
                        8'b1xxx_1111: alu_opcode = `ST;
 
                        8'h00, 8'b01xx_0000: alu_opcode = `NEG;
                        8'h03, 8'b01xx_0011: alu_opcode = `COM;
                        8'h04, 8'b01xx_0100: alu_opcode = `LSR;
                        8'h06, 8'b01xx_0110: alu_opcode = `ROR;
                        8'h07, 8'b01xx_0111: alu_opcode = `ASR;
                        8'h08, 8'b01xx_1000: alu_opcode = `LSL;
                        8'h09, 8'b01xx_1001: alu_opcode = `ROL;
                        8'h0a, 8'b01xx_1010: begin alu_opcode = `DEC; dec_alu_right_path_mod = `MOD_ONE; end // dec
                        8'h0c, 8'b01xx_1100: begin alu_opcode = `INC; dec_alu_right_path_mod = `MOD_ONE; end // inc
                        8'h0d, 8'b01xx_1101: alu_opcode = `AND;
                        8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
 
                        8'h19: alu_opcode = `DAA;
                        8'h1a: alu_opcode = `OR;
                        8'h1c: alu_opcode = `AND;
                        8'h1d: alu_opcode = `SEXT;
                        //8'h1e: alu_opcode = `EXG;
                        8'b0011_000x: alu_opcode = `LEA;
                        8'h3d: alu_opcode = `MUL;
                endcase
                if (page2_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1100: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
                if (page3_valid)
                        casex (postbyte0)
                                8'b10xx_0011,
                                8'b10xx_1100: alu_opcode = `SUB; //CMP
                                8'b1xxx_1110: alu_opcode = `LD;
                                8'b1xxx_1111: alu_opcode = `ST;
                        endcase
        end
 
endmodule
/* decodes the condition and checks the flags to see if it is met */
module test_condition(
        input wire [7:0] opcode,
        input wire [7:0] postbyte0,
        input wire page2_valid,
        input wire [7:0] CCR,
        output reg cond_taken
        );
 
wire [7:0] op = page2_valid ? postbyte0:opcode;
 
always @(*)
        begin
                cond_taken = 1'b0;
                if ((op == 8'h16) || (op == 8'h17) || (op == 8'h8D) ||
                        (op == 8'h0e) || (op == 8'h6e) || (op == 8'h7e)) // jmp
                        cond_taken = 1'b1; // LBRA/LBSR, BSR
                if (op[7:4] == 4'h2)
                        case (op[3:0])
                                4'h0: cond_taken = 1'b1; // BRA
                                4'h1: cond_taken = 0; // BRN
                                4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
                                4'h3: cond_taken = `DFLAGC | `DFLAGZ; // BLS
                                4'h4: cond_taken = !`DFLAGC; // BCC, BHS
                                4'h5: cond_taken = `DFLAGC; // BCS, BLO
                                4'h6: cond_taken = !`DFLAGZ; // BNE
                                4'h7: cond_taken = `DFLAGZ; // BEQ
                                4'h8: cond_taken = !`DFLAGV; // BVC
                                4'h9: cond_taken = `DFLAGV; // BVS
                                4'ha: cond_taken = !`DFLAGN; // BPL
                                4'hb: cond_taken = `DFLAGN; // BMI
                                4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
                                4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
                                4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
                                4'hf: cond_taken = (`DFLAGN != `DFLAGV) | (`DFLAGZ); // BLE
                endcase
        end
 
endmodule

Line No.	Rev	Author	Line
1	2	ale500
2			`/*`
3			`* Signals which registers have to be read/written for the current opcode`
4			`*`
5			`*`
6			`*`
7			`*/`
8			`include "defs.v"
9	9	ale500	`module decode_regs(`
10			`input wire cpu_clk,`
11	2	ale500	`input wire [7:0] opcode,`
12			`input wire [7:0] postbyte0,`
13			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
14			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
15	11	ale500	`output wire [3:0] path_left_addr_o,`
16			`output wire [3:0] path_right_addr_o,`
17			`output wire [3:0] dest_reg_o,`
18			`output reg [3:0] path_left_addr_lo,`
19			`output reg [3:0] path_right_addr_lo,`
20			`output reg [3:0] dest_reg_lo,`
21	4	ale500	`output wire write_dest,`
22			`output wire source_size,`
23	2	ale500	`output wire result_size`
24	9	ale500	`);`
25			`reg [3:0] path_left_addr, path_right_addr, dest_reg;`
26	2	ale500	`// for registers, memory writes are handled differently`
27	4	ale500	assign write_dest = (dest_reg != `RN_INV);
28			assign source_size = (path_left_addr < `RN_ACCA);
29	12	ale500	`// result size is used to determine the size of the argument`
30			`// to load, compare has no result, thus the source is used instead,`
31			`// why do we need the result size ?... because of tfr&exg`
32			assign result_size = (dest_reg == `RN_INV) ? (path_left_addr < `RN_ACCA):
33			(dest_reg < `RN_IMM16) ? 1:0;
34	11	ale500
35			`assign path_right_addr_o = path_right_addr;`
36			`assign path_left_addr_o = path_left_addr;`
37			`assign dest_reg_o = dest_reg;`
38
39
40	2	ale500	`always @(opcode, postbyte0, page2_valid, page3_valid)`
41			`begin`
42			path_left_addr = `RN_INV;
43			path_right_addr = `RN_INV;
44			dest_reg = `RN_INV;
45	4	ale500	`if (page2_valid)`
46	2	ale500	`begin`
47			`casex(postbyte0)`
48	4	ale500	8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_ACCD; // cmpd
49			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_IY; // cmpy
50			8'h8e, 8'h9e, 8'hae, 8'hbe: path_left_addr = `RN_IY; // ldy
51			8'h8f, 8'h9f, 8'haf, 8'hbf: path_left_addr = `RN_IY; // sty
52			8'hdf, 8'hef, 8'hff: path_left_addr = `RN_S; // STS
53	2	ale500	`endcase`
54			`casex (postbyte0) // right arm`
55	4	ale500	8'h83, 8'h8c, 8'h8e, 8'hce: path_right_addr = `RN_IMM16;
56	2	ale500	8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16;
57			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16;
58			8'h9e, 8'hae, 8'hbe: path_right_addr = `RN_MEM16;
59	10	ale500	8'h9f, 8'haf, 8'hbf: path_right_addr = `RN_MEM16; // STY
60	4	ale500	8'hde, 8'hee, 8'hfe: path_right_addr = `RN_MEM16; // lds
61	2	ale500	`endcase`
62			`casex(postbyte0) // dest`
63	10	ale500	`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpd`
64			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmpy`
65			8'h8e, 8'h9e, 8'hae, 8'hbe: dest_reg = `RN_IY; // LDY
66	4	ale500	8'hce, 8'hde, 8'hee, 8'hfe: dest_reg = `RN_S; // LDS
67	10	ale500	8'h9f, 8'haf, 8'hbf: dest_reg = `RN_MEM16; // STY
68			8'hdf, 8'hef, 8'hff: dest_reg = `RN_MEM16; // STS
69	2	ale500	`endcase`
70	4	ale500	`end`
71			`if (page3_valid)`
72			`begin`
73			`casex(postbyte0)`
74			8'h83, 8'h93, 8'ha3, 8'hb3: path_left_addr = `RN_U; // CMPU
75			8'h8c, 8'h9c, 8'hac, 8'hbc: path_left_addr = `RN_S; // CMPS
76			`endcase`
77			`casex (postbyte0) // right arm`
78	10	ale500	8'h83, 8'h8c: path_right_addr = `RN_IMM16; // CMPU, CMPS
79			8'h93, 8'ha3, 8'hb3: path_right_addr = `RN_MEM16; // CMPU
80			8'h9c, 8'hac, 8'hbc: path_right_addr = `RN_MEM16; // CMPS
81	4	ale500	`endcase`
82			`casex(postbyte0) // dest`
83			`8'h83, 8'h93, 8'ha3, 8'hb3: begin end // cmpu`
84			`8'h8c, 8'h9c, 8'hac, 8'hbc: begin end // cmps`
85			`endcase`
86	2	ale500	`end`
87			`// destination`
88	12	ale500	`casex(opcode)`
89			8'h1a, 8'h1c: begin path_left_addr = `RN_CC; path_right_addr = `RN_IMM8; dest_reg = `RN_CC; end // ANDCC, ORCC
90			8'h19: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end // DAA
91			8'h1d: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCA; end // SEX
92	5	ale500	`8'h1e, 8'h1f: begin dest_reg = postbyte0[3:0]; path_left_addr = postbyte0[7:4]; path_right_addr = postbyte0[3:0]; end // tfr, exg`
93	2	ale500	8'h30: dest_reg = `RN_IX;
94			8'h31: dest_reg = `RN_IY;
95			8'h32: dest_reg = `RN_S;
96			8'h33: dest_reg = `RN_U;
97			8'h39: dest_reg = `RN_PC; // rts
98			8'h3d: begin path_left_addr = `RN_ACCA; path_right_addr = `RN_ACCB; dest_reg = `RN_ACCD; end // mul
99			8'h4x: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
100			8'h5x: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
101	11	ale500	`8'h0x, 8'h6x, 8'h7x:`
102	12	ale500	`case (opcode[3:0])`
103			`4'he: begin end // no source or dest for jmp`
104	2	ale500	4'hf: begin dest_reg = `RN_MEM8; end // CLR, only dest
105			default: begin path_left_addr = `RN_MEM8; dest_reg = `RN_MEM8; end
106			`endcase`
107	10	ale500	`8'h8x, 8'h9x, 8'hax, 8'hbx:`
108			`case (opcode[3:0]) // default A->A`
109	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCA; // CMP, BIT
110	2	ale500	4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end
111	10	ale500	4'h7: begin path_left_addr = `RN_ACCA; dest_reg = `RN_MEM8; end // sta
112	4	ale500	4'hc: path_left_addr = `RN_IX; // cmpx
113	2	ale500	`4'hd: begin end // nothing active, jsr`
114	10	ale500	4'he: begin path_left_addr = `RN_IX; dest_reg = `RN_IX; end // ldx
115			4'hf: begin path_left_addr = `RN_IX; dest_reg = `RN_MEM16; end // stx
116	2	ale500	default: begin path_left_addr = `RN_ACCA; dest_reg = `RN_ACCA; end
117			`endcase`
118	10	ale500	`8'hcx, 8'hdx, 8'hex, 8'hfx:`
119	2	ale500	`case (opcode[3:0])`
120	9	ale500	4'h1, 4'h5: path_left_addr = `RN_ACCB; // CMP, BIT
121	15	ale500	4'h3: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // addd
122			4'h7: begin path_left_addr = `RN_ACCB; dest_reg = `RN_MEM8; end // stb
123			4'hc: begin path_left_addr = `RN_ACCD; dest_reg = `RN_ACCD; end // ldd
124			4'hd: begin path_left_addr = `RN_ACCD; dest_reg = `RN_MEM16; end // STD
125			4'he: begin dest_reg = `RN_U; end // LDU
126	10	ale500	4'hf: begin path_left_addr = `RN_U; dest_reg = `RN_MEM16; end // STU
127	2	ale500	default: begin path_left_addr = `RN_ACCB; dest_reg = `RN_ACCB; end
128			`endcase`
129			`endcase`
130			`casex (opcode) // right arm`
131			`// 8x and Cx`
132	15	ale500	`8'b1x00_000x, 8'b1x00_0010, // sub, cmp, scb`
133	10	ale500	8'b1x00_010x, 8'b1x00_0110, 8'b1x00_10xx: path_right_addr = `RN_IMM8;
134	15	ale500	`// 83, C3, 8C, CC, 8E, CE`
135			8'b1x00_0011, 8'b1x00_11x0: path_right_addr = `RN_IMM16; // cmpd, cmpx, ldx
136	2	ale500	`// 9, A, B, D, E, F`
137	15	ale500	`8'b1x01_000x, 8'b1x01_0010, // x0, x1, x2: sub cmp, scb`
138			`8'b1x01_010x, 8'b1x01_0110, 8'b1x01_10xx,`
139			`8'b1x1x_000x, 8'b1x1x_0010,`
140	10	ale500	8'b1x1x_010x, 8'b1x1x_0110, 8'b1x1x_10xx: path_right_addr = `RN_MEM8;
141	15	ale500	`// 9x, Ax, Bx, Dx, Ex, Fx`
142			`8'h93, 8'ha3, 8'hb3, // subd`
143			`8'hd3, 8'he3, 8'hf3, // addd`
144			`8'h9c, 8'hac, 8'hbc, // cmpx`
145			`8'hdc, 8'hec, 8'hfc, // ldd`
146			`//8'hdd, 8'hed, 8'hfd, // std`
147			`8'h9e, 8'hae, 8'hbe, // ldx`
148			`8'hde, 8'hee, 8'hfe, // ldu`
149			`//8'h9f, 8'haf, 8'hbf, // stx`
150			8'hdf, 8'hef, 8'hff: path_right_addr = `RN_MEM16;// stu
151	2	ale500	`endcase`
152			`end`
153	11	ale500	`// latched versions are used to fetch regsiters`
154			`// not-latched version in the decoder`
155	9	ale500	`always @(posedge cpu_clk)`
156			`begin`
157	11	ale500	`path_right_addr_lo <= path_right_addr;`
158			`path_left_addr_lo <= path_left_addr;`
159			`dest_reg_lo <= dest_reg;`
160	9	ale500	`end`
161	11	ale500
162	2	ale500	`endmodule`
163
164			`/* Decodes module and addressing mode for page 1 opcodes */`
165			`module decode_op(`
166			`input wire [7:0] opcode,`
167			`input wire [7:0] postbyte0,`
168			`input wire page2_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
169			`input wire page3_valid, // is 1 when the postbyte0 is a valid opcode (after it was loaded)`
170			`output reg [2:0] mode,`
171			`output reg [2:0] optype,`
172	14	ale500	`output reg op_SYNC,`
173			`output reg op_EXG,`
174			`output reg op_TFR,`
175			`output reg op_RTS,`
176			`output reg op_RTI,`
177			`output reg op_CWAI,`
178			`output reg op_MUL,`
179			`output reg op_SWI,`
180			`output reg op_PUSH,`
181			`output reg op_PULL,`
182			`output reg op_LEA,`
183			`output reg op_JMP,`
184			`output reg op_JSR,`
185	2	ale500	`output reg use_s`
186			`);`
187
188			`wire [3:0] oplo;`
189			`reg size;`
190			`assign oplo = opcode[3:0];`
191
192			`always @(opcode, postbyte0, page2_valid, page3_valid, oplo)`
193			`begin`
194			//dsize = `DSZ_8; // data operand size
195			//msize = `MSZ_8; // memory operand size
196			`use_s = 1;`
197			mode = `NONE;
198			`size = 0;`
199	14	ale500	`op_SYNC = 0;`
200			`op_EXG = 0;`
201			`op_TFR = 0;`
202			`op_RTS = 0;`
203			`op_RTI = 0;`
204			`op_CWAI = 0;`
205			`op_MUL = 0;`
206			`op_SWI = 0;`
207			`op_PUSH = 0;`
208			`op_PULL = 0;`
209			`op_LEA = 0;`
210			`op_JMP = 0;`
211			`op_JSR = 0;`
212	2	ale500	`// Addressing mode`
213			`casex(opcode)`
214			8'h0x: begin mode = `DIRECT; end
215	12	ale500	//8'h0e: begin optype = `OP_JMP; end
216	2	ale500	8'h12, 8'h13, 8'h19: mode = `INHERENT;
217			8'h14, 8'h15, 8'h18, 8'h1b: mode = `NONE; // undefined opcodes
218			8'h16: mode = `REL16;
219	14	ale500	8'h17: begin mode = `REL16; op_JSR = 1; end
220			8'h1a, 8'h1c, 8'h1d: mode = `IMMEDIATE; // handled in ALU ORCC, ANDCC, SEX
221			`8'h1e: op_EXG = 1;`
222			`8'h1f: op_TFR = 1;`
223	2	ale500	8'h2x: mode = `REL8;
224	14	ale500	8'h30, 8'h31, 8'h32, 8'h33: begin mode = `INDEXED; op_LEA = 1; end
225			`8'h34: op_PUSH = 1;`
226			`8'h35: op_PULL = 1;`
227			`8'h36: begin op_PUSH = 1; use_s = 0; end`
228			`8'h37: begin op_PULL = 1; use_s = 0; end`
229	2	ale500	8'h38, 8'h3e: mode = `NONE;
230			`// don't change to inh because SEQ_MEM_READ_x would not use register S as address`
231	14	ale500	8'h39: begin op_RTS = 1; mode = `INHERENT; end
232			8'h3b: begin op_RTI = 1; mode = `INHERENT; end
233			8'h3a, 8'h3c: mode = `INHERENT;
234			8'h3d: begin op_MUL = 1; mode = `INHERENT; end
235			8'h3f: begin op_SWI = 1; mode = `INHERENT; end
236	2	ale500	8'h4x: begin mode = `INHERENT; end
237			8'h5x: begin mode = `INHERENT; end
238			8'h6x: begin mode = `INDEXED; end
239	12	ale500	//8'h6e: begin optype = `OP_JMP; end
240	2	ale500	8'h7x: begin mode = `EXTENDED; end
241	12	ale500	//8'h7e: begin optype = `OP_JMP; end
242	2	ale500	`8'h8x:`
243			`begin`
244			`case (oplo)`
245			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
246			4'hd: mode = `REL8; // bsr
247			default: mode = `IMMEDIATE;
248			`endcase`
249			`end`
250			`8'hcx:`
251			`begin`
252			`case (oplo)`
253			4'h3, 4'hc, 4'he: begin mode = `IMMEDIATE; size = 1; end
254			default: mode = `IMMEDIATE;
255			`endcase`
256			`end`
257			8'h9x, 8'hdx: begin mode = `DIRECT; end
258			8'hax, 8'hex: begin mode = `INDEXED; end
259			8'hbx, 8'hfx: begin mode = `EXTENDED; end
260			`endcase`
261			`// Opcode type`
262			`casex(opcode)`
263	14	ale500	`8'h0e, 8'h6e, 8'h7e: op_JMP = 1;`
264			`8'b10xx1101: op_JSR = 1; // bsr & jsr`
265	2	ale500	`endcase`
266			`if (page2_valid == 1'b1)`
267			`begin`
268			`casex(postbyte0)`
269	12	ale500	8'h2x: mode = `REL16;
270	14	ale500	`8'h3f: op_SWI = 1;`
271	2	ale500	8'h83: begin mode = `IMMEDIATE; size = 1; end
272			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end`
273			8'h8c: begin mode = `IMMEDIATE; size = 1; end
274			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
275			8'h8e: begin mode = `IMMEDIATE; size = 1; end
276			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
277			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
278			8'hce: begin mode = `IMMEDIATE; size = 1; end
279			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
280			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
281			`endcase`
282			`casex( postbyte0)`
283			8'h9x, 8'hdx: mode = `DIRECT;
284			8'hax, 8'hex: mode = `INDEXED;
285			8'hbx, 8'hfx: mode = `EXTENDED;
286			`endcase`
287			`end`
288			`if (page3_valid == 1'b1)`
289			`begin`
290			`casex(postbyte0)`
291	14	ale500	`8'h3f: op_SWI = 1;`
292	2	ale500	8'h83: begin mode = `IMMEDIATE; size = 1; end // CMPD
293			`//8'h93, 8'ha3, 8'hb3: begin mem16 = 1; size = 1; end // CMPD`
294			8'h8c: begin mode = `IMMEDIATE; size = 1; end
295			`//8'h9c, 8'hac, 8'hbc: begin mem16 = 1; size = 1; end`
296			8'h8e: begin mode = `IMMEDIATE; size = 1; end
297			`//8'h9e, 8'hae, 8'hbe: begin mem16 = 1; size = 1; end`
298			`//8'h9f, 8'haf, 8'hbf: begin mem16 = 1; size = 1; end`
299			8'hce: begin mode = `IMMEDIATE; size = 1; end
300			`//8'hde, 8'hee, 8'hfe: begin mem16 = 1; size = 1; end`
301			`//8'hdf, 8'hef, 8'hff: begin mem16 = 1; size = 1; end`
302			`endcase`
303			`casex( postbyte0)`
304			8'h9x, 8'hdx: mode = `DIRECT;
305			8'hax, 8'hex: mode = `INDEXED;
306			8'hbx, 8'hfx: mode = `EXTENDED;
307			`endcase`
308			`end`
309			`end`
310
311			`endmodule`
312
313			`/* Decodes the Effective Address postbyte`
314			`to recover size of offset to load and post-incr/pre-decr info`
315			`*/`
316			`module decode_ea(`
317			`input wire [7:0] eapostbyte,`
318			`output reg noofs,`
319			`output reg ofs8, // needs an 8 bit offset`
320			`output reg ofs16, // needs an 16 bit offset`
321			`output reg write_post, // needs to write back a predecr or post incr`
322			`output wire isind // signals when the mode is indirect, the memory at the address is read to load the real address`
323			`);`
324
325			`assign isind = (eapostbyte[7] & eapostbyte[4]) ? 1'b1:1'b0;`
326			`always @(*)`
327			`begin`
328			`noofs = 0;`
329			`ofs8 = 0;`
330			`ofs16 = 0;`
331			`write_post = 0;`
332			`casex (eapostbyte)`
333			`8'b0xxxxxxx, 8'b1xx00100: noofs = 1;`
334			`8'b1xxx1000, 8'b1xxx1100: ofs8 = 1;`
335			`8'b1xxx1001, 8'b1xxx1101: ofs16 = 1;`
336			`8'b1xx11111: ofs16 = 1; // extended indirect`
337			`8'b1xxx00xx: write_post = 1;`
338			`endcase`
339			`end`
340			`endmodule`
341
342			`module decode_alu(`
343			`input wire [7:0] opcode,`
344			`input wire [7:0] postbyte0,`
345			`input wire page2_valid, // is 1 when the postbyte0 was loaded and is page2 opcode`
346			`input wire page3_valid, // is 1 when the postbyte0 was loaded and is page3 opcode`
347			`output reg [4:0] alu_opcode,`
348			`output reg [1:0] dec_alu_right_path_mod,`
349			`output wire dest_flags`
350			`);`
351	12	ale500	`// flags are written for alu opcodes as long as the opcode is not ANDCC or ORCC`
352			assign dest_flags = (alu_opcode != `NOP) && (opcode != 8'h1a) && (opcode != 8'h1c);
353	2	ale500	`always @(*)`
354			`begin`
355			alu_opcode = `NOP;
356			dec_alu_right_path_mod = `MOD_DEFAULT;
357			`casex (opcode)`
358			8'b1xxx_0000: alu_opcode = `SUB;
359	9	ale500	8'b1xxx_0001: alu_opcode = `SUB; // CMP
360	2	ale500	8'b1xxx_0010: alu_opcode = `SBC;
361			8'b10xx_0011: alu_opcode = `SUB;
362			8'b11xx_0011: alu_opcode = `ADD;
363			8'b1xxx_0100: alu_opcode = `AND;
364	9	ale500	8'b1xxx_0101: alu_opcode = `AND; // BIT
365	2	ale500	8'b1xxx_0110: alu_opcode = `LD;
366			8'b1xxx_0111: alu_opcode = `ST;
367			8'b1xxx_1000: alu_opcode = `EOR;
368			8'b1xxx_1001: alu_opcode = `ADC;
369			8'b1xxx_1010: alu_opcode = `OR;
370			8'b1xxx_1011: alu_opcode = `ADD;
371	9	ale500	8'b10xx_1100: alu_opcode = `SUB; // CMP
372	2	ale500	8'b11xx_1100: alu_opcode = `LD;
373	15	ale500	8'b11xx_1101: alu_opcode = `ST;
374	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
375			8'b1xxx_1111: alu_opcode = `ST;
376
377			8'h00, 8'b01xx_0000: alu_opcode = `NEG;
378			8'h03, 8'b01xx_0011: alu_opcode = `COM;
379			8'h04, 8'b01xx_0100: alu_opcode = `LSR;
380			8'h06, 8'b01xx_0110: alu_opcode = `ROR;
381			8'h07, 8'b01xx_0111: alu_opcode = `ASR;
382			8'h08, 8'b01xx_1000: alu_opcode = `LSL;
383			8'h09, 8'b01xx_1001: alu_opcode = `ROL;
384	12	ale500	8'h0a, 8'b01xx_1010: begin alu_opcode = `DEC; dec_alu_right_path_mod = `MOD_ONE; end // dec
385			8'h0c, 8'b01xx_1100: begin alu_opcode = `INC; dec_alu_right_path_mod = `MOD_ONE; end // inc
386	2	ale500	8'h0d, 8'b01xx_1101: alu_opcode = `AND;
387			8'h0f, 8'b01xx_1111: begin alu_opcode = `LD; dec_alu_right_path_mod = `MOD_ZERO; end // CLR
388
389			8'h19: alu_opcode = `DAA;
390	12	ale500	8'h1a: alu_opcode = `OR;
391			8'h1c: alu_opcode = `AND;
392	2	ale500	8'h1d: alu_opcode = `SEXT;
393	9	ale500	//8'h1e: alu_opcode = `EXG;
394	4	ale500	8'b0011_000x: alu_opcode = `LEA;
395	2	ale500	8'h3d: alu_opcode = `MUL;
396			`endcase`
397			`if (page2_valid)`
398			`casex (postbyte0)`
399			`8'b10xx_0011,`
400	12	ale500	8'b10xx_1100: alu_opcode = `SUB; //CMP
401	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
402			8'b1xxx_1111: alu_opcode = `ST;
403			`endcase`
404			`if (page3_valid)`
405			`casex (postbyte0)`
406			`8'b10xx_0011,`
407	12	ale500	8'b10xx_1100: alu_opcode = `SUB; //CMP
408	2	ale500	8'b1xxx_1110: alu_opcode = `LD;
409			8'b1xxx_1111: alu_opcode = `ST;
410			`endcase`
411			`end`
412
413			`endmodule`
414			`/* decodes the condition and checks the flags to see if it is met */`
415			`module test_condition(`
416			`input wire [7:0] opcode,`
417			`input wire [7:0] postbyte0,`
418			`input wire page2_valid,`
419			`input wire [7:0] CCR,`
420			`output reg cond_taken`
421			`);`
422
423			`wire [7:0] op = page2_valid ? postbyte0:opcode;`
424
425			`always @(*)`
426			`begin`
427			`cond_taken = 1'b0;`
428	12	ale500	`if ((op == 8'h16) \|\| (op == 8'h17) \|\| (op == 8'h8D) \|\|`
429			`(op == 8'h0e) \|\| (op == 8'h6e) \|\| (op == 8'h7e)) // jmp`
430	2	ale500	`cond_taken = 1'b1; // LBRA/LBSR, BSR`
431			`if (op[7:4] == 4'h2)`
432			`case (op[3:0])`
433			`4'h0: cond_taken = 1'b1; // BRA`
434			`4'h1: cond_taken = 0; // BRN`
435			4'h2: cond_taken = !(`DFLAGC & `DFLAGZ); // BHI
436			4'h3: cond_taken = `DFLAGC \| `DFLAGZ; // BLS
437			4'h4: cond_taken = !`DFLAGC; // BCC, BHS
438			4'h5: cond_taken = `DFLAGC; // BCS, BLO
439			4'h6: cond_taken = !`DFLAGZ; // BNE
440			4'h7: cond_taken = `DFLAGZ; // BEQ
441			4'h8: cond_taken = !`DFLAGV; // BVC
442			4'h9: cond_taken = `DFLAGV; // BVS
443			4'ha: cond_taken = !`DFLAGN; // BPL
444			4'hb: cond_taken = `DFLAGN; // BMI
445			4'hc: cond_taken = `DFLAGN == `DFLAGV; // BGE
446			4'hd: cond_taken = `DFLAGN != `DFLAGV; // BLT
447			4'he: cond_taken = (`DFLAGN == `DFLAGV) & (!`DFLAGZ); // BGT
448			4'hf: cond_taken = (`DFLAGN != `DFLAGV) \| (`DFLAGZ); // BLE
449			`endcase`
450			`end`
451
452			`endmodule`

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