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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Blame information for rev 16

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`default_nettype none
 
`define RN_ACCD         4'h0
`define RN_IX           4'h1
`define RN_IY           4'h2
`define RN_U            4'h3
`define RN_S            4'h4
`define RN_PC           4'h5
//`define RN_MEM16      4'h6
//`define RN_IMM16      4'h7
`define RN_ACCA         4'h8
`define RN_ACCB         4'h9
`define RN_CC           4'ha
`define RN_DP           4'hb
//`define RN_MEM8               4'hc
//`define       RN_IMM8         4'hd
`define RN_INV          4'hf
 
 
// opcodes that need an ALU result
`define NOP    5'b00000
`define SEXT   5'b00001
`define ST     5'b00010
`define BIT    5'b00011
 
`define LD     5'b00100 // in logic8
`define AND    5'b00101 // in logic8
`define OR     5'b00110 // in logic8
`define EOR    5'b00111 // in logic8
`define ADD    5'b01000 // in arith8
`define SUB    5'b01001 // in arith8
`define ADC    5'b01010 // in arith8
`define SBC    5'b01011 // in arith8
 
`define LSR    5'b10000
`define LSL    5'b10001
`define ROR    5'b10010
`define ROL    5'b10011
`define ASR    5'b10100
`define NEG    5'b10101
`define COM    5'b10110
`define INC    5'b11000 // encoding of least 2 bits must be like ADD/SUB
`define DEC    5'b11001
`define DAA    5'b11010
`define MUL    5'b11011
`define LEA    5'b11100
`define CLR    5'b11101
`define TST    5'b11110
 
/* Sequencer states */
 
`define SEQ_COLDRESET           'h00
`define SEQ_NMI                         'h01
`define SEQ_SWI                         'h02
`define SEQ_IRQ                         'h03
`define SEQ_FIRQ                        'h04
`define SEQ_SWI2                        'h05
`define SEQ_SWI3                        'h06
`define SEQ_UNDEF                       'h07
`define SEQ_LOADPC              'h08
`define SEQ_FETCH                       'h09
`define SEQ_FETCH_1             'h0a
`define SEQ_FETCH_2             'h0b
`define SEQ_FETCH_3             'h0c
`define SEQ_FETCH_4             'h0d
`define SEQ_FETCH_5             'h0e
 
`define SEQ_DECODE                      'h0f
`define SEQ_DECODE_P23          'h10 // x
 
`define SEQ_GRAL_ALU            'h11
`define SEQ_GRAL_WBACK          'h12
`define SEQ_CWAI_STACK          'h13 // stacks registers
`define SEQ_CWAI_WAIT           'h14 // waits for an interrupt
`define SEQ_TFREXG                      'h15
 
`define SEQ_IND_READ_EA         'h16 // offset 8 or 16 bits
`define SEQ_IND_READ_EA_1       'h17
`define SEQ_IND_READ_EA_2       'h18 // real operand from memory indirect
`define SEQ_IND_DECODE          'h19
`define SEQ_IND_DECODE_OFS  'h1a // used to load 8 or 16 bits offset
`define SEQ_JMP_LOAD_PC         'h1b
 
 
`define SEQ_JSR_PUSH            'h1c
`define SEQ_JSR_PUSH_L          'h1d // x
`define SEQ_RTS_POP_L           'h1e // x
`define SEQ_RTS_POP_H           'h1f // x
 
`define SEQ_PREPUSH                     'h20
`define SEQ_PREPULL                     'h21
`define SEQ_PUSH_WRITE_L        'h22
`define SEQ_PUSH_WRITE_L_1      'h23
`define SEQ_PUSH_WRITE_H        'h24
`define SEQ_PUSH_WRITE_H_1      'h25
`define SEQ_SYNC                        'h26
 
`define SEQ_PC_READ_H           'h30
`define SEQ_PC_READ_H_1         'h31
`define SEQ_PC_READ_H_2         'h32
`define SEQ_PC_READ_L           'h33
`define SEQ_PC_READ_L_1         'h34
`define SEQ_PC_READ_L_2         'h35
 
`define SEQ_MEM_READ_H          'h36
`define SEQ_MEM_READ_H_1        'h37
`define SEQ_MEM_READ_H_2        'h38
`define SEQ_MEM_READ_L          'h39
`define SEQ_MEM_READ_L_1        'h3a
`define SEQ_MEM_READ_L_2        'h3b
`define SEQ_MEM_WRITE_H         'h3c
`define SEQ_MEM_WRITE_H_1       'h3d
`define SEQ_MEM_WRITE_L         'h3e
`define SEQ_MEM_WRITE_L_1       'h3f
 
// flags used in MC6809_cpu.v
`define FLAGI regs_o_CCR[5]
`define FLAGF regs_o_CCR[6]
`define FLAGE regs_o_CCR[7]
 
`define DFLAGC CCR[0]
`define DFLAGV CCR[1]
`define DFLAGZ CCR[2]
`define DFLAGN CCR[3]
// some wires exist only for simulation
`define SIMULATION 1
// Adressing modes
`define NONE            3'h0
`define IMMEDIATE   3'h1
`define INHERENT        3'h2
`define DIRECT          3'h3
`define INDEXED         3'h4
`define EXTENDED        3'h5
`define REL8            3'h6
`define REL16           3'h7
 
// Address size
 
// memory transfer size, read or written, used for addresses 
`define MSZ_0   2'h0
`define MSZ_8   2'h1
`define MSZ_16  2'h2
// Data transfer size, to save to register, used for data from memory and to save results to memory/registers
`define DSZ_0   2'h0
`define DSZ_8   2'h1
`define DSZ_16  2'h2
/* Memory access type for input/output operands */
`define MT_NONE         3'h0
`define MT_BYTE         3'h1
`define MT_WORD         3'h2
`define MT_QUAD         3'h3
 
/* alu decoder right path modifier */
`define MOD_DEFAULT 2'h0
`define MOD_ONE         2'h1
`define MOD_ZERO        2'h2
`define MOD_MINUS1      2'h3
// Memory source address
`define MEMDEST_PC      1'h0
`define MEMDEST_MH      1'h1

Line No.	Rev	Author	Line
1	2	ale500
2			`default_nettype none
3
4			`define RN_ACCD 4'h0
5			`define RN_IX 4'h1
6			`define RN_IY 4'h2
7			`define RN_U 4'h3
8			`define RN_S 4'h4
9			`define RN_PC 4'h5
10	16	ale500	//`define RN_MEM16 4'h6
11			//`define RN_IMM16 4'h7
12	2	ale500	`define RN_ACCA 4'h8
13			`define RN_ACCB 4'h9
14			`define RN_CC 4'ha
15			`define RN_DP 4'hb
16	16	ale500	//`define RN_MEM8 4'hc
17			//`define RN_IMM8 4'hd
18	2	ale500	`define RN_INV 4'hf
19
20
21			`// opcodes that need an ALU result`
22			`define NOP 5'b00000
23	9	ale500	`define SEXT 5'b00001
24			`define ST 5'b00010
25			`define BIT 5'b00011
26	2	ale500
27	9	ale500	`define LD 5'b00100 // in logic8
28			`define AND 5'b00101 // in logic8
29			`define OR 5'b00110 // in logic8
30			`define EOR 5'b00111 // in logic8
31			`define ADD 5'b01000 // in arith8
32			`define SUB 5'b01001 // in arith8
33			`define ADC 5'b01010 // in arith8
34			`define SBC 5'b01011 // in arith8
35
36			`define LSR 5'b10000
37	12	ale500	`define LSL 5'b10001
38			`define ROR 5'b10010
39	9	ale500	`define ROL 5'b10011
40			`define ASR 5'b10100
41			`define NEG 5'b10101
42			`define COM 5'b10110
43	12	ale500	`define INC 5'b11000 // encoding of least 2 bits must be like ADD/SUB
44			`define DEC 5'b11001
45	9	ale500	`define DAA 5'b11010
46			`define MUL 5'b11011
47	4	ale500	`define LEA 5'b11100
48	16	ale500	`define CLR 5'b11101
49			`define TST 5'b11110
50	2	ale500
51			`/* Sequencer states */`
52
53			`define SEQ_COLDRESET 'h00
54			`define SEQ_NMI 'h01
55			`define SEQ_SWI 'h02
56			`define SEQ_IRQ 'h03
57			`define SEQ_FIRQ 'h04
58			`define SEQ_SWI2 'h05
59			`define SEQ_SWI3 'h06
60			`define SEQ_UNDEF 'h07
61			`define SEQ_LOADPC 'h08
62			`define SEQ_FETCH 'h09
63			`define SEQ_FETCH_1 'h0a
64			`define SEQ_FETCH_2 'h0b
65			`define SEQ_FETCH_3 'h0c
66			`define SEQ_FETCH_4 'h0d
67			`define SEQ_FETCH_5 'h0e
68
69			`define SEQ_DECODE 'h0f
70	16	ale500	`define SEQ_DECODE_P23 'h10 // x
71	2	ale500
72	5	ale500	`define SEQ_GRAL_ALU 'h11
73			`define SEQ_GRAL_WBACK 'h12
74	6	ale500	`define SEQ_CWAI_STACK 'h13 // stacks registers
75			`define SEQ_CWAI_WAIT 'h14 // waits for an interrupt
76			`define SEQ_TFREXG 'h15
77	2	ale500
78	6	ale500	`define SEQ_IND_READ_EA 'h16 // offset 8 or 16 bits
79			`define SEQ_IND_READ_EA_1 'h17
80			`define SEQ_IND_READ_EA_2 'h18 // real operand from memory indirect
81			`define SEQ_IND_DECODE 'h19
82			`define SEQ_IND_DECODE_OFS 'h1a // used to load 8 or 16 bits offset
83			`define SEQ_JMP_LOAD_PC 'h1b
84	2	ale500
85
86	6	ale500	`define SEQ_JSR_PUSH 'h1c
87	16	ale500	`define SEQ_JSR_PUSH_L 'h1d // x
88			`define SEQ_RTS_POP_L 'h1e // x
89			`define SEQ_RTS_POP_H 'h1f // x
90	2	ale500
91			`define SEQ_PREPUSH 'h20
92			`define SEQ_PREPULL 'h21
93			`define SEQ_PUSH_WRITE_L 'h22
94			`define SEQ_PUSH_WRITE_L_1 'h23
95			`define SEQ_PUSH_WRITE_H 'h24
96			`define SEQ_PUSH_WRITE_H_1 'h25
97	6	ale500	`define SEQ_SYNC 'h26
98	2	ale500
99			`define SEQ_PC_READ_H 'h30
100			`define SEQ_PC_READ_H_1 'h31
101			`define SEQ_PC_READ_H_2 'h32
102			`define SEQ_PC_READ_L 'h33
103			`define SEQ_PC_READ_L_1 'h34
104			`define SEQ_PC_READ_L_2 'h35
105
106			`define SEQ_MEM_READ_H 'h36
107			`define SEQ_MEM_READ_H_1 'h37
108			`define SEQ_MEM_READ_H_2 'h38
109			`define SEQ_MEM_READ_L 'h39
110			`define SEQ_MEM_READ_L_1 'h3a
111			`define SEQ_MEM_READ_L_2 'h3b
112			`define SEQ_MEM_WRITE_H 'h3c
113			`define SEQ_MEM_WRITE_H_1 'h3d
114			`define SEQ_MEM_WRITE_L 'h3e
115			`define SEQ_MEM_WRITE_L_1 'h3f
116
117	9	ale500	`// flags used in MC6809_cpu.v`
118	2	ale500	`define FLAGI regs_o_CCR[5]
119			`define FLAGF regs_o_CCR[6]
120	9	ale500	`define FLAGE regs_o_CCR[7]
121	2	ale500
122			`define DFLAGC CCR[0]
123			`define DFLAGV CCR[1]
124			`define DFLAGZ CCR[2]
125			`define DFLAGN CCR[3]
126			`// some wires exist only for simulation`
127			`define SIMULATION 1
128			`// Adressing modes`
129			`define NONE 3'h0
130			`define IMMEDIATE 3'h1
131			`define INHERENT 3'h2
132			`define DIRECT 3'h3
133			`define INDEXED 3'h4
134			`define EXTENDED 3'h5
135			`define REL8 3'h6
136			`define REL16 3'h7
137
138			`// Address size`
139
140			`// memory transfer size, read or written, used for addresses`
141			`define MSZ_0 2'h0
142			`define MSZ_8 2'h1
143			`define MSZ_16 2'h2
144			`// Data transfer size, to save to register, used for data from memory and to save results to memory/registers`
145			`define DSZ_0 2'h0
146			`define DSZ_8 2'h1
147			`define DSZ_16 2'h2
148	16	ale500	`/* Memory access type for input/output operands */`
149			`define MT_NONE 3'h0
150			`define MT_BYTE 3'h1
151			`define MT_WORD 3'h2
152			`define MT_QUAD 3'h3
153	2	ale500
154			`/* alu decoder right path modifier */`
155			`define MOD_DEFAULT 2'h0
156			`define MOD_ONE 2'h1
157			`define MOD_ZERO 2'h2
158			`define MOD_MINUS1 2'h3
159	16	ale500	`// Memory source address`
160			`define MEMDEST_PC 1'h0
161			`define MEMDEST_MH 1'h1

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[/] [6809_6309_compatible_core/] [trunk/] [rtl/] [verilog/] [defs.v] - Blame information for rev 16