Subversion Repositories 6809_6309_compatible_core

$date

        Mon Jan  6 06:54:14 2014

$end

$version

        Icarus Verilog

$end

$timescale

        1ns

$end

$scope module tb $end

$var wire 16 ! addr_o [15:0] $end

$var wire 8 " data_o_o [7:0] $end

$var wire 1 # we $end

$var wire 1 $ oe $end

$var wire 8 % data_o [7:0] $end

$var wire 8 & data_i [7:0] $end

$var wire 16 ' addr [15:0] $end

$var reg 1 ( clk $end

$var reg 1 ) reset $end

$scope module cpu $end

$var wire 1 ( cpu_clk $end

$var wire 1 * cpu_firq_n $end

$var wire 1 + cpu_irq_n $end

$var wire 1 , cpu_nmi_n $end

$var wire 1 ) cpu_reset $end

$var wire 6 - cpu_state_o [5:0] $end

$var wire 1 . k_firq_req $end

$var wire 1 / k_irq_req $end

$var wire 1 0 k_nmi_req $end

$var wire 1 1 k_reset $end

$var wire 16 2 regs_o_su [15:0] $end

$var wire 16 3 regs_o_right_path_data [15:0] $end

$var wire 16 4 regs_o_pc [15:0] $end

$var wire 16 5 regs_o_left_path_data [15:0] $end

$var wire 16 6 regs_o_eamem_addr [15:0] $end

$var wire 8 7 regs_o_dp [7:0] $end

$var wire 8 8 regs_o_CCR [7:0] $end

$var wire 1 9 dec_o_write_flags $end

$var wire 1 : dec_o_wdest $end

$var wire 1 ; dec_o_use_s $end

$var wire 1 < dec_o_source_size $end

$var wire 2 = dec_o_right_path_mod [1:0] $end

$var wire 4 > dec_o_right_path_addr [3:0] $end

$var wire 3 ? dec_o_p1_optype [2:0] $end

$var wire 3 @ dec_o_p1_mode [2:0] $end

$var wire 4 A dec_o_left_path_addr [3:0] $end

$var wire 1 B dec_o_ea_wpost $end

$var wire 1 C dec_o_ea_ofs8 $end

$var wire 1 D dec_o_ea_ofs16 $end

$var wire 1 E dec_o_ea_ofs0 $end

$var wire 1 F dec_o_ea_indirect $end

$var wire 4 G dec_o_dest_reg_addr [3:0] $end

$var wire 1 H dec_o_cond_taken $end

$var wire 1 I dec_o_alu_size $end

$var wire 5 J dec_o_alu_opcode [4:0] $end

$var wire 1 # cpu_we_o $end

$var wire 1 $ cpu_oe_o $end

$var wire 8 K cpu_data_o [7:0] $end

$var wire 8 L cpu_data_i [7:0] $end

$var wire 16 M cpu_addr_o [15:0] $end

$var wire 16 N alu_o_result [15:0] $end

$var wire 8 O alu_o_CCR [7:0] $end

$var reg 4 P datamux_o_alu_in_left_path_addr [3:0] $end

$var reg 16 Q datamux_o_alu_in_left_path_data [15:0] $end

$var reg 16 R datamux_o_alu_in_right_path_data [15:0] $end

$var reg 16 S datamux_o_dest [15:0] $end

$var reg 4 T datamux_o_dest_reg_addr [3:0] $end

$var reg 1 U k_clear_e $end

$var reg 16 V k_cpu_addr [15:0] $end

$var reg 8 W k_cpu_data_o [7:0] $end

$var reg 1 $ k_cpu_oe $end

$var reg 1 # k_cpu_we $end

$var reg 1 X k_dec_su $end

$var reg 8 Y k_eahi [7:0] $end

$var reg 8 Z k_ealo [7:0] $end

$var reg 1 [ k_forced_mem_size $end

$var reg 1 \ k_inc_pc $end

$var reg 1 ] k_inc_su $end

$var reg 8 ^ k_ind_ea [7:0] $end

$var reg 2 _ k_mem_dest [1:0] $end

$var reg 8 ` k_memhi [7:0] $end

$var reg 8 a k_memlo [7:0] $end

$var reg 1 b k_mul_cnt $end

$var reg 16 c k_new_pc [15:0] $end

$var reg 8 d k_ofshi [7:0] $end

$var reg 8 e k_ofslo [7:0] $end

$var reg 8 f k_opcode [7:0] $end

$var reg 1 g k_p2_valid $end

$var reg 1 h k_p3_valid $end

$var reg 8 i k_postbyte [7:0] $end

$var reg 4 j k_pp_active_reg [3:0] $end

$var reg 8 k k_pp_regs [7:0] $end

$var reg 3 l k_reg_firq [2:0] $end

$var reg 3 m k_reg_irq [2:0] $end

$var reg 3 n k_reg_nmi [2:0] $end

$var reg 1 o k_set_e $end

$var reg 1 p k_write_dest $end

$var reg 1 q k_write_exg $end

$var reg 1 r k_write_pc $end

$var reg 1 s k_write_post_incdec $end

$var reg 1 t k_write_tfr $end

$var reg 6 u next_mem_state [5:0] $end

$var reg 6 v next_push_state [5:0] $end

$var reg 6 w next_state [5:0] $end

$var reg 6 x state [5:0] $end

$scope module alu $end

$var wire 16 y a_in [15:0] $end

$var wire 16 z b_in [15:0] $end

$var wire 1 ( clk_in $end

$var wire 1 I sz_in $end

$var wire 8 { q8_out [7:0] $end

$var wire 16 | q16_out [15:0] $end

$var wire 5 } opcode_in [4:0] $end

$var wire 8 ~ ccr8_out [7:0] $end

$var wire 4 !" ccr16_out [3:0] $end

$var wire 8 "" CCR [7:0] $end

$var reg 8 #" CCRo [7:0] $end

$var reg 16 $" q_out [15:0] $end

$var reg 16 %" ra_in [15:0] $end

$var reg 16 &" rb_in [15:0] $end

$var reg 5 '" rop_in [4:0] $end

$scope module alu16 $end

$var wire 16 (" a_in [15:0] $end

$var wire 16 )" b_in [15:0] $end

$var wire 1 ( clk_in $end

$var wire 5 *" opcode_in [4:0] $end

$var wire 1 +" z_in $end

$var wire 1 ," v_in $end

$var wire 16 -" q16_mul [15:0] $end

$var wire 1 ." n_in $end

$var wire 1 /" c_in $end

$var wire 1 0" arith_v $end

$var wire 16 1" arith_q [15:0] $end

$var wire 1 2" arith_c $end

$var wire 8 3" CCR [7:0] $end

$var reg 4 4" CCRo [3:0] $end

$var reg 1 5" c16 $end

$var reg 1 6" n16 $end

$var reg 16 7" q16 [15:0] $end

$var reg 16 8" q_out [15:0] $end

$var reg 1 9" reg_n_in $end

$var reg 1 :" reg_z_in $end

$var reg 16 ;" regq16 [15:0] $end

$var reg 1 <" v16 $end

$var reg 1 =" z16 $end

$scope module a16 $end

$var wire 16 >" a_in [15:0] $end

$var wire 16 ?" b_in [15:0] $end

$var wire 1 /" carry_in $end

$var wire 2 @" opcode_in [1:0] $end

$var reg 1 2" carry_out $end

$var reg 1 0" overflow_out $end

$var reg 16 A" q_out [15:0] $end

$upscope $end

$scope module mulu $end

$var wire 8 B" a [7:0] $end

$var wire 8 C" b [7:0] $end

$var wire 1 ( clk_in $end

$var wire 16 D" q [15:0] $end

$var reg 16 E" pipe0 [15:0] $end

$var reg 16 F" pipe1 [15:0] $end

$upscope $end

$upscope $end

$scope module alu8 $end

$var wire 8 G" a_in [7:0] $end

$var wire 8 H" b_in [7:0] $end

$var wire 1 ( clk_in $end

$var wire 1 I" cneg8_r $end

$var wire 8 J" com8_r [7:0] $end

$var wire 8 K" com8_w [7:0] $end

$var wire 8 L" neg8_r [7:0] $end

$var wire 5 M" opcode_in [4:0] $end

$var wire 1 N" vcom8_r $end

$var wire 1 O" vneg8_r $end

$var wire 1 P" z_in $end

$var wire 1 Q" v_in $end

$var wire 1 R" shift_v $end

$var wire 8 S" shift_q [7:0] $end

$var wire 1 T" shift_c $end

$var wire 8 U" neg8_w [7:0] $end

$var wire 1 V" n_in $end

$var wire 8 W" logic_q [7:0] $end

$var wire 1 X" h_in $end

$var wire 1 Y" daa_lnm9 $end

$var wire 4 Z" daa8l_r [3:0] $end

$var wire 4 [" daa8h_r [3:0] $end

$var wire 1 \" cdaa8_r $end

$var wire 1 ]" ccom8_r $end

$var wire 1 ^" c_in $end

$var wire 1 _" arith_v $end

$var wire 8 `" arith_q [7:0] $end

$var wire 1 a" arith_h $end

$var wire 1 b" arith_c $end

$var wire 8 c" CCR [7:0] $end

$var reg 8 d" CCRo [7:0] $end

$var reg 1 e" c8 $end

$var reg 1 f" h8 $end

$var reg 8 g" q8 [7:0] $end

$var reg 8 h" q_out [7:0] $end

$var reg 8 i" regq8 [7:0] $end

$var reg 1 j" v8 $end

$scope module a8 $end

$var wire 8 k" a_in [7:0] $end

$var wire 8 l" b_in [7:0] $end

$var wire 1 ^" carry_in $end

$var wire 1 X" half_c_in $end

$var wire 2 m" opcode_in [1:0] $end

$var reg 1 b" carry_out $end

$var reg 1 a" half_c_out $end

$var reg 1 _" overflow_out $end

$var reg 8 n" q_out [7:0] $end

$upscope $end

$scope module l8 $end

$var wire 8 o" a_in [7:0] $end

$var wire 8 p" b_in [7:0] $end

$var wire 2 q" opcode_in [1:0] $end

$var reg 8 r" q_out [7:0] $end

$upscope $end

$scope module s8 $end

$var wire 8 s" a_in [7:0] $end

$var wire 8 t" b_in [7:0] $end

$var wire 1 ^" carry_in $end

$var wire 3 u" opcode_in [2:0] $end

$var wire 1 Q" overflow_in $end

$var wire 1 T" carry_out $end

$var reg 1 R" overflow_out $end

$var reg 8 v" q_out [7:0] $end

$upscope $end

$upscope $end

$upscope $end

$scope module dec_alu $end

$var wire 8 w" opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 x" postbyte0 [7:0] $end

$var wire 1 9 dest_flags $end

$var reg 5 y" alu_opcode [4:0] $end

$var reg 2 z" dec_alu_right_path_mod [1:0] $end

$upscope $end

$scope module dec_ea $end

$var wire 8 {" eapostbyte [7:0] $end

$var wire 1 F isind $end

$var reg 1 E noofs $end

$var reg 1 D ofs16 $end

$var reg 1 C ofs8 $end

$var reg 1 B write_post $end

$upscope $end

$scope module dec_op $end

$var wire 8 |" opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 }" postbyte0 [7:0] $end

$var wire 4 ~" oplo [3:0] $end

$var reg 3 !# mode [2:0] $end

$var reg 3 "# optype [2:0] $end

$var reg 1 ## size $end

$var reg 1 ; use_s $end

$upscope $end

$scope module dec_regs $end

$var wire 1 ( cpu_clk $end

$var wire 8 $# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 1 h page3_valid $end

$var wire 8 %# postbyte0 [7:0] $end

$var wire 1 : write_dest $end

$var wire 1 < source_size $end

$var wire 1 I result_size $end

$var reg 4 &# dest_reg [3:0] $end

$var reg 4 '# dest_reg_o [3:0] $end

$var reg 4 (# path_left_addr [3:0] $end

$var reg 4 )# path_left_addr_o [3:0] $end

$var reg 4 *# path_right_addr [3:0] $end

$var reg 4 +# path_right_addr_o [3:0] $end

$upscope $end

$scope module regs $end

$var wire 8 ,# CCR_in [7:0] $end

$var wire 1 U clear_e $end

$var wire 1 ( clk_in $end

$var wire 16 -# data_w [15:0] $end

$var wire 1 X dec_su $end

$var wire 16 .# eamem_addr_o [15:0] $end

$var wire 8 /# eapostbyte [7:0] $end

$var wire 4 0# exg_dest_r [3:0] $end

$var wire 1 \ inc_pc $end

$var wire 1 ] inc_su $end

$var wire 16 1# new_pc [15:0] $end

$var wire 16 2# offset16 [15:0] $end

$var wire 4 3# path_left_addr [3:0] $end

$var wire 4 4# path_right_addr [3:0] $end

$var wire 8 5# reg_dp [7:0] $end

$var wire 16 6# reg_pc [15:0] $end

$var wire 1 o set_e $end

$var wire 1 ; use_s $end

$var wire 1 q write_exg $end

$var wire 1 7# write_flags $end

$var wire 1 r write_pc $end

$var wire 1 s write_post $end

$var wire 1 p write_reg $end

$var wire 4 8# write_reg_addr [3:0] $end

$var wire 1 t write_tfr $end

$var wire 4 9# right_reg [3:0] $end

$var wire 16 :# right [15:0] $end

$var wire 16 ;# reg_su [15:0] $end

$var wire 16 <# pc_plus_1 [15:0] $end

$var wire 16 =# left [15:0] $end

$var wire 16 ># eamem_addr [15:0] $end

$var wire 16 ?# ea_reg_post [15:0] $end

$var wire 8 @# CCR_o [7:0] $end

$var reg 8 A# ACCA [7:0] $end

$var reg 8 B# ACCB [7:0] $end

$var reg 8 C# DP [7:0] $end

$var reg 16 D# IX [15:0] $end

$var reg 16 E# IY [15:0] $end

$var reg 16 F# PC [15:0] $end

$var reg 16 G# SS [15:0] $end

$var reg 16 H# SU [15:0] $end

$var reg 1 I# cff $end

$var reg 1 J# eflag $end

$var reg 1 K# fflag $end

$var reg 1 L# hflag $end

$var reg 1 M# intff $end

$var reg 1 N# nff $end

$var reg 16 O# path_left_data [15:0] $end

$var reg 16 P# path_right_data [15:0] $end

$var reg 1 Q# vff $end

$var reg 1 R# zff $end

$scope module ea $end

$var wire 8 S# acca [7:0] $end

$var wire 8 T# accb [7:0] $end

$var wire 16 U# ea_reg_post_o [15:0] $end

$var wire 16 V# eamem_addr_o [15:0] $end

$var wire 8 W# eapostbyte [7:0] $end

$var wire 16 X# ix [15:0] $end

$var wire 16 Y# iy [15:0] $end

$var wire 16 Z# offset16 [15:0] $end

$var wire 16 [# pc [15:0] $end

$var wire 16 \# s [15:0] $end

$var wire 16 ]# u [15:0] $end

$var reg 16 ^# ea_reg [15:0] $end

$var reg 16 _# ea_reg_post [15:0] $end

$var reg 16 `# eamem_addr [15:0] $end

$upscope $end

$upscope $end

$scope module test_cond $end

$var wire 8 a# CCR [7:0] $end

$var wire 8 b# opcode [7:0] $end

$var wire 1 g page2_valid $end

$var wire 8 c# postbyte0 [7:0] $end

$var wire 8 d# op [7:0] $end

$var reg 1 H cond_taken $end

$upscope $end

$upscope $end

$scope module imem $end

$var wire 16 e# addr [15:0] $end

$var wire 8 f# data_i [7:0] $end

$var wire 8 g# data_o [7:0] $end

$var wire 8 h# mem0 [7:0] $end

$var wire 8 i# mem1 [7:0] $end

$var wire 8 j# mem2 [7:0] $end

$var wire 8 k# mem3 [7:0] $end

$var wire 1 l# oe $end

$var wire 1 m# we $end

$var reg 8 n# latecheddata [7:0] $end

$upscope $end

$upscope $end

$enddefinitions $end

#0

$dumpvars

bx n#

1m#

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b111101 k#

b10111011 j#

b10101010 i#

b11001100 h#

bx g#

bx f#

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b111000000000 ]#

b111100000000 \#

b1111111111111110 [#

bx Z#

b1010010101011010 Y#

b0 X#

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b1111111111111111 O#

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b111000000000 H#

b111100000000 G#

b1111111111111110 F#

b1010010101011010 E#

b0 D#

b0 C#

bx B#

bx A#

b0 @#

bx ?#

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b1111111111111111 <#

b111x00000000 ;#

b1111111111111111 :#

bx 9#

bx 8#

07#

b1111111111111110 6#

b0 5#

bx 4#

bx 3#

bx 2#

bx 1#

bx 0#

bx /#

bx .#

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bx +#

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b0 x

bx w

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bx P

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$end

#5

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b1111111111111111 ("

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b110110 -

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b1111111111111110 '

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b1111111111111110 e#

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