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/* MC6809/HD6309 Compatible core
 * (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com
 *
 * Distributed under the terms of the Lesser GPL
 */
`timescale 1ns/1ns
`include "MC6809_cpu.v"
`include "alu16.v"
`include "decoders.v"
`include "regblock.v"
 
module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);
 
reg clk, reset;
 
assign addr_o = addr;
assign data_o_o = data_o;
wire [15:0] addr;
wire [7:0] data_o, data_i;
wire oe, we;
always
        #5 clk = ~clk;
 
MC6809_cpu cpu(
        .cpu_clk(clk),
        .cpu_reset_n(reset),
        .cpu_we_o(we),
        .cpu_oe_o(oe),
        .cpu_addr_o(addr),
        .cpu_data_i(data_i),
        .cpu_data_o(data_o)
        );
 
memory imem(addr, !oe, !we, data_i, data_o);
 
initial
        begin
                $dumpvars;
                clk = 0;
                reset = 0;
                #0
                #46
                reset = 1;
                #2000
                $finish;
        end
 
endmodule
 
module memory(
        input wire [15:0] addr,
        input wire oe,
        input wire we,
        output wire [7:0] data_o,
        input wire [7:0] data_i
        );
 
reg [7:0] mem[65535:0];
reg [7:0] latecheddata;
wire [7:0] mem0, mem1, mem2, mem3;
 
assign mem0 = mem[0];
assign mem1 = mem[1];
assign mem2 = mem[2];
assign mem3 = mem[3];
 
assign data_o = latecheddata;
always @(negedge oe)
        latecheddata <= mem[addr];
 
always @(negedge we)
        begin
                mem[addr] <= data_i;
                $display("W %04x = %02x %t", addr, data_i, $time);
        end
 
always @(negedge oe)
        begin
                $display("R %04x = %02x %t", addr, mem[addr], $time);
        end
//`define READTESTBIN
integer i;
initial
        begin
`ifdef READTESTBIN
                $readmemh("instructions_test.hex", mem);
                $display("instructions_test.hex read");
                mem[16'hfffe] = 8'h00; // setup reset
                mem[16'hffff] = 8'h00;
`else
                for (i = 0; i < 65536; i=i+1)
                        mem[i] = 8'ha5;
 
                mem[16'h1000] = 8'h3f; // lda #$10
                mem[16'h1001] = 8'h10; // 
                mem[16'h1002] = 8'hc6; // ldb #$12
                mem[16'h1003] = 8'h12; // 
 
                mem[16'h1004] = 8'h3d; // mul
                mem[16'h1005] = 8'h4c; // inca
                mem[16'h1006] = 8'h5c; // incb
 
                mem[16'h1007] = 8'h9d; // jsr
                mem[16'h1008] = 8'h0e; // 
                mem[16'h1009] = 8'h12; // nop
 
                mem[16'h100a] = 8'h20; // bre *
                mem[16'h100b] = 8'hfe; // 
                mem[16'h100c] = 8'h12; // 
                mem[16'h100d] = 8'h39; // 
                mem[16'h100e] = 8'h39; // 
 
                mem[16'h2000] = 8'h3b; // rti
                mem[16'h2002] = 8'h3b; // rti
                mem[16'h2004] = 8'h3b; // rti
                mem[16'h2006] = 8'h3b; // rti
                mem[16'h2008] = 8'h3b; // rti
                mem[16'h200a] = 8'h3b; // rti
                mem[16'h200c] = 8'h3b; // rti
                mem[16'h200e] = 8'h3b; // rti
 
 
/*
// test indexed store
                mem[16'h1000] = 8'h86; // lda #$fe
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha7; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha7; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha7; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha7; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha7; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha7; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha7; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test indexed load
                mem[16'h1000] = 8'h86; // lda #$02
                mem[16'h1001] = 8'h02; //
                mem[16'h1002] = 8'h9e; // ldx $00 (direct)
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'ha6; // lda ,x
                mem[16'h1005] = 8'b10000100; // ofs0
                mem[16'h1006] = 8'ha6; // lda ,x+
                mem[16'h1007] = 8'b10000000; //
 
 
                mem[16'h1008] = 8'ha6; // lda ,x++
                mem[16'h1009] = 8'b10000001; //
                mem[16'h100a] = 8'ha6; // lda ,-x
                mem[16'h100b] = 8'b10000010; //
 
                mem[16'h100c] = 8'ha6; // lda ,--x
                mem[16'h100d] = 8'b10000011; //
 
                mem[16'h100e] = 8'ha6; // lda 0,x ofs 5
                mem[16'h100f] = 8'h00; //
 
                mem[16'h1010] = 8'ha6; // lda 0,x ofs 8
                mem[16'h1011] = 8'b10001000; //
                mem[16'h1012] = 8'h00; //
 
                mem[16'h1013] = 8'ha6; // lda 0,x ofs 16
                mem[16'h1014] = 8'b10001001; //
                mem[16'h1015] = 8'h00; //
                mem[16'h1016] = 8'h00; //
*/
 
/* test extended
                mem[16'h1000] = 8'hc6; // ldb #$fe
                mem[16'h1001] = 8'hfe; //
                mem[16'h1002] = 8'h86; // lda #$0
                mem[16'h1003] = 8'h00; //
 
                mem[16'h1004] = 8'h4c; // inca
                mem[16'h1005] = 8'hb7; // sta $0000
                mem[16'h1006] = 8'h00; //
                mem[16'h1007] = 8'h00; //
 
 
                mem[16'h1008] = 8'hb6; // lda $0000
                mem[16'h1009] = 8'h00; //
                mem[16'h100a] = 8'h00; //
 
                mem[16'h100b] = 8'h26; // bne$.-5
                mem[16'h100c] = 8'hf7; //
 
                mem[16'h100d] = 8'h5c; // incb
 
                mem[16'h100e] = 8'hf7; // stb $0001
                mem[16'h100f] = 8'h00; //
                mem[16'h1010] = 8'h01; //
 
                mem[16'h1011] = 8'h20; // bra
                mem[16'h1012] = 8'hec; // $.-18
*/
                mem[16'hfff0] = 8'h20; // reset
                mem[16'hfff1] = 8'h00;
                mem[16'hfff2] = 8'h20; // reset
                mem[16'hfff3] = 8'h02;
                mem[16'hfff4] = 8'h20; // reset
                mem[16'hfff5] = 8'h04;
                mem[16'hfff6] = 8'h20; // reset
                mem[16'hfff7] = 8'h06;
                mem[16'hfff8] = 8'h20; // reset
                mem[16'hfff9] = 8'h08;
                mem[16'hfffa] = 8'h20; // reset
                mem[16'hfffb] = 8'h0a;
                mem[16'hfffc] = 8'h20; // reset
                mem[16'hfffd] = 8'h0c;
                mem[16'hfffe] = 8'h10; // reset
                mem[16'hffff] = 8'h00;
`endif
        end
 
endmodule

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[/] [6809_6309_compatible_core/] [trunk/] [sim/] [tb.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	ale500	`/* MC6809/HD6309 Compatible core`
2			`* (c) 2013 R.A. Paz Schmidt rapazschmidt@gmail.com`
3			`*`
4			`* Distributed under the terms of the Lesser GPL`
5			`*/`
6			`timescale 1ns/1ns
7			`include "MC6809_cpu.v"
8			`include "alu16.v"
9			`include "decoders.v"
10			`include "regblock.v"
11
12			`module tb(output wire [15:0] addr_o, output wire [7:0] data_o_o);`
13
14			`reg clk, reset;`
15
16			`assign addr_o = addr;`
17			`assign data_o_o = data_o;`
18			`wire [15:0] addr;`
19			`wire [7:0] data_o, data_i;`
20			`wire oe, we;`
21			`always`
22			`#5 clk = ~clk;`
23
24			`MC6809_cpu cpu(`
25			`.cpu_clk(clk),`
26			`.cpu_reset_n(reset),`
27			`.cpu_we_o(we),`
28			`.cpu_oe_o(oe),`
29			`.cpu_addr_o(addr),`
30			`.cpu_data_i(data_i),`
31			`.cpu_data_o(data_o)`
32			`);`
33
34			`memory imem(addr, !oe, !we, data_i, data_o);`
35
36			`initial`
37			`begin`
38			`$dumpvars;`
39			`clk = 0;`
40			`reset = 0;`
41			`#0`
42			`#46`
43			`reset = 1;`
44			`#2000`
45			`$finish;`
46			`end`
47
48			`endmodule`
49
50			`module memory(`
51			`input wire [15:0] addr,`
52			`input wire oe,`
53			`input wire we,`
54			`output wire [7:0] data_o,`
55			`input wire [7:0] data_i`
56			`);`
57
58			`reg [7:0] mem[65535:0];`
59			`reg [7:0] latecheddata;`
60			`wire [7:0] mem0, mem1, mem2, mem3;`
61
62			`assign mem0 = mem[0];`
63			`assign mem1 = mem[1];`
64			`assign mem2 = mem[2];`
65			`assign mem3 = mem[3];`
66
67			`assign data_o = latecheddata;`
68			`always @(negedge oe)`
69			`latecheddata <= mem[addr];`
70
71			`always @(negedge we)`
72			`begin`
73			`mem[addr] <= data_i;`
74			`$display("W %04x = %02x %t", addr, data_i, $time);`
75			`end`
76
77			`always @(negedge oe)`
78			`begin`
79			`$display("R %04x = %02x %t", addr, mem[addr], $time);`
80			`end`
81			//`define READTESTBIN
82			`integer i;`
83			`initial`
84			`begin`
85			`ifdef READTESTBIN
86			`$readmemh("instructions_test.hex", mem);`
87			`$display("instructions_test.hex read");`
88			`mem[16'hfffe] = 8'h00; // setup reset`
89			`mem[16'hffff] = 8'h00;`
90			`else
91			`for (i = 0; i < 65536; i=i+1)`
92			`mem[i] = 8'ha5;`
93
94			`mem[16'h1000] = 8'h3f; // lda #$10`
95			`mem[16'h1001] = 8'h10; //`
96			`mem[16'h1002] = 8'hc6; // ldb #$12`
97			`mem[16'h1003] = 8'h12; //`
98
99			`mem[16'h1004] = 8'h3d; // mul`
100			`mem[16'h1005] = 8'h4c; // inca`
101			`mem[16'h1006] = 8'h5c; // incb`
102
103			`mem[16'h1007] = 8'h9d; // jsr`
104			`mem[16'h1008] = 8'h0e; //`
105			`mem[16'h1009] = 8'h12; // nop`
106
107			`mem[16'h100a] = 8'h20; // bre *`
108			`mem[16'h100b] = 8'hfe; //`
109			`mem[16'h100c] = 8'h12; //`
110			`mem[16'h100d] = 8'h39; //`
111			`mem[16'h100e] = 8'h39; //`
112
113			`mem[16'h2000] = 8'h3b; // rti`
114			`mem[16'h2002] = 8'h3b; // rti`
115			`mem[16'h2004] = 8'h3b; // rti`
116			`mem[16'h2006] = 8'h3b; // rti`
117			`mem[16'h2008] = 8'h3b; // rti`
118			`mem[16'h200a] = 8'h3b; // rti`
119			`mem[16'h200c] = 8'h3b; // rti`
120			`mem[16'h200e] = 8'h3b; // rti`
121
122
123			`/*`
124			`// test indexed store`
125			`mem[16'h1000] = 8'h86; // lda #$fe`
126			`mem[16'h1001] = 8'h02; //`
127			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
128			`mem[16'h1003] = 8'h00; //`
129
130			`mem[16'h1004] = 8'ha7; // lda ,x`
131			`mem[16'h1005] = 8'b10000100; // ofs0`
132			`mem[16'h1006] = 8'ha7; // lda ,x+`
133			`mem[16'h1007] = 8'b10000000; //`
134
135
136			`mem[16'h1008] = 8'ha7; // lda ,x++`
137			`mem[16'h1009] = 8'b10000001; //`
138			`mem[16'h100a] = 8'ha6; // lda ,-x`
139			`mem[16'h100b] = 8'b10000010; //`
140
141			`mem[16'h100c] = 8'ha7; // lda ,--x`
142			`mem[16'h100d] = 8'b10000011; //`
143
144			`mem[16'h100e] = 8'ha7; // lda 0,x ofs 5`
145			`mem[16'h100f] = 8'h00; //`
146
147			`mem[16'h1010] = 8'ha7; // lda 0,x ofs 8`
148			`mem[16'h1011] = 8'b10001000; //`
149			`mem[16'h1012] = 8'h00; //`
150
151			`mem[16'h1013] = 8'ha7; // lda 0,x ofs 16`
152			`mem[16'h1014] = 8'b10001001; //`
153			`mem[16'h1015] = 8'h00; //`
154			`mem[16'h1016] = 8'h00; //`
155			`*/`
156
157			`/* test indexed load`
158			`mem[16'h1000] = 8'h86; // lda #$02`
159			`mem[16'h1001] = 8'h02; //`
160			`mem[16'h1002] = 8'h9e; // ldx $00 (direct)`
161			`mem[16'h1003] = 8'h00; //`
162
163			`mem[16'h1004] = 8'ha6; // lda ,x`
164			`mem[16'h1005] = 8'b10000100; // ofs0`
165			`mem[16'h1006] = 8'ha6; // lda ,x+`
166			`mem[16'h1007] = 8'b10000000; //`
167
168
169			`mem[16'h1008] = 8'ha6; // lda ,x++`
170			`mem[16'h1009] = 8'b10000001; //`
171			`mem[16'h100a] = 8'ha6; // lda ,-x`
172			`mem[16'h100b] = 8'b10000010; //`
173
174			`mem[16'h100c] = 8'ha6; // lda ,--x`
175			`mem[16'h100d] = 8'b10000011; //`
176
177			`mem[16'h100e] = 8'ha6; // lda 0,x ofs 5`
178			`mem[16'h100f] = 8'h00; //`
179
180			`mem[16'h1010] = 8'ha6; // lda 0,x ofs 8`
181			`mem[16'h1011] = 8'b10001000; //`
182			`mem[16'h1012] = 8'h00; //`
183
184			`mem[16'h1013] = 8'ha6; // lda 0,x ofs 16`
185			`mem[16'h1014] = 8'b10001001; //`
186			`mem[16'h1015] = 8'h00; //`
187			`mem[16'h1016] = 8'h00; //`
188			`*/`
189
190			`/* test extended`
191			`mem[16'h1000] = 8'hc6; // ldb #$fe`
192			`mem[16'h1001] = 8'hfe; //`
193			`mem[16'h1002] = 8'h86; // lda #$0`
194			`mem[16'h1003] = 8'h00; //`
195
196			`mem[16'h1004] = 8'h4c; // inca`
197			`mem[16'h1005] = 8'hb7; // sta $0000`
198			`mem[16'h1006] = 8'h00; //`
199			`mem[16'h1007] = 8'h00; //`
200
201
202			`mem[16'h1008] = 8'hb6; // lda $0000`
203			`mem[16'h1009] = 8'h00; //`
204			`mem[16'h100a] = 8'h00; //`
205
206			`mem[16'h100b] = 8'h26; // bne$.-5`
207			`mem[16'h100c] = 8'hf7; //`
208
209			`mem[16'h100d] = 8'h5c; // incb`
210
211			`mem[16'h100e] = 8'hf7; // stb $0001`
212			`mem[16'h100f] = 8'h00; //`
213			`mem[16'h1010] = 8'h01; //`
214
215			`mem[16'h1011] = 8'h20; // bra`
216			`mem[16'h1012] = 8'hec; // $.-18`
217			`*/`
218			`mem[16'hfff0] = 8'h20; // reset`
219			`mem[16'hfff1] = 8'h00;`
220			`mem[16'hfff2] = 8'h20; // reset`
221			`mem[16'hfff3] = 8'h02;`
222			`mem[16'hfff4] = 8'h20; // reset`
223			`mem[16'hfff5] = 8'h04;`
224			`mem[16'hfff6] = 8'h20; // reset`
225			`mem[16'hfff7] = 8'h06;`
226			`mem[16'hfff8] = 8'h20; // reset`
227			`mem[16'hfff9] = 8'h08;`
228			`mem[16'hfffa] = 8'h20; // reset`
229			`mem[16'hfffb] = 8'h0a;`
230			`mem[16'hfffc] = 8'h20; // reset`
231			`mem[16'hfffd] = 8'h0c;`
232			`mem[16'hfffe] = 8'h10; // reset`
233			`mem[16'hffff] = 8'h00;`
234			`endif
235			`end`
236
237			`endmodule`