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PAR: Place And Route Diamond (64-bit) 3.1.0.96.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
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Sun Jul 06 07:47:00 2014
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C:/lscc/diamond/3.1_x64/ispfpga\bin\nt64\par -f P6809_P6809.p2t
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P6809_P6809_map.ncd P6809_P6809.dir P6809_P6809.prf -gui
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Preference file: P6809_P6809.prf.
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Level/ Number Worst Timing Worst Timing Run NCD
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Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
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---------- -------- ----- ------ ----------- ----------- ----- ------
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5_1 * 0 - - - - 14 Complete
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* : Design saved.
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Total (real) run time for 1-seed: 14 secs
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par done!
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Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
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Sun Jul 06 07:47:00 2014
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PAR: Place And Route Diamond (64-bit) 3.1.0.96.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
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Preference file: P6809_P6809.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file P6809_P6809_map.ncd.
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Design name: CC3_top
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NCD version: 3.2
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Vendor: LATTICE
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Device: LCMXO2-7000HE
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Package: TQFP144
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Performance: 4
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Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.1_x64/ispfpga.
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Package Status: Final Version 1.36
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Performance Hardware Data Status: Final) Version 23.4
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License checked out.
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Ignore Preference Error(s): True
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Device utilization summary:
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PIO (prelim) 69+4(JTAG)/336 22% used
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69+4(JTAG)/115 63% bonded
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IOLOGIC 10/336 2% used
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SLICE 1234/3432 35% used
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GSR 1/1 100% used
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EBR 10/26 38% used
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INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
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INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
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Number of Signals: 2876
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Number of Connections: 9723
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Pin Constraint Summary:
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68 out of 68 pins locked (100% locked).
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The following 1 signal is selected to use the primary clock routing resources:
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clk40_i_c (driver: clk40_i, clk load #: 318)
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The following 3 signals are selected to use the secondary clock routing resources:
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cpu0/G_9 (driver: cpu0/SLICE_837, clk load #: 0, sr load #: 0, ce load #: 111)
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cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_744, clk load #: 0, sr load #: 0, ce load #: 17)
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cpu0/regs/PC_0_sqmuxa_1_i_o2_RNIHDJD1 (driver: cpu0/regs/SLICE_887, clk load #: 0, sr load #: 0, ce load #: 16)
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Signal reset_o_c is selected as Global Set/Reset.
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.
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Starting Placer Phase 0.
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............
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Finished Placer Phase 0. REAL time: 2 secs
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Starting Placer Phase 1.
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........................
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Placer score = 779607.
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Finished Placer Phase 1. REAL time: 6 secs
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Starting Placer Phase 2.
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.
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Placer score = 774076
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Finished Placer Phase 2. REAL time: 7 secs
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------------------ Clock Report ------------------
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Global Clock Resources:
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CLK_PIN : 1 out of 8 (12%)
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PLL : 0 out of 2 (0%)
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DCM : 0 out of 2 (0%)
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DCC : 0 out of 8 (0%)
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Quadrants All (TL, TR, BL, BR) - Global Clocks:
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PRIMARY "clk40_i_c" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 318
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SECONDARY "cpu0/G_9" from F0 on comp "cpu0/SLICE_837" on site "R21C18A", clk load = 0, ce load = 111, sr load = 0
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SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_744" on site "R21C18B", clk load = 0, ce load = 17, sr load = 0
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SECONDARY "cpu0/regs/PC_0_sqmuxa_1_i_o2_RNIHDJD1" from F1 on comp "cpu0/regs/SLICE_887" on site "R14C20A", clk load = 0, ce load = 16, sr load = 0
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PRIMARY : 1 out of 8 (12%)
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SECONDARY: 3 out of 8 (37%)
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Edge Clocks:
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No edge clock selected.
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--------------- End of Clock Report ---------------
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I/O Usage Summary (final):
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69 + 4(JTAG) out of 336 (21.7%) PIO sites used.
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69 + 4(JTAG) out of 115 (63.5%) bonded PIO sites used.
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Number of PIO comps: 69; differential: 0
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Number of Vref pins used: 0
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I/O Bank Usage Summary:
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+----------+----------------+------------+-----------+
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| I/O Bank | Usage | Bank Vccio | Bank Vref |
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+----------+----------------+------------+-----------+
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| 0 | 11 / 28 ( 39%) | 2.5V | - |
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| 1 | 13 / 29 ( 44%) | 2.5V | - |
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| 2 | 20 / 29 ( 68%) | 2.5V | - |
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| 3 | 8 / 9 ( 88%) | 2.5V | - |
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| 4 | 7 / 10 ( 70%) | 2.5V | - |
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| 5 | 10 / 10 (100%) | 2.5V | - |
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+----------+----------------+------------+-----------+
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Total placer CPU time: 6 secs
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Dumping design to file P6809_P6809.dir/5_1.ncd.
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-----------------------------------------------------------------
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INFO - par: ASE feature is off due to non timing-driven settings.
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-----------------------------------------------------------------
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Starting router resource preassignment
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Completed router resource preassignment. Real time: 9 secs
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Start NBR router at 07:47:09 07/06/14
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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in the earlier iterations. In each iteration, it tries to
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solve the conflicts while keeping the critical connections
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routed as short as possible. The routing process is said to
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be completed when no conflicts exist and all connections
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are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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worst slack and total negative slack may not be the same as
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that in TRCE report. You should always run TRCE to verify
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your design. Thanks.
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*****************************************************************
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Start NBR special constraint process at 07:47:09 07/06/14
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Start NBR section for initial routing
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Level 4, iteration 1
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290(0.08%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secs
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Info: Initial congestion level at 75% usage is 0
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Info: Initial congestion area at 75% usage is 5 (0.50%)
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Start NBR section for normal routing
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Level 4, iteration 1
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125(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secs
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Level 4, iteration 2
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46(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 11 secs
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Level 4, iteration 3
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17(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 4
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11(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 5
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8(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 6
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4(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 7
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2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 8
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2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 9
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1(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 10
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2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Level 4, iteration 11
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Start NBR section for re-routing
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 12 secs
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Start NBR section for post-routing
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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Number of unrouted connections : 0 (0.00%)
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Number of connections with timing violations : 0 (0.00%)
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Estimated worst slack :
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Timing score : 0
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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Total CPU time 12 secs
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Total REAL time: 12 secs
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Completely routed.
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End of route. 9723 routed (100.00%); 0 unrouted.
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Checking DRC ...
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No errors found.
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Hold time timing score: 0, hold timing errors: 0
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Timing score: 0
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Dumping design to file P6809_P6809.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Number of errors = 0
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Total CPU time to completion: 13 secs
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Total REAL time to completion: 14 secs
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par done!
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2014 Lattice Semiconductor Corporation, All rights reserved.
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