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ale500 |
#Build: Synplify Pro I-2013.09L , Build 064R, Nov 15 2013
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#install: C:\lscc\diamond\3.1_x64\synpbase
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#OS: Windows 7 6.1
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#Hostname: ALE-PC
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#Implementation: P6809
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$ Start of Compile
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#Sun Jul 06 07:46:25 2014
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Synopsys Verilog Compiler, version comp201309rc, Build 136R, built Nov 18 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2013 Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\pmi_def.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\umr_capim.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_objects.v"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\scemi_pipes.svh"
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@I::"C:\lscc\diamond\3.1_x64\synpbase\lib\vlog\hypermods.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v"
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@I:"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\defs.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v"
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@I::"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v"
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Verilog syntax check successful!
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File C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v changed - recompiling
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Selecting top level module CC3_top
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":604:7:604:12|Synthesizing module mul8x8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":66:7:66:12|Synthesizing module logic8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":89:7:89:12|Synthesizing module arith8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":162:7:162:12|Synthesizing module shift8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":202:7:202:10|Synthesizing module alu8
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":323:0:323:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:12:239:13|No assignment to n8
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@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":239:20:239:21|No assignment to z8
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":133:7:133:13|Synthesizing module arith16
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":329:7:329:11|Synthesizing module alu16
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":412:23:412:29|No assignment to wire arith_h
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@W: CL169 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Pruning register regq16[15:0]
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":15:7:15:9|Synthesizing module alu
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":191:7:191:13|Synthesizing module calc_ea
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":155:7:155:15|Synthesizing module decode_op
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":286:7:286:15|Synthesizing module decode_ea
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":312:7:312:16|Synthesizing module decode_alu
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":385:7:385:20|Synthesizing module test_condition
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
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@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":456:6:456:13|Ignoring system task $display
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@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":1125:0:1125:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":70:11:70:23|No assignment to wire alu8_o_result
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@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":71:11:71:20|No assignment to wire alu8_o_CCR
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 100 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 101 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_indirect_loaded -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 102 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 103 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 104 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 105 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 106 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 107 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 108 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 109 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 110 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 111 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 112 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 113 |
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@A: CL282 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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| 114 |
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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| 115 |
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[1] is always 0, optimizing ...
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| 116 |
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@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Register bit next_mem_state[2] is always 0, optimizing ...
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| 117 |
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@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
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| 118 |
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| 119 |
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@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bit 1 of k_mem_dest[1:0]
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| 120 |
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| 121 |
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1120:7:1120:9|Synthesizing module VHI
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| 122 |
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| 123 |
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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| 124 |
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| 125 |
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@N: CG364 :"C:\lscc\diamond\3.1_x64\synpbase\lib\lucent\machxo2.v":1124:7:1124:9|Synthesizing module VLO
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| 126 |
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| 127 |
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":8:7:8:12|Synthesizing module bios2k
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| 128 |
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| 129 |
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@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
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| 131 |
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\fontrom.v":8:7:8:13|Synthesizing module fontrom
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| 132 |
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| 133 |
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@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":8:7:8:15|Synthesizing module textmem4k
|
| 134 |
|
|
|
| 135 |
|
|
@W: CL168 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
|
| 136 |
|
|
|
| 137 |
|
|
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":2:7:2:13|Synthesizing module vgatext
|
| 138 |
|
|
|
| 139 |
|
|
@N: CG793 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":133:4:133:11|Ignoring system task $display
|
| 140 |
|
|
@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":167:6:167:11|System task $write is not supported yet
|
| 141 |
|
|
@N: CG512 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":174:6:174:11|System task $write is not supported yet
|
| 142 |
|
|
@W: CG532 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
|
| 143 |
|
|
@W: CG781 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
|
| 144 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
|
| 145 |
|
|
|
| 146 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
|
| 147 |
|
|
|
| 148 |
|
|
@W: CL271 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
|
| 149 |
|
|
|
| 150 |
|
|
@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element redr.
|
| 151 |
|
|
@N: CL177 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Sharing sequential element greenr.
|
| 152 |
|
|
@N: CG364 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":10:7:10:13|Synthesizing module CC3_top
|
| 153 |
|
|
|
| 154 |
|
|
@W: CG133 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":37:14:37:21|No assignment to clk_div2
|
| 155 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o
|
| 156 |
|
|
|
| 157 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in
|
| 158 |
|
|
|
| 159 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
|
| 160 |
|
|
|
| 161 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:23:44:29|No assignment to wire cpu1_we
|
| 162 |
|
|
|
| 163 |
|
|
@W: CG360 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe
|
| 164 |
|
|
|
| 165 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 166 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 167 |
|
|
@W: CL156 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
|
| 168 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
|
| 169 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
|
| 170 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
|
| 171 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
|
| 172 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
|
| 173 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
|
| 174 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
|
| 175 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
|
| 176 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
|
| 177 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
|
| 178 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
|
| 179 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
|
| 180 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
|
| 181 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
|
| 182 |
|
|
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":325:0:325:5|Pruning register bits 5 to 3 of next_push_state[5:0]
|
| 183 |
|
|
|
| 184 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
|
| 185 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":389:18:389:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
| 186 |
|
|
|
| 187 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":314:18:314:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
|
| 188 |
|
|
|
| 189 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\decoders.v":287:18:287:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
|
| 190 |
|
|
|
| 191 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":333:18:333:20|Input port bits 7 to 4 of CCR[7:0] are unused
|
| 192 |
|
|
|
| 193 |
|
|
@W: CL246 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":206:18:206:20|Input port bits 3 to 2 of CCR[7:0] are unused
|
| 194 |
|
|
|
| 195 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":203:12:203:17|Input clk_in is unused
|
| 196 |
|
|
@W: CL159 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":164:18:164:21|Input b_in is unused
|
| 197 |
|
|
@W: CL279 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
|
| 198 |
|
|
|
| 199 |
|
|
@W: CL189 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
|
| 200 |
|
|
@W: CL260 :"C:\02_Elektronik\020_V6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
|
| 201 |
|
|
|
| 202 |
|
|
@END
|
| 203 |
|
|
|
| 204 |
|
|
At c_ver Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 87MB peak: 99MB)
|
| 205 |
|
|
|
| 206 |
|
|
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
|
| 207 |
|
|
# Sun Jul 06 07:46:27 2014
|
| 208 |
|
|
|
| 209 |
|
|
###########################################################]
|
| 210 |
|
|
Premap Report
|
| 211 |
|
|
|
| 212 |
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 800R, Built Nov 18 2013 10:58:25
|
| 213 |
|
|
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
| 214 |
|
|
Product Version I-2013.09L
|
| 215 |
|
|
|
| 216 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
| 217 |
|
|
|
| 218 |
|
|
@L: C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rpt
|
| 219 |
|
|
Printing clock summary report in "C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809_scck.rpt" file
|
| 220 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 221 |
|
|
@N: MF666 |Clock conversion enabled
|
| 222 |
|
|
|
| 223 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
|
| 224 |
|
|
|
| 225 |
|
|
|
| 226 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 102MB peak: 104MB)
|
| 227 |
|
|
|
| 228 |
|
|
|
| 229 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 117MB)
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 117MB peak: 119MB)
|
| 233 |
|
|
|
| 234 |
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
| 235 |
|
|
|
| 236 |
|
|
|
| 237 |
|
|
Clock Summary
|
| 238 |
|
|
**************
|
| 239 |
|
|
|
| 240 |
|
|
Start Requested Requested Clock Clock
|
| 241 |
|
|
Clock Frequency Period Type Group
|
| 242 |
|
|
--------------------------------------------------------------------------------------------------------------------
|
| 243 |
|
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
| 244 |
|
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
| 245 |
|
|
CC3_top|div_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
| 246 |
|
|
====================================================================================================================
|
| 247 |
|
|
|
| 248 |
|
|
@W: MT529 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
| 249 |
|
|
|
| 250 |
|
|
Pre-mapping successful!
|
| 251 |
|
|
|
| 252 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 82MB peak: 146MB)
|
| 253 |
|
|
|
| 254 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 255 |
|
|
# Sun Jul 06 07:46:29 2014
|
| 256 |
|
|
|
| 257 |
|
|
###########################################################]
|
| 258 |
|
|
Map & Optimize Report
|
| 259 |
|
|
|
| 260 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 800R, Built Nov 18 2013 10:58:25
|
| 261 |
|
|
Copyright (C) 1994-2013, Synopsys, Inc. This software and the associated documentation are proprietary to Synopsys, Inc. This software may only be used in accordance with the terms and conditions of a written license agreement with Synopsys, Inc. All other use or distribution of the software is strictly prohibited.
|
| 262 |
|
|
Product Version I-2013.09L
|
| 263 |
|
|
|
| 264 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 99MB)
|
| 265 |
|
|
|
| 266 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 267 |
|
|
@N: MF666 |Clock conversion enabled
|
| 268 |
|
|
|
| 269 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 98MB peak: 100MB)
|
| 270 |
|
|
|
| 271 |
|
|
|
| 272 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| 273 |
|
|
|
| 274 |
|
|
|
| 275 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 114MB)
|
| 276 |
|
|
|
| 277 |
|
|
|
| 278 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 114MB peak: 116MB)
|
| 279 |
|
|
|
| 280 |
|
|
|
| 281 |
|
|
|
| 282 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
| 283 |
|
|
|
| 284 |
|
|
|
| 285 |
|
|
Available hyper_sources - for debug and ip models
|
| 286 |
|
|
None Found
|
| 287 |
|
|
|
| 288 |
|
|
|
| 289 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 144MB peak: 146MB)
|
| 290 |
|
|
|
| 291 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 292 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 293 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 294 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
|
| 295 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
|
| 296 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
|
| 297 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
|
| 298 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
|
| 299 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
|
| 300 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
|
| 301 |
|
|
@N:"c:\02_elektronik\020_v6809\trunk\syn\lattice\vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
|
| 302 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 303 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 304 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
| 305 |
|
|
|
| 306 |
|
|
Finished factoring (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 168MB peak: 168MB)
|
| 307 |
|
|
|
| 308 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 309 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 310 |
|
|
@N: BN362 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":325:0:325:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
| 311 |
|
|
|
| 312 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 164MB peak: 170MB)
|
| 313 |
|
|
|
| 314 |
|
|
|
| 315 |
|
|
|
| 316 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:03s; CPU Time elapsed 0h:00m:03s; Memory used current: 163MB peak: 177MB)
|
| 317 |
|
|
|
| 318 |
|
|
@N: FA113 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":616:12:617:75|Pipelining module pipe0_1[11:0]
|
| 319 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe0[11:0] pushed in.
|
| 320 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":614:0:614:5|Register pipe1[15:0] pushed in.
|
| 321 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rop_in[4:0] pushed in.
|
| 322 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register ra_in[15:0] pushed in.
|
| 323 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":518:0:518:5|Register reg_n_in pushed in.
|
| 324 |
|
|
@N: MF169 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":39:0:39:5|Register rb_in[15:0] pushed in.
|
| 325 |
|
|
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
|
| 326 |
|
|
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":145:35:145:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_i_m2[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
|
| 327 |
|
|
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\alu16.v":146:35:146:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2_i_m2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
|
| 328 |
|
|
@N: FX404 :"c:\02_elektronik\020_v6809\trunk\syn\lattice\..\..\rtl\verilog\mc6809_cpu.v":288:2:288:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.k_new_pc_2[15:0] from cpu0.un1_regs_o_pc[15:0]
|
| 329 |
|
|
|
| 330 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)
|
| 331 |
|
|
|
| 332 |
|
|
|
| 333 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 165MB peak: 177MB)
|
| 334 |
|
|
|
| 335 |
|
|
|
| 336 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 164MB peak: 177MB)
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 164MB peak: 177MB)
|
| 340 |
|
|
|
| 341 |
|
|
|
| 342 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 242MB peak: 246MB)
|
| 343 |
|
|
|
| 344 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 345 |
|
|
------------------------------------------------------------
|
| 346 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 347 |
|
|
------------------------------------------------------------
|
| 348 |
|
|
------------------------------------------------------------
|
| 349 |
|
|
|
| 350 |
|
|
|
| 351 |
|
|
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 182MB peak: 246MB)
|
| 352 |
|
|
|
| 353 |
|
|
@N: FX164 |The option to pack flops in the IOB has not been specified
|
| 354 |
|
|
|
| 355 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 183MB peak: 246MB)
|
| 356 |
|
|
|
| 357 |
|
|
|
| 358 |
|
|
|
| 359 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
| 360 |
|
|
|
| 361 |
|
|
1 non-gated/non-generated clock tree(s) driving 505 clock pin(s) of sequential element(s)
|
| 362 |
|
|
|
| 363 |
|
|
301 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
| 364 |
|
|
|
| 365 |
|
|
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 366 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 367 |
|
|
---------------------------------------------------------------------------------------
|
| 368 |
|
|
@K:CKID0001 clk40_i port 505 cpu_clk
|
| 369 |
|
|
=======================================================================================
|
| 370 |
|
|
|
| 371 |
|
|
|
| 372 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 373 |
|
|
|
| 374 |
|
|
Writing Analyst data base C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\P6809_P6809.srm
|
| 375 |
|
|
|
| 376 |
|
|
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 185MB peak: 246MB)
|
| 377 |
|
|
|
| 378 |
|
|
Writing EDIF Netlist and constraint files
|
| 379 |
|
|
@W: MT558 |Unable to locate source for clock CC3_top|div_derived_clock. Clock will not be forward annotated
|
| 380 |
|
|
@W: MT558 |Unable to locate source for clock CC3_top|cpu_clk_derived_clock. Clock will not be forward annotated
|
| 381 |
|
|
I-2013.09L
|
| 382 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
| 383 |
|
|
|
| 384 |
|
|
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:17s; Memory used current: 189MB peak: 246MB)
|
| 385 |
|
|
|
| 386 |
|
|
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
|
| 387 |
|
|
|
| 388 |
|
|
|
| 389 |
|
|
|
| 390 |
|
|
##### START OF TIMING REPORT #####[
|
| 391 |
|
|
# Timing Report written on Sun Jul 06 07:46:48 2014
|
| 392 |
|
|
#
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
Top view: CC3_top
|
| 396 |
|
|
Requested Frequency: 1.0 MHz
|
| 397 |
|
|
Wire load mode: top
|
| 398 |
|
|
Paths requested: 5
|
| 399 |
|
|
Constraint File(s):
|
| 400 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
| 401 |
|
|
|
| 402 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
| 403 |
|
|
|
| 404 |
|
|
|
| 405 |
|
|
|
| 406 |
|
|
Performance Summary
|
| 407 |
|
|
*******************
|
| 408 |
|
|
|
| 409 |
|
|
|
| 410 |
|
|
Worst slack in design: 979.573
|
| 411 |
|
|
|
| 412 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
| 413 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 414 |
|
|
------------------------------------------------------------------------------------------------------------------------
|
| 415 |
|
|
CC3_top|clk40_i 1.0 MHz 49.0 MHz 1000.000 20.427 979.573 inferred Inferred_clkgroup_0
|
| 416 |
|
|
========================================================================================================================
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
Clock Relationships
|
| 423 |
|
|
*******************
|
| 424 |
|
|
|
| 425 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 426 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
| 427 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 428 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
| 429 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 979.573 | No paths - | No paths - | No paths -
|
| 430 |
|
|
==========================================================================================================================
|
| 431 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 432 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 433 |
|
|
|
| 434 |
|
|
|
| 435 |
|
|
|
| 436 |
|
|
Interface Information
|
| 437 |
|
|
*********************
|
| 438 |
|
|
|
| 439 |
|
|
No IO constraint found
|
| 440 |
|
|
|
| 441 |
|
|
|
| 442 |
|
|
|
| 443 |
|
|
====================================
|
| 444 |
|
|
Detailed Report for Clock: CC3_top|clk40_i
|
| 445 |
|
|
====================================
|
| 446 |
|
|
|
| 447 |
|
|
|
| 448 |
|
|
|
| 449 |
|
|
Starting Points with Worst Slack
|
| 450 |
|
|
********************************
|
| 451 |
|
|
|
| 452 |
|
|
Starting Arrival
|
| 453 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 454 |
|
|
Clock
|
| 455 |
|
|
------------------------------------------------------------------------------------------------------
|
| 456 |
|
|
cpu0.alu.rb_in[0] CC3_top|clk40_i FD1P3AX Q rb_in[0] 1.228 979.573
|
| 457 |
|
|
cpu0.alu.rb_in[1] CC3_top|clk40_i FD1P3AX Q rb_in[1] 1.228 979.716
|
| 458 |
|
|
cpu0.alu.rb_in[2] CC3_top|clk40_i FD1P3AX Q rb_in[2] 1.228 979.716
|
| 459 |
|
|
cpu0.k_opcode[6] CC3_top|clk40_i FD1P3AX Q k_opcode[6] 1.347 979.827
|
| 460 |
|
|
cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.339 979.836
|
| 461 |
|
|
cpu0.alu.rb_in[4] CC3_top|clk40_i FD1P3AX Q rb_in[4] 1.232 979.855
|
| 462 |
|
|
cpu0.alu.rb_in[3] CC3_top|clk40_i FD1P3AX Q rb_in[3] 1.228 979.859
|
| 463 |
|
|
cpu0.alu.rb_in_pipe_2 CC3_top|clk40_i FD1P3AX Q rb_in_pipe_2 1.268 979.883
|
| 464 |
|
|
cpu0.k_opcode[3] CC3_top|clk40_i FD1P3AX Q k_opcode[3] 1.369 979.909
|
| 465 |
|
|
cpu0.k_opcode[2] CC3_top|clk40_i FD1P3AX Q k_opcode[2] 1.368 979.911
|
| 466 |
|
|
======================================================================================================
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
Ending Points with Worst Slack
|
| 470 |
|
|
******************************
|
| 471 |
|
|
|
| 472 |
|
|
Starting Required
|
| 473 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 474 |
|
|
Clock
|
| 475 |
|
|
----------------------------------------------------------------------------------------------
|
| 476 |
|
|
cpu0.regs.SS[14] CC3_top|clk40_i FD1P3AX D SS_s[14] 999.894 979.573
|
| 477 |
|
|
cpu0.regs.SS[15] CC3_top|clk40_i FD1P3AX D SS_s[15] 999.894 979.573
|
| 478 |
|
|
cpu0.regs.SU[14] CC3_top|clk40_i FD1P3AX D SU_s[14] 999.894 979.573
|
| 479 |
|
|
cpu0.regs.SU[15] CC3_top|clk40_i FD1P3AX D SU_s[15] 999.894 979.573
|
| 480 |
|
|
cpu0.regs.SS[12] CC3_top|clk40_i FD1P3AX D SS_s[12] 999.894 979.716
|
| 481 |
|
|
cpu0.regs.SS[13] CC3_top|clk40_i FD1P3AX D SS_s[13] 999.894 979.716
|
| 482 |
|
|
cpu0.regs.SU[12] CC3_top|clk40_i FD1P3AX D SU_s[12] 999.894 979.716
|
| 483 |
|
|
cpu0.regs.SU[13] CC3_top|clk40_i FD1P3AX D SU_s[13] 999.894 979.716
|
| 484 |
|
|
cpu0.regs.SS[10] CC3_top|clk40_i FD1P3AX D SS_s[10] 999.894 979.859
|
| 485 |
|
|
cpu0.regs.SS[11] CC3_top|clk40_i FD1P3AX D SS_s[11] 999.894 979.859
|
| 486 |
|
|
==============================================================================================
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
|
| 490 |
|
|
Worst Path Information
|
| 491 |
|
|
***********************
|
| 492 |
|
|
|
| 493 |
|
|
|
| 494 |
|
|
Path information for path number 1:
|
| 495 |
|
|
Requested Period: 1000.000
|
| 496 |
|
|
- Setup time: 0.106
|
| 497 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 498 |
|
|
= Required time: 999.894
|
| 499 |
|
|
|
| 500 |
|
|
- Propagation time: 20.321
|
| 501 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 502 |
|
|
= Slack (critical) : 979.573
|
| 503 |
|
|
|
| 504 |
|
|
Number of logic level(s): 22
|
| 505 |
|
|
Starting point: cpu0.alu.rb_in[0] / Q
|
| 506 |
|
|
Ending point: cpu0.regs.SS[15] / D
|
| 507 |
|
|
The start point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 508 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
| 509 |
|
|
|
| 510 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 511 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 512 |
|
|
----------------------------------------------------------------------------------------------------------------
|
| 513 |
|
|
cpu0.alu.rb_in[0] FD1P3AX Q Out 1.228 1.228 -
|
| 514 |
|
|
rb_in[0] Net - - - - 9
|
| 515 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV A In 0.000 1.228 -
|
| 516 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO INV Z Out 0.568 1.796 -
|
| 517 |
|
|
rb_in_i[0] Net - - - - 1
|
| 518 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D A1 In 0.000 1.796 -
|
| 519 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_0_0 CCU2D COUT Out 1.545 3.340 -
|
| 520 |
|
|
un8_q_out_cry_0 Net - - - - 1
|
| 521 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D CIN In 0.000 3.340 -
|
| 522 |
|
|
cpu0.alu.alu16.a16.un8_q_out_cry_1_0 CCU2D S1 Out 1.549 4.889 -
|
| 523 |
|
|
un8_q_out[2] Net - - - - 1
|
| 524 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 A In 0.000 4.889 -
|
| 525 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 5.906 -
|
| 526 |
|
|
q_out_2_i_m2_cry_1_0_RNO_0 Net - - - - 1
|
| 527 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D C1 In 0.000 5.906 -
|
| 528 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_1_0 CCU2D COUT Out 1.545 7.451 -
|
| 529 |
|
|
q_out_2_i_m2_cry_2 Net - - - - 1
|
| 530 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D CIN In 0.000 7.451 -
|
| 531 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_3_0 CCU2D COUT Out 0.143 7.593 -
|
| 532 |
|
|
q_out_2_i_m2_cry_4 Net - - - - 1
|
| 533 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D CIN In 0.000 7.593 -
|
| 534 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_5_0 CCU2D COUT Out 0.143 7.736 -
|
| 535 |
|
|
q_out_2_i_m2_cry_6 Net - - - - 1
|
| 536 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D CIN In 0.000 7.736 -
|
| 537 |
|
|
cpu0.alu.alu16.a16.q_out_2_i_m2_cry_7_0 CCU2D S0 Out 1.549 9.285 -
|
| 538 |
|
|
N_186 Net - - - - 1
|
| 539 |
|
|
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 B In 0.000 9.285 -
|
| 540 |
|
|
cpu0.alu.alu16.a16.q_out_3[7] ORCALUT4 Z Out 1.153 10.438 -
|
| 541 |
|
|
arith_q[7] Net - - - - 3
|
| 542 |
|
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 A In 0.000 10.438 -
|
| 543 |
|
|
cpu0.alu.alu16.q_out_1[7] ORCALUT4 Z Out 1.017 11.455 -
|
| 544 |
|
|
N_63 Net - - - - 1
|
| 545 |
|
|
cpu0.alu.alu16.q_out[7] PFUMX ALUT In 0.000 11.455 -
|
| 546 |
|
|
cpu0.alu.alu16.q_out[7] PFUMX Z Out 0.286 11.741 -
|
| 547 |
|
|
q16_out[7] Net - - - - 2
|
| 548 |
|
|
cpu0.alu.q_out[7] ORCALUT4 B In 0.000 11.741 -
|
| 549 |
|
|
cpu0.alu.q_out[7] ORCALUT4 Z Out 0.449 12.190 -
|
| 550 |
|
|
alu_o_result[7] Net - - - - 1
|
| 551 |
|
|
cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX ALUT In 0.000 12.190 -
|
| 552 |
|
|
cpu0.alu.alu8.s8.datamux_o_dest[7] PFUMX Z Out 0.286 12.476 -
|
| 553 |
|
|
datamux_o_dest[7] Net - - - - 2
|
| 554 |
|
|
cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 B In 0.000 12.476 -
|
| 555 |
|
|
cpu0.regs.path_left_data_RNIVJGV[7] ORCALUT4 Z Out 1.273 13.749 -
|
| 556 |
|
|
left_1[7] Net - - - - 9
|
| 557 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 B In 0.000 13.749 -
|
| 558 |
|
|
cpu0.regs.SS_16_0[7] ORCALUT4 Z Out 1.017 14.766 -
|
| 559 |
|
|
N_252 Net - - - - 1
|
| 560 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 A In 0.000 14.766 -
|
| 561 |
|
|
cpu0.regs.SS_16[7] ORCALUT4 Z Out 1.017 15.782 -
|
| 562 |
|
|
SS_16[7] Net - - - - 1
|
| 563 |
|
|
cpu0.regs.SS_222_m3 ORCALUT4 B In 0.000 15.782 -
|
| 564 |
|
|
cpu0.regs.SS_222_m3 ORCALUT4 Z Out 1.017 16.799 -
|
| 565 |
|
|
SS_222_i1_mux Net - - - - 1
|
| 566 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D C1 In 0.000 16.799 -
|
| 567 |
|
|
cpu0.regs.SS_cry_0[6] CCU2D COUT Out 1.545 18.344 -
|
| 568 |
|
|
SS_cry[7] Net - - - - 1
|
| 569 |
|
|
cpu0.regs.SS_cry_0[8] CCU2D CIN In 0.000 18.344 -
|
| 570 |
|
|
cpu0.regs.SS_cry_0[8] CCU2D COUT Out 0.143 18.486 -
|
| 571 |
|
|
SS_cry[9] Net - - - - 1
|
| 572 |
|
|
cpu0.regs.SS_cry_0[10] CCU2D CIN In 0.000 18.486 -
|
| 573 |
|
|
cpu0.regs.SS_cry_0[10] CCU2D COUT Out 0.143 18.629 -
|
| 574 |
|
|
SS_cry[11] Net - - - - 1
|
| 575 |
|
|
cpu0.regs.SS_cry_0[12] CCU2D CIN In 0.000 18.629 -
|
| 576 |
|
|
cpu0.regs.SS_cry_0[12] CCU2D COUT Out 0.143 18.772 -
|
| 577 |
|
|
SS_cry[13] Net - - - - 1
|
| 578 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D CIN In 0.000 18.772 -
|
| 579 |
|
|
cpu0.regs.SS_cry_0[14] CCU2D S1 Out 1.549 20.321 -
|
| 580 |
|
|
SS_s[15] Net - - - - 1
|
| 581 |
|
|
cpu0.regs.SS[15] FD1P3AX D In 0.000 20.321 -
|
| 582 |
|
|
================================================================================================================
|
| 583 |
|
|
|
| 584 |
|
|
|
| 585 |
|
|
|
| 586 |
|
|
##### END OF TIMING REPORT #####]
|
| 587 |
|
|
|
| 588 |
|
|
---------------------------------------
|
| 589 |
|
|
Resource Usage Report
|
| 590 |
|
|
Part: lcmxo2_7000he-4
|
| 591 |
|
|
|
| 592 |
|
|
Register bits: 489 of 6864 (7%)
|
| 593 |
|
|
PIC Latch: 0
|
| 594 |
|
|
I/O cells: 69
|
| 595 |
|
|
Block Rams : 10 of 26 (38%)
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
Details:
|
| 599 |
|
|
BB: 8
|
| 600 |
|
|
CCU2D: 183
|
| 601 |
|
|
DP8KC: 10
|
| 602 |
|
|
FD1P3AX: 438
|
| 603 |
|
|
FD1P3DX: 6
|
| 604 |
|
|
FD1S3AX: 33
|
| 605 |
|
|
FD1S3IX: 2
|
| 606 |
|
|
GSR: 1
|
| 607 |
|
|
IB: 1
|
| 608 |
|
|
INV: 12
|
| 609 |
|
|
L6MUX21: 30
|
| 610 |
|
|
OB: 60
|
| 611 |
|
|
OFS1P3DX: 9
|
| 612 |
|
|
OFS1P3IX: 1
|
| 613 |
|
|
ORCALUT4: 2078
|
| 614 |
|
|
PFUMX: 239
|
| 615 |
|
|
PUR: 1
|
| 616 |
|
|
VHI: 14
|
| 617 |
|
|
VLO: 20
|
| 618 |
|
|
false: 1
|
| 619 |
|
|
true: 7
|
| 620 |
|
|
Mapper successful!
|
| 621 |
|
|
|
| 622 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 58MB peak: 246MB)
|
| 623 |
|
|
|
| 624 |
|
|
Process took 0h:00m:18s realtime, 0h:00m:17s cputime
|
| 625 |
|
|
# Sun Jul 06 07:46:48 2014
|
| 626 |
|
|
|
| 627 |
|
|
###########################################################]
|
