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ale500 |
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Loading design for application trce from file P6809_P6809_map.ncd.
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| 3 |
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Design name: CC3_top
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| 4 |
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NCD version: 3.2
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Vendor: LATTICE
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Device: LCMXO2-7000HE
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Package: TQFP144
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Performance: 4
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Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
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Package Status: Final Version 1.36
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Performance Hardware Data Status: Final) Version 23.4
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
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ale500 |
Thu Feb 6 15:35:22 2014
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| 18 |
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
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Design file: P6809_P6809_map.ncd
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| 28 |
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Preference file: P6809_P6809.prf
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| 29 |
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Device,speed: LCMXO2-7000HE,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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ale500 |
4096 items scored, 198 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 0.564ns
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ale500 |
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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| 48 |
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Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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| 51 |
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ale500 |
Delay: 25.398ns (42.7% logic, 57.3% route), 21 logic levels.
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ale500 |
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Constraint Details:
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| 55 |
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ale500 |
25.398ns physical path delay cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55 exceeds
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ale500 |
25.000ns delay constraint less
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ale500 |
0.166ns DIN_SET requirement (totaling 24.834ns) by 0.564ns
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| 59 |
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ale500 |
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| 60 |
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Physical Path Details:
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| 61 |
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ale500 |
Data path cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55:
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Name Fanout Delay (ns) Site Resource
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ale500 |
REG_DEL --- 0.452 *SLICE_215.CLK to */SLICE_215.Q0 cpu0/alu/SLICE_215 (from cpu_clkgen)
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| 66 |
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ROUTE 24 e 1.234 */SLICE_215.Q0 to */SLICE_199.A1 cpu0/alu/rb_in[0]
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| 67 |
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CTOF_DEL --- 0.495 */SLICE_199.A1 to */SLICE_199.F1 cpu0/alu/alu16/SLICE_199
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| 68 |
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ROUTE 1 e 1.234 */SLICE_199.F1 to *6/SLICE_99.A1 cpu0/alu/alu16/a16/rb_in_i[0]
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| 69 |
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C1TOFCO_DE --- 0.889 *6/SLICE_99.A1 to */SLICE_99.FCO cpu0/alu/alu16/a16/SLICE_99
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| 70 |
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ROUTE 1 e 0.001 */SLICE_99.FCO to */SLICE_98.FCI cpu0/alu/alu16/a16/un8_q_out_cry_0
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| 71 |
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FCITOF0_DE --- 0.585 */SLICE_98.FCI to *6/SLICE_98.F0 cpu0/alu/alu16/a16/SLICE_98
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| 72 |
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ROUTE 1 e 1.234 *6/SLICE_98.F0 to *SLICE_1214.A0 cpu0/alu/alu16/a16/un8_q_out[1]
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| 73 |
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CTOF_DEL --- 0.495 *SLICE_1214.A0 to *SLICE_1214.F0 cpu0/alu/SLICE_1214
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| 74 |
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ROUTE 1 e 1.234 *SLICE_1214.F0 to */SLICE_116.C0 cpu0/alu/alu16/a16/q_out_2_cry_1_0_RNO
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| 75 |
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C0TOFCO_DE --- 1.023 */SLICE_116.C0 to *SLICE_116.FCO cpu0/alu/alu16/a16/SLICE_116
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| 76 |
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ROUTE 1 e 0.001 *SLICE_116.FCO to *SLICE_115.FCI cpu0/alu/alu16/a16/q_out_2_cry_2
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| 77 |
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FCITOFCO_D --- 0.162 *SLICE_115.FCI to *SLICE_115.FCO cpu0/alu/alu16/a16/SLICE_115
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| 78 |
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ROUTE 1 e 0.001 *SLICE_115.FCO to *SLICE_114.FCI cpu0/alu/alu16/a16/q_out_2_cry_4
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| 79 |
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FCITOFCO_D --- 0.162 *SLICE_114.FCI to *SLICE_114.FCO cpu0/alu/alu16/a16/SLICE_114
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| 80 |
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ROUTE 1 e 0.001 *SLICE_114.FCO to *SLICE_113.FCI cpu0/alu/alu16/a16/q_out_2_cry_6
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| 81 |
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FCITOFCO_D --- 0.162 *SLICE_113.FCI to *SLICE_113.FCO cpu0/alu/alu16/a16/SLICE_113
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| 82 |
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ROUTE 1 e 0.001 *SLICE_113.FCO to *SLICE_112.FCI cpu0/alu/alu16/a16/q_out_2_cry_8
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| 83 |
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FCITOFCO_D --- 0.162 *SLICE_112.FCI to *SLICE_112.FCO cpu0/alu/alu16/a16/SLICE_112
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| 84 |
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ROUTE 1 e 0.001 *SLICE_112.FCO to *SLICE_111.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
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| 85 |
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FCITOF1_DE --- 0.643 *SLICE_111.FCI to */SLICE_111.F1 cpu0/alu/alu16/a16/SLICE_111
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| 86 |
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ROUTE 1 e 1.234 */SLICE_111.F1 to *SLICE_1048.B0 cpu0/alu/alu16/a16/N_2375
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| 87 |
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CTOF_DEL --- 0.495 *SLICE_1048.B0 to *SLICE_1048.F0 cpu0/alu/alu16/SLICE_1048
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| 88 |
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ROUTE 1 e 0.480 *SLICE_1048.F0 to *SLICE_1048.A1 cpu0/alu/alu16/arith_q[12]
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| 89 |
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CTOF_DEL --- 0.495 *SLICE_1048.A1 to *SLICE_1048.F1 cpu0/alu/alu16/SLICE_1048
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| 90 |
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ROUTE 1 e 1.234 *SLICE_1048.F1 to *SLICE_1066.A1 cpu0/alu/alu16/N_2342
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| 91 |
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CTOF_DEL --- 0.495 *SLICE_1066.A1 to *SLICE_1066.F1 cpu0/alu/alu16/SLICE_1066
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| 92 |
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ROUTE 2 e 1.234 *SLICE_1066.F1 to *SLICE_1082.B0 cpu0/alu/q16_out[12]
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| 93 |
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CTOF_DEL --- 0.495 *SLICE_1082.B0 to *SLICE_1082.F0 cpu0/alu/SLICE_1082
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| 94 |
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ROUTE 2 e 1.234 *SLICE_1082.F0 to */SLICE_363.A0 cpu0/datamux_o_dest[12]
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| 95 |
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CTOF_DEL --- 0.495 */SLICE_363.A0 to */SLICE_363.F0 cpu0/regs/SLICE_363
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| 96 |
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ROUTE 6 e 1.234 */SLICE_363.F0 to *SLICE_1193.B0 cpu0/regs/left_1[12]
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| 97 |
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CTOF_DEL --- 0.495 *SLICE_1193.B0 to *SLICE_1193.F0 cpu0/regs/SLICE_1193
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| 98 |
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ROUTE 1 e 1.234 *SLICE_1193.F0 to */SLICE_951.A1 cpu0/regs/N_291
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| 99 |
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CTOF_DEL --- 0.495 */SLICE_951.A1 to */SLICE_951.F1 cpu0/regs/SLICE_951
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| 100 |
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ROUTE 1 e 0.480 */SLICE_951.F1 to */SLICE_951.B0 cpu0/regs/SU_16[12]
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| 101 |
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CTOF_DEL --- 0.495 */SLICE_951.B0 to */SLICE_951.F0 cpu0/regs/SLICE_951
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| 102 |
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ROUTE 1 e 1.234 */SLICE_951.F0 to *s/SLICE_56.C0 cpu0/regs/SU_219_i1_mux
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| 103 |
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C0TOFCO_DE --- 1.023 *s/SLICE_56.C0 to */SLICE_56.FCO cpu0/regs/SLICE_56
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| 104 |
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ROUTE 1 e 0.001 */SLICE_56.FCO to */SLICE_55.FCI cpu0/regs/SU_cry[13]
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| 105 |
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FCITOF1_DE --- 0.643 */SLICE_55.FCI to *s/SLICE_55.F1 cpu0/regs/SLICE_55
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| 106 |
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ROUTE 1 e 0.001 *s/SLICE_55.F1 to */SLICE_55.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
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| 107 |
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ale500 |
--------
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| 108 |
10 |
ale500 |
25.398 (42.7% logic, 57.3% route), 21 logic levels.
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| 109 |
9 |
ale500 |
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| 110 |
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ale500 |
Warning: 39.118MHz is the maximum frequency for this preference.
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| 111 |
9 |
ale500 |
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| 112 |
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Report Summary
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| 113 |
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--------------
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| 114 |
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----------------------------------------------------------------------------
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| 115 |
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Preference | Constraint| Actual|Levels
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| 116 |
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----------------------------------------------------------------------------
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| 117 |
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| 118 |
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FREQUENCY NET "cpu_clkgen" 40.000000 | | |
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| 119 |
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ale500 |
MHz ; | 40.000 MHz| 39.118 MHz| 21 *
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| 120 |
9 |
ale500 |
| | |
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| 121 |
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----------------------------------------------------------------------------
|
| 122 |
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| 123 |
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| 124 |
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1 preference(marked by "*" above) not met.
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| 125 |
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| 126 |
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----------------------------------------------------------------------------
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| 127 |
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Critical Nets | Loads| Errors| % of total
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| 128 |
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----------------------------------------------------------------------------
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| 129 |
10 |
ale500 |
cpu0/alu/alu16/N_2342 | 1| 178| 89.90%
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| 130 |
9 |
ale500 |
| | |
|
| 131 |
10 |
ale500 |
cpu0/alu/q16_out[12] | 2| 178| 89.90%
|
| 132 |
9 |
ale500 |
| | |
|
| 133 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_10 | 1| 178| 89.90%
|
| 134 |
9 |
ale500 |
| | |
|
| 135 |
10 |
ale500 |
cpu0/alu/alu16/arith_q[12] | 1| 178| 89.90%
|
| 136 |
9 |
ale500 |
| | |
|
| 137 |
10 |
ale500 |
cpu0/alu/alu16/a16/N_2375 | 1| 178| 89.90%
|
| 138 |
9 |
ale500 |
| | |
|
| 139 |
10 |
ale500 |
cpu0/datamux_o_dest[12] | 2| 178| 89.90%
|
| 140 |
9 |
ale500 |
| | |
|
| 141 |
10 |
ale500 |
cpu0/regs/left_1[12] | 6| 178| 89.90%
|
| 142 |
9 |
ale500 |
| | |
|
| 143 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_8 | 1| 124| 62.63%
|
| 144 |
9 |
ale500 |
| | |
|
| 145 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out_cry_4 | 1| 122| 61.62%
|
| 146 |
9 |
ale500 |
| | |
|
| 147 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out_cry_2 | 1| 106| 53.54%
|
| 148 |
9 |
ale500 |
| | |
|
| 149 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out_cry_6 | 1| 104| 52.53%
|
| 150 |
9 |
ale500 |
| | |
|
| 151 |
10 |
ale500 |
cpu0/regs/SS_cry[13] | 1| 99| 50.00%
|
| 152 |
9 |
ale500 |
| | |
|
| 153 |
10 |
ale500 |
cpu0/regs/SU_cry[13] | 1| 99| 50.00%
|
| 154 |
9 |
ale500 |
| | |
|
| 155 |
10 |
ale500 |
cpu0/regs/N_255 | 1| 89| 44.95%
|
| 156 |
9 |
ale500 |
| | |
|
| 157 |
10 |
ale500 |
cpu0/regs/N_291 | 1| 89| 44.95%
|
| 158 |
9 |
ale500 |
| | |
|
| 159 |
10 |
ale500 |
cpu0/regs/SS_235_i1_mux | 1| 89| 44.95%
|
| 160 |
9 |
ale500 |
| | |
|
| 161 |
10 |
ale500 |
cpu0/regs/SS_16[12] | 1| 89| 44.95%
|
| 162 |
9 |
ale500 |
| | |
|
| 163 |
10 |
ale500 |
cpu0/regs/SU_219_i1_mux | 1| 89| 44.95%
|
| 164 |
9 |
ale500 |
| | |
|
| 165 |
10 |
ale500 |
cpu0/regs/SU_16[12] | 1| 89| 44.95%
|
| 166 |
9 |
ale500 |
| | |
|
| 167 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_6 | 1| 78| 39.39%
|
| 168 |
9 |
ale500 |
| | |
|
| 169 |
10 |
ale500 |
cpu0/alu/alu16/a16/rb_in_i[0] | 1| 58| 29.29%
|
| 170 |
9 |
ale500 |
| | |
|
| 171 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out_cry_0 | 1| 58| 29.29%
|
| 172 |
9 |
ale500 |
| | |
|
| 173 |
10 |
ale500 |
cpu0/alu/rb_in[0] | 24| 58| 29.29%
|
| 174 |
9 |
ale500 |
| | |
|
| 175 |
10 |
ale500 |
cpu0/regs/SS_s[15] | 1| 55| 27.78%
|
| 176 |
9 |
ale500 |
| | |
|
| 177 |
10 |
ale500 |
cpu0/regs/SU_s[15] | 1| 55| 27.78%
|
| 178 |
9 |
ale500 |
| | |
|
| 179 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out_cry_8 | 1| 54| 27.27%
|
| 180 |
9 |
ale500 |
| | |
|
| 181 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_4 | 1| 46| 23.23%
|
| 182 |
9 |
ale500 |
| | |
|
| 183 |
10 |
ale500 |
cpu0/regs/SS_s[14] | 1| 44| 22.22%
|
| 184 |
9 |
ale500 |
| | |
|
| 185 |
10 |
ale500 |
cpu0/regs/SU_s[14] | 1| 44| 22.22%
|
| 186 |
9 |
ale500 |
| | |
|
| 187 |
10 |
ale500 |
cpu0/alu/alu16/a16/rb_in_i[1] | 1| 34| 17.17%
|
| 188 |
9 |
ale500 |
| | |
|
| 189 |
10 |
ale500 |
cpu0/alu/rb_in[1] | 24| 34| 17.17%
|
| 190 |
9 |
ale500 |
| | |
|
| 191 |
10 |
ale500 |
cpu0/alu/alu16/a16/rb_in_i[2] | 1| 32| 16.16%
|
| 192 |
9 |
ale500 |
| | |
|
| 193 |
10 |
ale500 |
cpu0/alu/rb_in[2] | 21| 32| 16.16%
|
| 194 |
9 |
ale500 |
| | |
|
| 195 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO | 1| 30| 15.15%
|
| 196 |
9 |
ale500 |
| | |
|
| 197 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[9] | 1| 30| 15.15%
|
| 198 |
9 |
ale500 |
| | |
|
| 199 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO | 1| 28| 14.14%
|
| 200 |
9 |
ale500 |
| | |
|
| 201 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[7] | 1| 28| 14.14%
|
| 202 |
9 |
ale500 |
| | |
|
| 203 |
10 |
ale500 |
cpu0/alu/alu16/a16/rb_in_i[4] | 1| 24| 12.12%
|
| 204 |
9 |
ale500 |
| | |
|
| 205 |
10 |
ale500 |
cpu0/alu/alu16/a16/rb_in_i[3] | 1| 24| 12.12%
|
| 206 |
9 |
ale500 |
| | |
|
| 207 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0| 1| 24| 12.12%
|
| 208 |
9 |
ale500 |
| | |
|
| 209 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[10] | 1| 24| 12.12%
|
| 210 |
9 |
ale500 |
| | |
|
| 211 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_0| 1| 24| 12.12%
|
| 212 |
9 |
ale500 |
| | |
|
| 213 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[8] | 1| 24| 12.12%
|
| 214 |
9 |
ale500 |
| | |
|
| 215 |
10 |
ale500 |
cpu0/alu/rb_in[4] | 21| 24| 12.12%
|
| 216 |
9 |
ale500 |
| | |
|
| 217 |
10 |
ale500 |
cpu0/alu/rb_in[3] | 22| 24| 12.12%
|
| 218 |
9 |
ale500 |
| | |
|
| 219 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO | 1| 22| 11.11%
|
| 220 |
9 |
ale500 |
| | |
|
| 221 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[5] | 1| 22| 11.11%
|
| 222 |
9 |
ale500 |
| | |
|
| 223 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO_0| 1| 20| 10.10%
|
| 224 |
9 |
ale500 |
| | |
|
| 225 |
10 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[6] | 1| 20| 10.10%
|
| 226 |
9 |
ale500 |
| | |
|
| 227 |
10 |
ale500 |
cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO | 1| 20| 10.10%
|
| 228 |
|
|
| | |
|
| 229 |
|
|
cpu0/alu/alu16/a16/un8_q_out[3] | 1| 20| 10.10%
|
| 230 |
|
|
| | |
|
| 231 |
9 |
ale500 |
----------------------------------------------------------------------------
|
| 232 |
|
|
|
| 233 |
|
|
|
| 234 |
|
|
Clock Domains Analysis
|
| 235 |
|
|
------------------------
|
| 236 |
|
|
|
| 237 |
|
|
Found 1 clocks:
|
| 238 |
|
|
|
| 239 |
10 |
ale500 |
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
| 240 |
9 |
ale500 |
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
| 241 |
|
|
|
| 242 |
|
|
|
| 243 |
|
|
Timing summary (Setup):
|
| 244 |
|
|
---------------
|
| 245 |
|
|
|
| 246 |
10 |
ale500 |
Timing errors: 198 Score: 60114
|
| 247 |
|
|
Cumulative negative slack: 60114
|
| 248 |
9 |
ale500 |
|
| 249 |
10 |
ale500 |
Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)
|
| 250 |
9 |
ale500 |
|
| 251 |
|
|
--------------------------------------------------------------------------------
|
| 252 |
|
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
| 253 |
10 |
ale500 |
Thu Feb 6 15:35:22 2014
|
| 254 |
9 |
ale500 |
|
| 255 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
| 256 |
|
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Copyright (c) 1995 AT&T Corp. All rights reserved.
|
| 257 |
|
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
| 258 |
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
| 259 |
|
|
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
| 260 |
|
|
|
| 261 |
|
|
Report Information
|
| 262 |
|
|
------------------
|
| 263 |
|
|
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
|
| 264 |
|
|
Design file: P6809_P6809_map.ncd
|
| 265 |
|
|
Preference file: P6809_P6809.prf
|
| 266 |
|
|
Device,speed: LCMXO2-7000HE,M
|
| 267 |
|
|
Report level: verbose report, limited to 1 item per preference
|
| 268 |
|
|
--------------------------------------------------------------------------------
|
| 269 |
|
|
|
| 270 |
|
|
BLOCK ASYNCPATHS
|
| 271 |
|
|
BLOCK RESETPATHS
|
| 272 |
|
|
--------------------------------------------------------------------------------
|
| 273 |
|
|
|
| 274 |
|
|
|
| 275 |
|
|
|
| 276 |
|
|
================================================================================
|
| 277 |
|
|
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
| 278 |
|
|
4096 items scored, 0 timing errors detected.
|
| 279 |
|
|
--------------------------------------------------------------------------------
|
| 280 |
|
|
|
| 281 |
|
|
|
| 282 |
10 |
ale500 |
Passed: The following path meets requirements by 0.386ns
|
| 283 |
9 |
ale500 |
|
| 284 |
|
|
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
| 285 |
|
|
|
| 286 |
10 |
ale500 |
Source: FF Q reset_cnt[0] (from cpu_clkgen +)
|
| 287 |
|
|
Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)
|
| 288 |
9 |
ale500 |
|
| 289 |
10 |
ale500 |
Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.
|
| 290 |
9 |
ale500 |
|
| 291 |
|
|
Constraint Details:
|
| 292 |
|
|
|
| 293 |
10 |
ale500 |
0.330ns physical path delay SLICE_444 to SLICE_444 meets
|
| 294 |
|
|
-0.056ns LSR_HLD and
|
| 295 |
|
|
0.000ns delay constraint requirement (totaling -0.056ns) by 0.386ns
|
| 296 |
9 |
ale500 |
|
| 297 |
|
|
Physical Path Details:
|
| 298 |
|
|
|
| 299 |
10 |
ale500 |
Data path SLICE_444 to SLICE_444:
|
| 300 |
9 |
ale500 |
|
| 301 |
|
|
Name Fanout Delay (ns) Site Resource
|
| 302 |
10 |
ale500 |
REG_DEL --- 0.131 SLICE_444.CLK to SLICE_444.Q0 SLICE_444 (from cpu_clkgen)
|
| 303 |
|
|
ROUTE 5 e 0.199 SLICE_444.Q0 to SLICE_444.LSR reset_cnt[0] (to cpu_clkgen)
|
| 304 |
9 |
ale500 |
--------
|
| 305 |
10 |
ale500 |
0.330 (39.7% logic, 60.3% route), 1 logic levels.
|
| 306 |
9 |
ale500 |
|
| 307 |
|
|
Report Summary
|
| 308 |
|
|
--------------
|
| 309 |
|
|
----------------------------------------------------------------------------
|
| 310 |
|
|
Preference(MIN Delays) | Constraint| Actual|Levels
|
| 311 |
|
|
----------------------------------------------------------------------------
|
| 312 |
|
|
| | |
|
| 313 |
|
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
| 314 |
10 |
ale500 |
MHz ; | -| -| 1
|
| 315 |
9 |
ale500 |
| | |
|
| 316 |
|
|
----------------------------------------------------------------------------
|
| 317 |
|
|
|
| 318 |
|
|
|
| 319 |
|
|
All preferences were met.
|
| 320 |
|
|
|
| 321 |
|
|
|
| 322 |
|
|
Clock Domains Analysis
|
| 323 |
|
|
------------------------
|
| 324 |
|
|
|
| 325 |
|
|
Found 1 clocks:
|
| 326 |
|
|
|
| 327 |
10 |
ale500 |
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
| 328 |
9 |
ale500 |
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
| 329 |
|
|
|
| 330 |
|
|
|
| 331 |
|
|
Timing summary (Hold):
|
| 332 |
|
|
---------------
|
| 333 |
|
|
|
| 334 |
|
|
Timing errors: 0 Score: 0
|
| 335 |
|
|
Cumulative negative slack: 0
|
| 336 |
|
|
|
| 337 |
10 |
ale500 |
Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)
|
| 338 |
9 |
ale500 |
|
| 339 |
|
|
|
| 340 |
|
|
|
| 341 |
|
|
Timing summary (Setup and Hold):
|
| 342 |
|
|
---------------
|
| 343 |
|
|
|
| 344 |
10 |
ale500 |
Timing errors: 198 (setup), 0 (hold)
|
| 345 |
|
|
Score: 60114 (setup), 0 (hold)
|
| 346 |
|
|
Cumulative negative slack: 60114 (60114+0)
|
| 347 |
9 |
ale500 |
--------------------------------------------------------------------------------
|
| 348 |
|
|
|
| 349 |
|
|
--------------------------------------------------------------------------------
|
| 350 |
|
|
|
