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9 |
ale500 |
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Loading design for application trce from file P6809_P6809_map.ncd.
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Design name: CC3_top
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NCD version: 3.2
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Vendor: LATTICE
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Device: LCMXO2-7000HE
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Package: TQFP144
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Performance: 4
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Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
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Package Status: Final Version 1.36
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Performance Hardware Data Status: Final) Version 23.4
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Setup and Hold Report
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--------------------------------------------------------------------------------
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Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
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Mon Jan 6 06:54:33 2014
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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| 24 |
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Report Information
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| 25 |
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
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| 27 |
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Design file: P6809_P6809_map.ncd
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Preference file: P6809_P6809.prf
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| 29 |
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Device,speed: LCMXO2-7000HE,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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| 37 |
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================================================================================
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Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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4096 items scored, 672 timing errors detected.
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| 42 |
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 1.741ns
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| 47 |
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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| 48 |
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| 49 |
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Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)
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| 50 |
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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| 51 |
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| 52 |
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Delay: 26.575ns (42.4% logic, 57.6% route), 22 logic levels.
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| 53 |
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| 54 |
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Constraint Details:
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| 55 |
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| 56 |
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26.575ns physical path delay cpu0/SLICE_229 to cpu0/regs/SLICE_64 exceeds
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| 57 |
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25.000ns delay constraint less
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| 58 |
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0.166ns DIN_SET requirement (totaling 24.834ns) by 1.741ns
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| 59 |
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| 60 |
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Physical Path Details:
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| 61 |
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| 62 |
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Data path cpu0/SLICE_229 to cpu0/regs/SLICE_64:
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| 63 |
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| 64 |
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Name Fanout Delay (ns) Site Resource
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| 65 |
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REG_DEL --- 0.452 *SLICE_229.CLK to */SLICE_229.Q0 cpu0/SLICE_229 (from cpu_clkgen)
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| 66 |
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ROUTE 26 e 1.234 */SLICE_229.Q0 to *SLICE_1227.A1 cpu0/alu/rb_in[0]
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| 67 |
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CTOF_DEL --- 0.495 *SLICE_1227.A1 to *SLICE_1227.F1 cpu0/alu/SLICE_1227
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| 68 |
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ROUTE 1 e 1.234 *SLICE_1227.F1 to */SLICE_167.A1 cpu0/alu/alu8/a8/rb_in_i[0]
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| 69 |
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C1TOFCO_DE --- 0.889 */SLICE_167.A1 to *SLICE_167.FCO cpu0/alu/alu8/a8/SLICE_167
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| 70 |
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ROUTE 1 e 0.001 *SLICE_167.FCO to *SLICE_166.FCI cpu0/alu/alu8/a8/un8_q_out_cry_0
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| 71 |
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FCITOF0_DE --- 0.585 *SLICE_166.FCI to */SLICE_166.F0 cpu0/alu/alu8/a8/SLICE_166
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| 72 |
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ROUTE 1 e 1.234 */SLICE_166.F0 to *SLICE_1216.A1 cpu0/alu/alu8/a8/un8_q_out[1]
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| 73 |
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CTOF_DEL --- 0.495 *SLICE_1216.A1 to *SLICE_1216.F1 cpu0/alu/SLICE_1216
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| 74 |
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ROUTE 1 e 1.234 *SLICE_1216.F1 to */SLICE_176.C0 cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO
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| 75 |
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C0TOFCO_DE --- 1.023 */SLICE_176.C0 to *SLICE_176.FCO cpu0/alu/alu8/a8/SLICE_176
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| 76 |
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ROUTE 1 e 0.001 *SLICE_176.FCO to *SLICE_175.FCI cpu0/alu/alu8/a8/q_out_2_cry_2
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| 77 |
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FCITOFCO_D --- 0.162 *SLICE_175.FCI to *SLICE_175.FCO cpu0/alu/alu8/a8/SLICE_175
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| 78 |
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ROUTE 1 e 0.001 *SLICE_175.FCO to *SLICE_174.FCI cpu0/alu/alu8/a8/q_out_2_cry_4
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| 79 |
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FCITOFCO_D --- 0.162 *SLICE_174.FCI to *SLICE_174.FCO cpu0/alu/alu8/a8/SLICE_174
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| 80 |
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ROUTE 1 e 0.001 *SLICE_174.FCO to *SLICE_173.FCI cpu0/alu/alu8/a8/q_out_2_cry_6
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| 81 |
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FCITOF0_DE --- 0.585 *SLICE_173.FCI to */SLICE_173.F0 cpu0/alu/alu8/a8/SLICE_173
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| 82 |
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ROUTE 1 e 1.234 */SLICE_173.F0 to */SLICE_639.A1 cpu0/alu/alu8/a8/N_2388
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| 83 |
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CTOF_DEL --- 0.495 */SLICE_639.A1 to */SLICE_639.F1 cpu0/alu/alu8/a8/SLICE_639
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| 84 |
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ROUTE 2 e 1.234 */SLICE_639.F1 to */SLICE_561.A0 cpu0/alu/alu8/arith_q[7]
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| 85 |
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CTOOFX_DEL --- 0.721 */SLICE_561.A0 to *LICE_561.OFX0 cpu0/alu/alu8/q_out_4[7]/SLICE_561
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| 86 |
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ROUTE 2 e 1.234 *LICE_561.OFX0 to *SLICE_1235.A0 cpu0/alu/alu8/N_160
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| 87 |
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CTOF_DEL --- 0.495 *SLICE_1235.A0 to *SLICE_1235.F0 cpu0/alu/alu8/SLICE_1235
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| 88 |
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ROUTE 2 e 1.234 *SLICE_1235.F0 to */SLICE_542.A1 cpu0/alu/q8_out[7]
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| 89 |
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CTOOFX_DEL --- 0.721 */SLICE_542.A1 to *LICE_542.OFX0 cpu0/alu/alu8/l8/datamux_o_dest[7]/SLICE_542
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| 90 |
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ROUTE 2 e 1.234 *LICE_542.OFX0 to */SLICE_361.B1 cpu0/datamux_o_dest[7]
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| 91 |
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CTOF_DEL --- 0.495 */SLICE_361.B1 to */SLICE_361.F1 cpu0/regs/SLICE_361
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| 92 |
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ROUTE 9 e 1.234 */SLICE_361.F1 to *SLICE_1126.B0 cpu0/regs/left_1[7]
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| 93 |
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CTOF_DEL --- 0.495 *SLICE_1126.B0 to *SLICE_1126.F0 cpu0/regs/SLICE_1126
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| 94 |
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ROUTE 1 e 1.234 *SLICE_1126.F0 to */SLICE_902.A1 cpu0/regs/N_286
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| 95 |
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CTOF_DEL --- 0.495 */SLICE_902.A1 to */SLICE_902.F1 cpu0/regs/SLICE_902
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| 96 |
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ROUTE 1 e 0.480 */SLICE_902.F1 to */SLICE_902.B0 cpu0/regs/SU_16[7]
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| 97 |
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CTOF_DEL --- 0.495 */SLICE_902.B0 to */SLICE_902.F0 cpu0/regs/SLICE_902
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| 98 |
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ROUTE 1 e 1.234 */SLICE_902.F0 to *s/SLICE_68.C1 cpu0/regs/SU_212_i1_mux
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| 99 |
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C1TOFCO_DE --- 0.889 *s/SLICE_68.C1 to */SLICE_68.FCO cpu0/regs/SLICE_68
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| 100 |
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ROUTE 1 e 0.001 */SLICE_68.FCO to */SLICE_67.FCI cpu0/regs/SU_cry[7]
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| 101 |
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FCITOFCO_D --- 0.162 */SLICE_67.FCI to */SLICE_67.FCO cpu0/regs/SLICE_67
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| 102 |
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ROUTE 1 e 0.001 */SLICE_67.FCO to */SLICE_66.FCI cpu0/regs/SU_cry[9]
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| 103 |
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FCITOFCO_D --- 0.162 */SLICE_66.FCI to */SLICE_66.FCO cpu0/regs/SLICE_66
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| 104 |
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ROUTE 1 e 0.001 */SLICE_66.FCO to */SLICE_65.FCI cpu0/regs/SU_cry[11]
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| 105 |
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FCITOFCO_D --- 0.162 */SLICE_65.FCI to */SLICE_65.FCO cpu0/regs/SLICE_65
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| 106 |
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ROUTE 1 e 0.001 */SLICE_65.FCO to */SLICE_64.FCI cpu0/regs/SU_cry[13]
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| 107 |
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FCITOF1_DE --- 0.643 */SLICE_64.FCI to *s/SLICE_64.F1 cpu0/regs/SLICE_64
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| 108 |
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ROUTE 1 e 0.001 *s/SLICE_64.F1 to */SLICE_64.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
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| 109 |
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--------
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| 110 |
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26.575 (42.4% logic, 57.6% route), 22 logic levels.
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| 111 |
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| 112 |
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Warning: 37.396MHz is the maximum frequency for this preference.
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| 113 |
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| 114 |
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Report Summary
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| 115 |
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--------------
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| 116 |
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----------------------------------------------------------------------------
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| 117 |
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Preference | Constraint| Actual|Levels
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| 118 |
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----------------------------------------------------------------------------
|
| 119 |
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|
| 120 |
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FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
| 121 |
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MHz ; | 40.000 MHz| 37.396 MHz| 22 *
|
| 122 |
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|
| 123 |
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----------------------------------------------------------------------------
|
| 124 |
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|
| 125 |
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| 126 |
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1 preference(marked by "*" above) not met.
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| 127 |
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| 128 |
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----------------------------------------------------------------------------
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| 129 |
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Critical Nets | Loads| Errors| % of total
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| 130 |
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----------------------------------------------------------------------------
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| 131 |
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cpu0/alu/q8_out[7] | 2| 550| 81.85%
|
| 132 |
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| | |
|
| 133 |
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cpu0/alu/alu8/N_160 | 2| 550| 81.85%
|
| 134 |
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| | |
|
| 135 |
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cpu0/alu/alu8/a8/N_2388 | 1| 550| 81.85%
|
| 136 |
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| | |
|
| 137 |
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cpu0/alu/alu8/arith_q[7] | 2| 550| 81.85%
|
| 138 |
|
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| | |
|
| 139 |
|
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cpu0/regs/left_1[7] | 9| 550| 81.85%
|
| 140 |
|
|
| | |
|
| 141 |
|
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cpu0/datamux_o_dest[7] | 2| 550| 81.85%
|
| 142 |
|
|
| | |
|
| 143 |
|
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cpu0/alu/alu8/a8/q_out_2_cry_6 | 1| 454| 67.56%
|
| 144 |
|
|
| | |
|
| 145 |
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cpu0/alu/alu8/a8/q_out_2_cry_4 | 1| 336| 50.00%
|
| 146 |
|
|
| | |
|
| 147 |
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cpu0/alu/alu8/a8/un8_q_out_cry_2 | 1| 334| 49.70%
|
| 148 |
|
|
| | |
|
| 149 |
|
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cpu0/regs/SS_cry[7] | 1| 323| 48.07%
|
| 150 |
|
|
| | |
|
| 151 |
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cpu0/regs/SU_cry[7] | 1| 323| 48.07%
|
| 152 |
|
|
| | |
|
| 153 |
|
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cpu0/regs/N_250 | 1| 275| 40.92%
|
| 154 |
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|
| | |
|
| 155 |
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cpu0/regs/N_286 | 1| 275| 40.92%
|
| 156 |
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|
| | |
|
| 157 |
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cpu0/regs/SS_228_i1_mux | 1| 275| 40.92%
|
| 158 |
|
|
| | |
|
| 159 |
|
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cpu0/regs/SS_16[7] | 1| 275| 40.92%
|
| 160 |
|
|
| | |
|
| 161 |
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cpu0/regs/SU_212_i1_mux | 1| 275| 40.92%
|
| 162 |
|
|
| | |
|
| 163 |
|
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cpu0/regs/SU_16[7] | 1| 275| 40.92%
|
| 164 |
|
|
| | |
|
| 165 |
|
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cpu0/regs/SS_cry[9] | 1| 267| 39.73%
|
| 166 |
|
|
| | |
|
| 167 |
|
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cpu0/regs/SU_cry[9] | 1| 267| 39.73%
|
| 168 |
|
|
| | |
|
| 169 |
|
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cpu0/alu/alu8/a8/un8_q_out_cry_4 | 1| 252| 37.50%
|
| 170 |
|
|
| | |
|
| 171 |
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cpu0/alu/alu8/a8/un8_q_out_cry_0 | 1| 220| 32.74%
|
| 172 |
|
|
| | |
|
| 173 |
|
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cpu0/alu/rb_in[0] | 26| 214| 31.85%
|
| 174 |
|
|
| | |
|
| 175 |
|
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cpu0/alu/alu8/a8/rb_in_i[0] | 1| 208| 30.95%
|
| 176 |
|
|
| | |
|
| 177 |
|
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cpu0/regs/SS_cry[11] | 1| 203| 30.21%
|
| 178 |
|
|
| | |
|
| 179 |
|
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cpu0/regs/SU_cry[11] | 1| 203| 30.21%
|
| 180 |
|
|
| | |
|
| 181 |
|
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cpu0/alu/alu8/a8/rb_in_i[1] | 1| 146| 21.73%
|
| 182 |
|
|
| | |
|
| 183 |
|
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cpu0/alu/rb_in[1] | 26| 146| 21.73%
|
| 184 |
|
|
| | |
|
| 185 |
|
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cpu0/alu/alu8/a8/q_out_2_cry_2 | 1| 144| 21.43%
|
| 186 |
|
|
| | |
|
| 187 |
|
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cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO | 1| 114| 16.96%
|
| 188 |
|
|
| | |
|
| 189 |
|
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cpu0/alu/alu8/a8/un8_q_out[3] | 1| 114| 16.96%
|
| 190 |
|
|
| | |
|
| 191 |
|
|
cpu0/alu/alu8/a8/rb_in_i[2] | 1| 112| 16.67%
|
| 192 |
|
|
| | |
|
| 193 |
|
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cpu0/alu/rb_in[2] | 23| 112| 16.67%
|
| 194 |
|
|
| | |
|
| 195 |
|
|
cpu0/regs/SS_cry[13] | 1| 112| 16.67%
|
| 196 |
|
|
| | |
|
| 197 |
|
|
cpu0/regs/SU_cry[13] | 1| 112| 16.67%
|
| 198 |
|
|
| | |
|
| 199 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO_0 | 1| 108| 16.07%
|
| 200 |
|
|
| | |
|
| 201 |
|
|
cpu0/alu/alu8/a8/un8_q_out[6] | 1| 108| 16.07%
|
| 202 |
|
|
| | |
|
| 203 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_3_0_RNO_0 | 1| 106| 15.77%
|
| 204 |
|
|
| | |
|
| 205 |
|
|
cpu0/alu/alu8/a8/un8_q_out[4] | 1| 106| 15.77%
|
| 206 |
|
|
| | |
|
| 207 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_5_0_RNO | 1| 104| 15.48%
|
| 208 |
|
|
| | |
|
| 209 |
|
|
cpu0/alu/alu8/a8/un8_q_out[5] | 1| 104| 15.48%
|
| 210 |
|
|
| | |
|
| 211 |
|
|
cpu0/alu/alu8/a8/un8_q_out_cry_6 | 1| 96| 14.29%
|
| 212 |
|
|
| | |
|
| 213 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_7_0_RNO | 1| 96| 14.29%
|
| 214 |
|
|
| | |
|
| 215 |
|
|
cpu0/alu/alu8/a8/un8_q_out[7] | 1| 96| 14.29%
|
| 216 |
|
|
| | |
|
| 217 |
|
|
cpu0/alu/alu8/a8/rb_in_i[3] | 1| 82| 12.20%
|
| 218 |
|
|
| | |
|
| 219 |
|
|
cpu0/alu/rb_in[3] | 24| 82| 12.20%
|
| 220 |
|
|
| | |
|
| 221 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO_0 | 1| 74| 11.01%
|
| 222 |
|
|
| | |
|
| 223 |
|
|
cpu0/alu/alu8/a8/un8_q_out[2] | 1| 74| 11.01%
|
| 224 |
|
|
| | |
|
| 225 |
|
|
cpu0/alu/alu8/a8/q_out_2_cry_1_0_RNO | 1| 70| 10.42%
|
| 226 |
|
|
| | |
|
| 227 |
|
|
cpu0/alu/alu8/a8/un8_q_out[1] | 1| 70| 10.42%
|
| 228 |
|
|
| | |
|
| 229 |
|
|
----------------------------------------------------------------------------
|
| 230 |
|
|
|
| 231 |
|
|
|
| 232 |
|
|
Clock Domains Analysis
|
| 233 |
|
|
------------------------
|
| 234 |
|
|
|
| 235 |
|
|
Found 1 clocks:
|
| 236 |
|
|
|
| 237 |
|
|
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
|
| 238 |
|
|
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
| 239 |
|
|
|
| 240 |
|
|
|
| 241 |
|
|
Timing summary (Setup):
|
| 242 |
|
|
---------------
|
| 243 |
|
|
|
| 244 |
|
|
Timing errors: 672 Score: 491074
|
| 245 |
|
|
Cumulative negative slack: 491074
|
| 246 |
|
|
|
| 247 |
|
|
Constraints cover 1007472 paths, 1 nets, and 9180 connections (96.2% coverage)
|
| 248 |
|
|
|
| 249 |
|
|
--------------------------------------------------------------------------------
|
| 250 |
|
|
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
|
| 251 |
|
|
Mon Jan 6 06:54:33 2014
|
| 252 |
|
|
|
| 253 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
| 254 |
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
| 255 |
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
| 256 |
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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Report Information
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
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Design file: P6809_P6809_map.ncd
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Preference file: P6809_P6809.prf
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Device,speed: LCMXO2-7000HE,M
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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4096 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.443ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q cpu_clk (from cpu_clkgen +)
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Destination: FF Data in cpu_clk (to cpu_clkgen +)
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Delay: 0.430ns (53.5% logic, 46.5% route), 2 logic levels.
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Constraint Details:
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0.430ns physical path delay SLICE_383 to SLICE_383 meets
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-0.013ns DIN_HLD and
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0.000ns delay constraint requirement (totaling -0.013ns) by 0.443ns
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Physical Path Details:
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Data path SLICE_383 to SLICE_383:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.131 SLICE_383.CLK to SLICE_383.Q0 SLICE_383 (from cpu_clkgen)
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ROUTE 101 e 0.199 SLICE_383.Q0 to SLICE_383.A0 cpu_clk
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CTOF_DEL --- 0.099 SLICE_383.A0 to SLICE_383.F0 SLICE_383
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ROUTE 1 e 0.001 SLICE_383.F0 to SLICE_383.DI0 cpu_clk_i (to cpu_clkgen)
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--------
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0.430 (53.5% logic, 46.5% route), 2 logic levels.
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Report Summary
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--------------
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----------------------------------------------------------------------------
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Preference(MIN Delays) | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY NET "cpu_clkgen" 40.000000 | | |
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MHz ; | -| -| 2
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----------------------------------------------------------------------------
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All preferences were met.
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Clock Domains Analysis
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------------------------
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Found 1 clocks:
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Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 290
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Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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Timing summary (Hold):
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---------------
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Timing errors: 0 Score: 0
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Cumulative negative slack: 0
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Constraints cover 1007472 paths, 1 nets, and 9435 connections (98.9% coverage)
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Timing summary (Setup and Hold):
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---------------
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Timing errors: 672 (setup), 0 (hold)
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Score: 491074 (setup), 0 (hold)
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Cumulative negative slack: 491074 (491074+0)
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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