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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809.twr] - Blame information for rev 10

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Line No. Rev Author Line
1 9 ale500 
 
2 
Loading design for application trce from file P6809_P6809.ncd.
3 
Design name: CC3_top
4 
NCD version: 3.2
5 
Vendor:      LATTICE
6 
Device:      LCMXO2-7000HE
7 
Package:     TQFP144
8 
Performance: 4
9 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
10 
Package Status:                     Final          Version 1.36
11 
Performance Hardware Data Status:   Final)         Version 23.4
12 
Setup and Hold Report
13 
 
14 
--------------------------------------------------------------------------------
15 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
16 10 ale500 
Thu Feb  6 15:36:11 2014
17 9 ale500 
 
18 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
19 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
20 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
21 
Copyright (c) 2001 Agere Systems   All rights reserved.
22 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
23 
 
24 
Report Information
25 
------------------
26 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
27 
Design file:     P6809_P6809.ncd
28 
Preference file: P6809_P6809.prf
29 
Device,speed:    LCMXO2-7000HE,4
30 
Report level:    verbose report, limited to 10 items per preference
31 
--------------------------------------------------------------------------------
32 
 
33 
BLOCK ASYNCPATHS
34 
BLOCK RESETPATHS
35 
--------------------------------------------------------------------------------
36 
 
37 
 
38 
 
39 
================================================================================
40 
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
41 
            4096 items scored, 0 timing errors detected.
42 
--------------------------------------------------------------------------------
43 
 
44 
 
45 10 ale500 
Passed: The following path meets requirements by 0.251ns
46 9 ale500 
 
47 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
48 
 
49 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
50 9 ale500 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
51 
 
52 10 ale500 
   Delay:              24.583ns  (36.2% logic, 63.8% route), 18 logic levels.
53 9 ale500 
 
54 
 Constraint Details:
55 
 
56 10 ale500 
     24.583ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
57 9 ale500 
     25.000ns delay constraint less
58 
      0.000ns skew and
59 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.251ns
60 9 ale500 
 
61 
 Physical Path Details:
62 
 
63 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
64 9 ale500 
 
65 
   Name    Fanout   Delay (ns)          Site               Resource
66 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
67 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
68 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
69 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
70 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
71 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
72 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
73 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
74 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
75 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
76 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
77 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
78 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
79 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
80 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
81 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
82 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
83 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
84 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
85 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
86 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
87 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
88 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
89 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
90 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
91 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
92 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
93 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
94 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
95 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
96 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
97 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
98 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
99 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
100 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
101 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
102 9 ale500 
                  --------
103 10 ale500 
                   24.583   (36.2% logic, 63.8% route), 18 logic levels.
104 9 ale500 
 
105 
 Clock Skew Details:
106 
 
107 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
108 9 ale500 
 
109 
   Name    Fanout   Delay (ns)          Site               Resource
110 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
111 9 ale500 
                  --------
112 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
113 
 
114 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
115 9 ale500 
 
116 
   Name    Fanout   Delay (ns)          Site               Resource
117 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
118 9 ale500 
                  --------
119 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
120 
 
121 
 
122 10 ale500 
Passed: The following path meets requirements by 0.309ns
123 9 ale500 
 
124 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
125 
 
126 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
127 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
128 9 ale500 
 
129 10 ale500 
   Delay:              24.525ns  (36.0% logic, 64.0% route), 18 logic levels.
130 9 ale500 
 
131 
 Constraint Details:
132 
 
133 10 ale500 
     24.525ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
134 9 ale500 
     25.000ns delay constraint less
135 
      0.000ns skew and
136 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.309ns
137 9 ale500 
 
138 
 Physical Path Details:
139 
 
140 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
141 9 ale500 
 
142 
   Name    Fanout   Delay (ns)          Site               Resource
143 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
144 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
145 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
146 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
147 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
148 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
149 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
150 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
151 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
152 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
153 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
154 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
155 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
156 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
157 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
158 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
159 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
160 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
161 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
162 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
163 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
164 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
165 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
166 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
167 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
168 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
169 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
170 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
171 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
172 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
173 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
174 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
175 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
176 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
177 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
178 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
179 9 ale500 
                  --------
180 10 ale500 
                   24.525   (36.0% logic, 64.0% route), 18 logic levels.
181 9 ale500 
 
182 
 Clock Skew Details:
183 
 
184 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
185 9 ale500 
 
186 
   Name    Fanout   Delay (ns)          Site               Resource
187 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
188 9 ale500 
                  --------
189 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
190 
 
191 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
192 9 ale500 
 
193 
   Name    Fanout   Delay (ns)          Site               Resource
194 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
195 9 ale500 
                  --------
196 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
197 
 
198 
 
199 10 ale500 
Passed: The following path meets requirements by 0.324ns
200 9 ale500 
 
201 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
202 
 
203 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
204 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
205 9 ale500 
 
206 10 ale500 
   Delay:              24.510ns  (36.1% logic, 63.9% route), 19 logic levels.
207 9 ale500 
 
208 
 Constraint Details:
209 
 
210 10 ale500 
     24.510ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
211 9 ale500 
     25.000ns delay constraint less
212 
      0.000ns skew and
213 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.324ns
214 9 ale500 
 
215 
 Physical Path Details:
216 
 
217 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
218 9 ale500 
 
219 
   Name    Fanout   Delay (ns)          Site               Resource
220 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
221 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
222 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
223 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
224 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
225 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
226 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
227 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
228 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
229 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
230 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
231 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
232 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
233 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
234 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
235 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
236 
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
237 
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
238 
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
239 
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
240 
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
241 
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
242 
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
243 
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
244 
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
245 
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
246 
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
247 
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
248 
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
249 
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
250 
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
251 
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
252 
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
253 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
254 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
255 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
256 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
257 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
258 9 ale500 
                  --------
259 10 ale500 
                   24.510   (36.1% logic, 63.9% route), 19 logic levels.
260 9 ale500 
 
261 
 Clock Skew Details:
262 
 
263 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
264 9 ale500 
 
265 
   Name    Fanout   Delay (ns)          Site               Resource
266 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
267 9 ale500 
                  --------
268 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
269 
 
270 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
271 9 ale500 
 
272 
   Name    Fanout   Delay (ns)          Site               Resource
273 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
274 9 ale500 
                  --------
275 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
276 
 
277 
 
278 10 ale500 
Passed: The following path meets requirements by 0.351ns
279 9 ale500 
 
280 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
281 
 
282 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
283 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
284 9 ale500 
 
285 10 ale500 
   Delay:              24.483ns  (36.2% logic, 63.8% route), 19 logic levels.
286 9 ale500 
 
287 
 Constraint Details:
288 
 
289 10 ale500 
     24.483ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
290 9 ale500 
     25.000ns delay constraint less
291 
      0.000ns skew and
292 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.351ns
293 9 ale500 
 
294 
 Physical Path Details:
295 
 
296 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
297 9 ale500 
 
298 
   Name    Fanout   Delay (ns)          Site               Resource
299 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
300 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
301 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
302 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
303 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
304 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
305 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
306 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
307 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
308 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
309 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
310 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
311 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
312 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
313 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
314 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
315 
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
316 
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
317 
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
318 
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
319 
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
320 
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
321 
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
322 
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
323 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
324 
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
325 
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
326 
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
327 
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
328 
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
329 
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
330 
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
331 
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
332 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
333 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
334 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
335 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
336 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
337 9 ale500 
                  --------
338 10 ale500 
                   24.483   (36.2% logic, 63.8% route), 19 logic levels.
339 9 ale500 
 
340 
 Clock Skew Details:
341 
 
342 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
343 9 ale500 
 
344 
   Name    Fanout   Delay (ns)          Site               Resource
345 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
346 9 ale500 
                  --------
347 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
348 
 
349 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
350 9 ale500 
 
351 
   Name    Fanout   Delay (ns)          Site               Resource
352 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
353 9 ale500 
                  --------
354 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
355 
 
356 
 
357 10 ale500 
Passed: The following path meets requirements by 0.362ns
358 9 ale500 
 
359 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
360 
 
361 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[1]  (from cpu_clkgen +)
362 9 ale500 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
363 
 
364 10 ale500 
   Delay:              24.472ns  (36.3% logic, 63.7% route), 18 logic levels.
365 9 ale500 
 
366 
 Constraint Details:
367 
 
368 10 ale500 
     24.472ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
369 9 ale500 
     25.000ns delay constraint less
370 
      0.000ns skew and
371 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.362ns
372 9 ale500 
 
373 
 Physical Path Details:
374 
 
375 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
376 9 ale500 
 
377 
   Name    Fanout   Delay (ns)          Site               Resource
378 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q1 SLICE_260 (from cpu_clkgen)
379 
ROUTE        30     1.613     R18C14A.Q1 to     R18C24D.D1 cpu0/k_ind_ea[1]
380 
CTOF_DEL    ---     0.495     R18C24D.D1 to     R18C24D.F1 cpu0/SLICE_337
381 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
382 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
383 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
384 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
385 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
386 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
387 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
388 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
389 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
390 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
391 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
392 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
393 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
394 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
395 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
396 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
397 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
398 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
399 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
400 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
401 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
402 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
403 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
404 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
405 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
406 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
407 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
408 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
409 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
410 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
411 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
412 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
413 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
414 9 ale500 
                  --------
415 10 ale500 
                   24.472   (36.3% logic, 63.7% route), 18 logic levels.
416 9 ale500 
 
417 
 Clock Skew Details:
418 
 
419 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
420 9 ale500 
 
421 
   Name    Fanout   Delay (ns)          Site               Resource
422 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
423 9 ale500 
                  --------
424 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
425 
 
426 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
427 9 ale500 
 
428 
   Name    Fanout   Delay (ns)          Site               Resource
429 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
430 9 ale500 
                  --------
431 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
432 
 
433 
 
434 10 ale500 
Passed: The following path meets requirements by 0.382ns
435 9 ale500 
 
436 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
437 
 
438 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
439 9 ale500 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
440 
 
441 10 ale500 
   Delay:              24.452ns  (36.0% logic, 64.0% route), 19 logic levels.
442 9 ale500 
 
443 
 Constraint Details:
444 
 
445 10 ale500 
     24.452ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
446 9 ale500 
     25.000ns delay constraint less
447 
      0.000ns skew and
448 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.382ns
449 9 ale500 
 
450 
 Physical Path Details:
451 
 
452 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
453 9 ale500 
 
454 
   Name    Fanout   Delay (ns)          Site               Resource
455 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
456 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
457 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
458 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
459 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
460 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
461 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
462 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
463 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
464 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
465 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
466 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
467 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
468 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
469 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
470 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
471 
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
472 
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
473 
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
474 
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
475 
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
476 
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
477 
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
478 
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
479 
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
480 
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
481 
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
482 
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
483 
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
484 
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
485 
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
486 
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
487 
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
488 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
489 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
490 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
491 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
492 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
493 9 ale500 
                  --------
494 10 ale500 
                   24.452   (36.0% logic, 64.0% route), 19 logic levels.
495 9 ale500 
 
496 
 Clock Skew Details:
497 
 
498 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
499 9 ale500 
 
500 
   Name    Fanout   Delay (ns)          Site               Resource
501 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
502 9 ale500 
                  --------
503 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
504 
 
505 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
506 9 ale500 
 
507 
   Name    Fanout   Delay (ns)          Site               Resource
508 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
509 9 ale500 
                  --------
510 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
511 
 
512 
 
513 10 ale500 
Passed: The following path meets requirements by 0.391ns
514 9 ale500 
 
515 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
516 
 
517 10 ale500 
   Source:         FF         Q              cpu0/regs/IY_pipe_14  (from cpu_clkgen +)
518 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
519 9 ale500 
 
520 10 ale500 
   Delay:              24.443ns  (39.4% logic, 60.6% route), 20 logic levels.
521 9 ale500 
 
522 
 Constraint Details:
523 
 
524 10 ale500 
     24.443ns physical path delay cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55 meets
525 9 ale500 
     25.000ns delay constraint less
526 
      0.000ns skew and
527 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.391ns
528 9 ale500 
 
529 
 Physical Path Details:
530 
 
531 10 ale500 
      Data path cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55:
532 9 ale500 
 
533 
   Name    Fanout   Delay (ns)          Site               Resource
534 10 ale500 
REG_DEL     ---     0.452    R16C22A.CLK to     R16C22A.Q0 cpu0/regs/SLICE_323 (from cpu_clkgen)
535 
ROUTE        16     1.390     R16C22A.Q0 to     R16C25A.A1 cpu0/regs/IY_1_sqmuxaf
536 
CTOF_DEL    ---     0.495     R16C25A.A1 to     R16C25A.F1 cpu0/regs/SLICE_1012
537 
ROUTE         1     0.693     R16C25A.F1 to     R16C25A.B0 cpu0/regs/N_665
538 
CTOF_DEL    ---     0.495     R16C25A.B0 to     R16C25A.F0 cpu0/regs/SLICE_1012
539 
ROUTE         3     1.435     R16C25A.F0 to     R21C25B.C1 cpu0/regs/IY[0]
540 
CTOOFX_DEL  ---     0.721     R21C25B.C1 to   R21C25B.OFX0 cpu0/regs/ea/ea_reg_3[0]/SLICE_511
541 
ROUTE         5     1.487   R21C25B.OFX0 to     R21C19D.D0 cpu0/regs/ea_reg[0]
542 
CTOF_DEL    ---     0.495     R21C19D.D0 to     R21C19D.F0 cpu0/regs/SLICE_917
543 
ROUTE         2     1.152     R21C19D.F0 to     R19C18A.C1 cpu0/regs/ea/N_72
544 
C1TOFCO_DE  ---     0.889     R19C18A.C1 to    R19C18A.FCO cpu0/regs/ea/SLICE_45
545 
ROUTE         1     0.000    R19C18A.FCO to    R19C18B.FCI cpu0/regs/ea/eamem_addr_o_cry_0
546 
FCITOFCO_D  ---     0.162    R19C18B.FCI to    R19C18B.FCO cpu0/regs/ea/SLICE_44
547 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
548 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
549 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
550 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
551 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
552 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
553 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
554 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
555 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
556 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
557 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
558 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
559 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
560 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
561 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
562 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
563 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
564 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
565 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
566 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
567 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
568 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
569 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
570 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
571 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
572 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
573 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
574 9 ale500 
                  --------
575 10 ale500 
                   24.443   (39.4% logic, 60.6% route), 20 logic levels.
576 9 ale500 
 
577 
 Clock Skew Details:
578 
 
579 10 ale500 
      Source Clock Path clk40_i to cpu0/regs/SLICE_323:
580 9 ale500 
 
581 
   Name    Fanout   Delay (ns)          Site               Resource
582 10 ale500 
ROUTE       367     2.399       27.PADDI to    R16C22A.CLK cpu_clkgen
583 9 ale500 
                  --------
584 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
585 
 
586 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
587 9 ale500 
 
588 
   Name    Fanout   Delay (ns)          Site               Resource
589 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
590 9 ale500 
                  --------
591 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
592 
 
593 
 
594 10 ale500 
Passed: The following path meets requirements by 0.396ns
595 9 ale500 
 
596 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
597 
 
598 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
599 
   Destination:    FF         Data in        cpu0/regs/SS[15]  (to cpu_clkgen +)
600 9 ale500 
 
601 10 ale500 
   Delay:              24.438ns  (36.4% logic, 63.6% route), 18 logic levels.
602 9 ale500 
 
603 
 Constraint Details:
604 
 
605 10 ale500 
     24.438ns physical path delay SLICE_260 to cpu0/regs/SLICE_64 meets
606 9 ale500 
     25.000ns delay constraint less
607 
      0.000ns skew and
608 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.396ns
609 9 ale500 
 
610 
 Physical Path Details:
611 
 
612 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_64:
613 9 ale500 
 
614 
   Name    Fanout   Delay (ns)          Site               Resource
615 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
616 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
617 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
618 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
619 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
620 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
621 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
622 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
623 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
624 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
625 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
626 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
627 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
628 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
629 
FCITOF1_DE  ---     0.643    R19C19A.FCI to     R19C19A.F1 cpu0/regs/ea/SLICE_41
630 
ROUTE         4     2.403     R19C19A.F1 to     R16C32D.D0 cpu0/regs/ea/regs_o_eamem_addr[8]
631 
CTOF_DEL    ---     0.495     R16C32D.D0 to     R16C32D.F0 cpu0/regs/SLICE_922
632 
ROUTE         1     0.645     R16C32D.F0 to     R14C32C.D0 cpu0/regs/ea/N_1412
633 
CTOF_DEL    ---     0.495     R14C32C.D0 to     R14C32C.F0 cpu0/SLICE_900
634 
ROUTE         2     1.704     R14C32C.F0 to     R12C25C.D0 cpu0/datamux_o_dest[8]
635 
CTOF_DEL    ---     0.495     R12C25C.D0 to     R12C25C.F0 cpu0/regs/SLICE_361
636 
ROUTE         6     0.469     R12C25C.F0 to     R12C25B.C1 cpu0/regs/left_1[8]
637 
CTOF_DEL    ---     0.495     R12C25B.C1 to     R12C25B.F1 cpu0/regs/SLICE_1189
638 
ROUTE         1     1.088     R12C25B.F1 to     R14C25C.B1 cpu0/regs/N_251
639 
CTOF_DEL    ---     0.495     R14C25C.B1 to     R14C25C.F1 cpu0/regs/SLICE_955
640 
ROUTE         1     0.626     R14C25C.F1 to     R14C25C.D0 cpu0/regs/SS_16[8]
641 
CTOF_DEL    ---     0.495     R14C25C.D0 to     R14C25C.F0 cpu0/regs/SLICE_955
642 
ROUTE         1     1.570     R14C25C.F0 to     R10C26B.C0 cpu0/regs/SS_231_i1_mux
643 
C0TOFCO_DE  ---     1.023     R10C26B.C0 to    R10C26B.FCO cpu0/regs/SLICE_67
644 
ROUTE         1     0.000    R10C26B.FCO to    R10C26C.FCI cpu0/regs/SS_cry[9]
645 
FCITOFCO_D  ---     0.162    R10C26C.FCI to    R10C26C.FCO cpu0/regs/SLICE_66
646 
ROUTE         1     0.000    R10C26C.FCO to    R10C26D.FCI cpu0/regs/SS_cry[11]
647 
FCITOFCO_D  ---     0.162    R10C26D.FCI to    R10C26D.FCO cpu0/regs/SLICE_65
648 
ROUTE         1     0.000    R10C26D.FCO to    R10C27A.FCI cpu0/regs/SS_cry[13]
649 
FCITOF1_DE  ---     0.643    R10C27A.FCI to     R10C27A.F1 cpu0/regs/SLICE_64
650 
ROUTE         1     0.000     R10C27A.F1 to    R10C27A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
651 9 ale500 
                  --------
652 10 ale500 
                   24.438   (36.4% logic, 63.6% route), 18 logic levels.
653 9 ale500 
 
654 
 Clock Skew Details:
655 
 
656 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
657 9 ale500 
 
658 
   Name    Fanout   Delay (ns)          Site               Resource
659 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
660 9 ale500 
                  --------
661 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
662 
 
663 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_64:
664 
 
665 
   Name    Fanout   Delay (ns)          Site               Resource
666 10 ale500 
ROUTE       367     2.399       27.PADDI to    R10C27A.CLK cpu_clkgen
667 9 ale500 
                  --------
668 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
669 
 
670 
 
671 10 ale500 
Passed: The following path meets requirements by 0.409ns
672 9 ale500 
 
673 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
674 
 
675 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
676 
   Destination:    FF         Data in        cpu0/regs/SU[14]  (to cpu_clkgen +)
677 9 ale500 
 
678 10 ale500 
   Delay:              24.425ns  (36.0% logic, 64.0% route), 19 logic levels.
679 9 ale500 
 
680 
 Constraint Details:
681 
 
682 10 ale500 
     24.425ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
683 9 ale500 
     25.000ns delay constraint less
684 
      0.000ns skew and
685 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.409ns
686 9 ale500 
 
687 
 Physical Path Details:
688 
 
689 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
690 9 ale500 
 
691 
   Name    Fanout   Delay (ns)          Site               Resource
692 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
693 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
694 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
695 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
696 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
697 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
698 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
699 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
700 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
701 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
702 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
703 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
704 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
705 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
706 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
707 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
708 
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
709 
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
710 
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
711 
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
712 
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
713 
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
714 
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
715 
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
716 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
717 
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
718 
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
719 
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
720 
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
721 
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
722 
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
723 
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
724 
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
725 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
726 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
727 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
728 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
729 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
730 9 ale500 
                  --------
731 10 ale500 
                   24.425   (36.0% logic, 64.0% route), 19 logic levels.
732 9 ale500 
 
733 
 Clock Skew Details:
734 
 
735 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
736 9 ale500 
 
737 
   Name    Fanout   Delay (ns)          Site               Resource
738 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
739 9 ale500 
                  --------
740 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
741 
 
742 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
743 9 ale500 
 
744 
   Name    Fanout   Delay (ns)          Site               Resource
745 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
746 9 ale500 
                  --------
747 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
748 
 
749 
 
750 10 ale500 
Passed: The following path meets requirements by 0.413ns
751 9 ale500 
 
752 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
753 
 
754 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
755 
   Destination:    FF         Data in        cpu0/regs/SU[13]  (to cpu_clkgen +)
756 9 ale500 
 
757 10 ale500 
   Delay:              24.421ns  (35.7% logic, 64.3% route), 17 logic levels.
758 9 ale500 
 
759 
 Constraint Details:
760 
 
761 10 ale500 
     24.421ns physical path delay SLICE_260 to cpu0/regs/SLICE_56 meets
762 9 ale500 
     25.000ns delay constraint less
763 
      0.000ns skew and
764 10 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.413ns
765 9 ale500 
 
766 
 Physical Path Details:
767 
 
768 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_56:
769 9 ale500 
 
770 
   Name    Fanout   Delay (ns)          Site               Resource
771 10 ale500 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
772 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
773 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
774 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
775 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
776 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
777 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
778 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
779 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
780 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
781 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
782 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
783 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
784 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
785 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
786 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
787 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
788 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
789 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
790 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
791 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
792 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
793 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
794 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
795 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
796 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
797 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
798 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
799 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
800 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
801 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
802 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
803 
FCITOF1_DE  ---     0.643    R11C23D.FCI to     R11C23D.F1 cpu0/regs/SLICE_56
804 
ROUTE         1     0.000     R11C23D.F1 to    R11C23D.DI1 cpu0/regs/SU_s[13] (to cpu_clkgen)
805 9 ale500 
                  --------
806 10 ale500 
                   24.421   (35.7% logic, 64.3% route), 17 logic levels.
807 9 ale500 
 
808 
 Clock Skew Details:
809 
 
810 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
811 9 ale500 
 
812 
   Name    Fanout   Delay (ns)          Site               Resource
813 10 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
814 9 ale500 
                  --------
815 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
816 
 
817 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_56:
818 9 ale500 
 
819 
   Name    Fanout   Delay (ns)          Site               Resource
820 10 ale500 
ROUTE       367     2.399       27.PADDI to    R11C23D.CLK cpu_clkgen
821 9 ale500 
                  --------
822 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
823 
 
824 10 ale500 
Report:   40.406MHz is the maximum frequency for this preference.
825 9 ale500 
 
826 
Report Summary
827 
--------------
828 
----------------------------------------------------------------------------
829 
Preference                              |   Constraint|       Actual|Levels
830 
----------------------------------------------------------------------------
831 
                                        |             |             |
832 
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
833 10 ale500 
MHz ;                                   |   40.000 MHz|   40.406 MHz|  18
834 9 ale500 
                                        |             |             |
835 
----------------------------------------------------------------------------
836 
 
837 
 
838 
All preferences were met.
839 
 
840 
 
841 
Clock Domains Analysis
842 
------------------------
843 
 
844 
Found 1 clocks:
845 
 
846 10 ale500 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
847 9 ale500 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
848 
 
849 
 
850 
Timing summary (Setup):
851 
---------------
852 
 
853 
Timing errors: 0  Score: 0
854 
Cumulative negative slack: 0
855 
 
856 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
857 9 ale500 
 
858 
--------------------------------------------------------------------------------
859 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
860 10 ale500 
Thu Feb  6 15:36:12 2014
861 9 ale500 
 
862 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
863 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
864 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
865 
Copyright (c) 2001 Agere Systems   All rights reserved.
866 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
867 
 
868 
Report Information
869 
------------------
870 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
871 
Design file:     P6809_P6809.ncd
872 
Preference file: P6809_P6809.prf
873 
Device,speed:    LCMXO2-7000HE,m
874 
Report level:    verbose report, limited to 10 items per preference
875 
--------------------------------------------------------------------------------
876 
 
877 
BLOCK ASYNCPATHS
878 
BLOCK RESETPATHS
879 
--------------------------------------------------------------------------------
880 
 
881 
 
882 
 
883 
================================================================================
884 
Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
885 
            4096 items scored, 0 timing errors detected.
886 
--------------------------------------------------------------------------------
887 
 
888 
 
889 10 ale500 
Passed: The following path meets requirements by 0.217ns
890 9 ale500 
 
891 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
892 
 
893 10 ale500 
   Source:         FF         Q              textctrl/chars_data[6]  (from cpu_clkgen +)
894 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)
895 9 ale500 
 
896 10 ale500 
   Delay:               0.322ns  (40.7% logic, 59.3% route), 1 logic levels.
897 9 ale500 
 
898 
 Constraint Details:
899 
 
900 10 ale500 
      0.322ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
901 
      0.052ns ADDR_HLD and
902 9 ale500 
      0.000ns delay constraint less
903 10 ale500 
     -0.053ns skew requirement (totaling 0.105ns) by 0.217ns
904 9 ale500 
 
905 
 Physical Path Details:
906 
 
907 10 ale500 
      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
908 9 ale500 
 
909 
   Name    Fanout   Delay (ns)          Site               Resource
910 10 ale500 
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q0 SLICE_454 (from cpu_clkgen)
911 
ROUTE         4     0.191     R14C17C.Q0 to *_R13C16.ADA11 textctrl/chars_data[6] (to cpu_clkgen)
912 9 ale500 
                  --------
913 10 ale500 
                    0.322   (40.7% logic, 59.3% route), 1 logic levels.
914 9 ale500 
 
915 
 Clock Skew Details:
916 
 
917 10 ale500 
      Source Clock Path clk40_i to SLICE_454:
918 9 ale500 
 
919 
   Name    Fanout   Delay (ns)          Site               Resource
920 10 ale500 
ROUTE       367     0.846       27.PADDI to    R14C17C.CLK cpu_clkgen
921 9 ale500 
                  --------
922 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
923 
 
924 10 ale500 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
925 9 ale500 
 
926 
   Name    Fanout   Delay (ns)          Site               Resource
927 10 ale500 
ROUTE       367     0.899       27.PADDI to *R_R13C16.CLKA cpu_clkgen
928 9 ale500 
                  --------
929 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
930 
 
931 
 
932 10 ale500 
Passed: The following path meets requirements by 0.234ns
933 9 ale500 
 
934 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
935 
 
936 10 ale500 
   Source:         FF         Q              textctrl/chars_data[7]  (from cpu_clkgen +)
937 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)
938 9 ale500 
 
939 10 ale500 
   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.
940 9 ale500 
 
941 
 Constraint Details:
942 
 
943 10 ale500 
      0.339ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
944 
      0.052ns ADDR_HLD and
945 9 ale500 
      0.000ns delay constraint less
946 10 ale500 
     -0.053ns skew requirement (totaling 0.105ns) by 0.234ns
947 9 ale500 
 
948 
 Physical Path Details:
949 
 
950 10 ale500 
      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
951 9 ale500 
 
952 
   Name    Fanout   Delay (ns)          Site               Resource
953 10 ale500 
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q1 SLICE_454 (from cpu_clkgen)
954 
ROUTE         4     0.208     R14C17C.Q1 to *_R13C16.ADA12 textctrl/chars_data[7] (to cpu_clkgen)
955 9 ale500 
                  --------
956 10 ale500 
                    0.339   (38.6% logic, 61.4% route), 1 logic levels.
957 9 ale500 
 
958 
 Clock Skew Details:
959 
 
960 10 ale500 
      Source Clock Path clk40_i to SLICE_454:
961 9 ale500 
 
962 
   Name    Fanout   Delay (ns)          Site               Resource
963 10 ale500 
ROUTE       367     0.846       27.PADDI to    R14C17C.CLK cpu_clkgen
964 9 ale500 
                  --------
965 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
966 
 
967 10 ale500 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
968 9 ale500 
 
969 
   Name    Fanout   Delay (ns)          Site               Resource
970 10 ale500 
ROUTE       367     0.899       27.PADDI to *R_R13C16.CLKA cpu_clkgen
971 9 ale500 
                  --------
972 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
973 
 
974 
 
975 10 ale500 
Passed: The following path meets requirements by 0.344ns
976 9 ale500 
 
977 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
978 
 
979 10 ale500 
   Source:         FF         Q              reset_cnt[0]  (from cpu_clkgen +)
980 
   Destination:    FF         Data in        reset_cnt[0]  (to cpu_clkgen +)
981 9 ale500 
 
982 10 ale500 
   Delay:               0.288ns  (45.5% logic, 54.5% route), 1 logic levels.
983 9 ale500 
 
984 
 Constraint Details:
985 
 
986 10 ale500 
      0.288ns physical path delay SLICE_444 to SLICE_444 meets
987 
     -0.056ns LSR_HLD and
988 9 ale500 
      0.000ns delay constraint less
989 10 ale500 
      0.000ns skew requirement (totaling -0.056ns) by 0.344ns
990 9 ale500 
 
991 
 Physical Path Details:
992 
 
993 10 ale500 
      Data path SLICE_444 to SLICE_444:
994 9 ale500 
 
995 
   Name    Fanout   Delay (ns)          Site               Resource
996 10 ale500 
REG_DEL     ---     0.131     R19C8D.CLK to      R19C8D.Q0 SLICE_444 (from cpu_clkgen)
997 
ROUTE         5     0.157      R19C8D.Q0 to     R19C8D.LSR reset_cnt[0] (to cpu_clkgen)
998 9 ale500 
                  --------
999 10 ale500 
                    0.288   (45.5% logic, 54.5% route), 1 logic levels.
1000 9 ale500 
 
1001 
 Clock Skew Details:
1002 
 
1003 10 ale500 
      Source Clock Path clk40_i to SLICE_444:
1004 9 ale500 
 
1005 
   Name    Fanout   Delay (ns)          Site               Resource
1006 10 ale500 
ROUTE       367     0.846       27.PADDI to     R19C8D.CLK cpu_clkgen
1007 9 ale500 
                  --------
1008 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1009 
 
1010 10 ale500 
      Destination Clock Path clk40_i to SLICE_444:
1011 9 ale500 
 
1012 
   Name    Fanout   Delay (ns)          Site               Resource
1013 10 ale500 
ROUTE       367     0.846       27.PADDI to     R19C8D.CLK cpu_clkgen
1014 9 ale500 
                  --------
1015 10 ale500 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1016 9 ale500 
 
1017 
 
1018 10 ale500 
Passed: The following path meets requirements by 0.370ns
1019 9 ale500 
 
1020 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1021 
 
1022 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[0]  (from cpu_clkgen +)
1023 
   Destination:    FF         Data in        textctrl/blink_cnt[0]  (to cpu_clkgen +)
1024 9 ale500 
 
1025 10 ale500 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1026 9 ale500 
 
1027 
 Constraint Details:
1028 
 
1029 10 ale500 
      0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
1030 
     -0.013ns DIN_HLD and
1031 9 ale500 
      0.000ns delay constraint less
1032 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1033 9 ale500 
 
1034 
 Physical Path Details:
1035 
 
1036 10 ale500 
      Data path textctrl/SLICE_29 to textctrl/SLICE_29:
1037 9 ale500 
 
1038 
   Name    Fanout   Delay (ns)          Site               Resource
1039 10 ale500 
REG_DEL     ---     0.131    R25C10A.CLK to     R25C10A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
1040 
ROUTE         1     0.127     R25C10A.Q1 to     R25C10A.A1 textctrl/blink_cnt[0]
1041 
CTOF_DEL    ---     0.099     R25C10A.A1 to     R25C10A.F1 textctrl/SLICE_29
1042 
ROUTE         1     0.000     R25C10A.F1 to    R25C10A.DI1 textctrl/blink_cnt_s[0] (to cpu_clkgen)
1043 9 ale500 
                  --------
1044 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1045 9 ale500 
 
1046 
 Clock Skew Details:
1047 
 
1048 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_29:
1049 9 ale500 
 
1050 
   Name    Fanout   Delay (ns)          Site               Resource
1051 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10A.CLK cpu_clkgen
1052 9 ale500 
                  --------
1053 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1054 9 ale500 
 
1055 10 ale500 
      Destination Clock Path clk40_i to textctrl/SLICE_29:
1056 9 ale500 
 
1057 
   Name    Fanout   Delay (ns)          Site               Resource
1058 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10A.CLK cpu_clkgen
1059 9 ale500 
                  --------
1060 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1061 9 ale500 
 
1062 
 
1063 10 ale500 
Passed: The following path meets requirements by 0.370ns
1064 9 ale500 
 
1065 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1066 
 
1067 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[4]  (from cpu_clkgen +)
1068 
   Destination:    FF         Data in        textctrl/blink_cnt[4]  (to cpu_clkgen +)
1069 9 ale500 
 
1070 10 ale500 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1071 9 ale500 
 
1072 
 Constraint Details:
1073 
 
1074 10 ale500 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1075 
     -0.013ns DIN_HLD and
1076 9 ale500 
      0.000ns delay constraint less
1077 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1078 9 ale500 
 
1079 
 Physical Path Details:
1080 
 
1081 10 ale500 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1082 9 ale500 
 
1083 
   Name    Fanout   Delay (ns)          Site               Resource
1084 10 ale500 
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q1 textctrl/SLICE_27 (from cpu_clkgen)
1085 
ROUTE         1     0.127     R25C10C.Q1 to     R25C10C.A1 textctrl/blink_cnt[4]
1086 
CTOF_DEL    ---     0.099     R25C10C.A1 to     R25C10C.F1 textctrl/SLICE_27
1087 
ROUTE         1     0.000     R25C10C.F1 to    R25C10C.DI1 textctrl/blink_cnt_s[4] (to cpu_clkgen)
1088 9 ale500 
                  --------
1089 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1090 9 ale500 
 
1091 
 Clock Skew Details:
1092 
 
1093 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1094 9 ale500 
 
1095 
   Name    Fanout   Delay (ns)          Site               Resource
1096 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1097 9 ale500 
                  --------
1098 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1099 9 ale500 
 
1100 10 ale500 
      Destination Clock Path clk40_i to textctrl/SLICE_27:
1101 9 ale500 
 
1102 
   Name    Fanout   Delay (ns)          Site               Resource
1103 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1104 9 ale500 
                  --------
1105 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1106 9 ale500 
 
1107 
 
1108 
Passed: The following path meets requirements by 0.370ns
1109 
 
1110 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1111 
 
1112 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[3]  (from cpu_clkgen +)
1113 
   Destination:    FF         Data in        textctrl/blink_cnt[3]  (to cpu_clkgen +)
1114 9 ale500 
 
1115 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1116 
 
1117 
 Constraint Details:
1118 
 
1119 10 ale500 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1120 9 ale500 
     -0.013ns DIN_HLD and
1121 
      0.000ns delay constraint less
1122 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1123 
 
1124 
 Physical Path Details:
1125 
 
1126 10 ale500 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1127 9 ale500 
 
1128 
   Name    Fanout   Delay (ns)          Site               Resource
1129 10 ale500 
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
1130 
ROUTE         1     0.127     R25C10C.Q0 to     R25C10C.A0 textctrl/blink_cnt[3]
1131 
CTOF_DEL    ---     0.099     R25C10C.A0 to     R25C10C.F0 textctrl/SLICE_27
1132 
ROUTE         1     0.000     R25C10C.F0 to    R25C10C.DI0 textctrl/blink_cnt_s[3] (to cpu_clkgen)
1133 9 ale500 
                  --------
1134 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1135 
 
1136 
 Clock Skew Details:
1137 
 
1138 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1139 9 ale500 
 
1140 
   Name    Fanout   Delay (ns)          Site               Resource
1141 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1142 9 ale500 
                  --------
1143 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1144 
 
1145 10 ale500 
      Destination Clock Path clk40_i to textctrl/SLICE_27:
1146 9 ale500 
 
1147 
   Name    Fanout   Delay (ns)          Site               Resource
1148 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1149 9 ale500 
                  --------
1150 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1151 
 
1152 
 
1153 
Passed: The following path meets requirements by 0.370ns
1154 
 
1155 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1156 
 
1157 
   Source:         FF         Q              textctrl/blink_cnt[1]  (from cpu_clkgen +)
1158 
   Destination:    FF         Data in        textctrl/blink_cnt[1]  (to cpu_clkgen +)
1159 
 
1160 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1161 
 
1162 
 Constraint Details:
1163 
 
1164 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1165 
     -0.013ns DIN_HLD and
1166 
      0.000ns delay constraint less
1167 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1168 
 
1169 
 Physical Path Details:
1170 
 
1171 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1172 
 
1173 
   Name    Fanout   Delay (ns)          Site               Resource
1174 10 ale500 
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
1175 
ROUTE         1     0.127     R25C10B.Q0 to     R25C10B.A0 textctrl/blink_cnt[1]
1176 
CTOF_DEL    ---     0.099     R25C10B.A0 to     R25C10B.F0 textctrl/SLICE_28
1177 
ROUTE         1     0.000     R25C10B.F0 to    R25C10B.DI0 textctrl/blink_cnt_s[1] (to cpu_clkgen)
1178 9 ale500 
                  --------
1179 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1180 
 
1181 
 Clock Skew Details:
1182 
 
1183 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1184 
 
1185 
   Name    Fanout   Delay (ns)          Site               Resource
1186 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1187 9 ale500 
                  --------
1188 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1189 
 
1190 
      Destination Clock Path clk40_i to textctrl/SLICE_28:
1191 
 
1192 
   Name    Fanout   Delay (ns)          Site               Resource
1193 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1194 9 ale500 
                  --------
1195 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1196 
 
1197 
 
1198 
Passed: The following path meets requirements by 0.370ns
1199 
 
1200 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1201 
 
1202 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[2]  (from cpu_clkgen +)
1203 
   Destination:    FF         Data in        textctrl/blink_cnt[2]  (to cpu_clkgen +)
1204 9 ale500 
 
1205 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1206 
 
1207 
 Constraint Details:
1208 
 
1209 10 ale500 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1210 9 ale500 
     -0.013ns DIN_HLD and
1211 
      0.000ns delay constraint less
1212 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1213 
 
1214 
 Physical Path Details:
1215 
 
1216 10 ale500 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1217 9 ale500 
 
1218 
   Name    Fanout   Delay (ns)          Site               Resource
1219 10 ale500 
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
1220 
ROUTE         1     0.127     R25C10B.Q1 to     R25C10B.A1 textctrl/blink_cnt[2]
1221 
CTOF_DEL    ---     0.099     R25C10B.A1 to     R25C10B.F1 textctrl/SLICE_28
1222 
ROUTE         1     0.000     R25C10B.F1 to    R25C10B.DI1 textctrl/blink_cnt_s[2] (to cpu_clkgen)
1223 9 ale500 
                  --------
1224 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1225 
 
1226 
 Clock Skew Details:
1227 
 
1228 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1229 9 ale500 
 
1230 
   Name    Fanout   Delay (ns)          Site               Resource
1231 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1232 9 ale500 
                  --------
1233 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1234 
 
1235 10 ale500 
      Destination Clock Path clk40_i to textctrl/SLICE_28:
1236 9 ale500 
 
1237 
   Name    Fanout   Delay (ns)          Site               Resource
1238 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1239 9 ale500 
                  --------
1240 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1241 
 
1242 
 
1243 10 ale500 
Passed: The following path meets requirements by 0.371ns
1244 9 ale500 
 
1245 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1246 
 
1247 10 ale500 
   Source:         FF         Q              textctrl/chars_data[3]  (from cpu_clkgen +)
1248 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to cpu_clkgen +)
1249 9 ale500 
 
1250 10 ale500 
   Delay:               0.476ns  (27.5% logic, 72.5% route), 1 logic levels.
1251 9 ale500 
 
1252 
 Constraint Details:
1253 
 
1254 10 ale500 
      0.476ns physical path delay textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0 meets
1255 
      0.052ns ADDR_HLD and
1256 9 ale500 
      0.000ns delay constraint less
1257 10 ale500 
     -0.053ns skew requirement (totaling 0.105ns) by 0.371ns
1258 9 ale500 
 
1259 
 Physical Path Details:
1260 
 
1261 10 ale500 
      Data path textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0:
1262 9 ale500 
 
1263 
   Name    Fanout   Delay (ns)          Site               Resource
1264 10 ale500 
REG_DEL     ---     0.131    R19C14D.CLK to     R19C14D.Q1 textctrl/SLICE_1231 (from cpu_clkgen)
1265 
ROUTE         4     0.345     R19C14D.Q1 to *R_R20C16.ADA8 textctrl/chars_data[3] (to cpu_clkgen)
1266 9 ale500 
                  --------
1267 10 ale500 
                    0.476   (27.5% logic, 72.5% route), 1 logic levels.
1268 9 ale500 
 
1269 
 Clock Skew Details:
1270 
 
1271 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_1231:
1272 9 ale500 
 
1273 
   Name    Fanout   Delay (ns)          Site               Resource
1274 10 ale500 
ROUTE       367     0.846       27.PADDI to    R19C14D.CLK cpu_clkgen
1275 9 ale500 
                  --------
1276 10 ale500 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1277 9 ale500 
 
1278 10 ale500 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1279 9 ale500 
 
1280 
   Name    Fanout   Delay (ns)          Site               Resource
1281 10 ale500 
ROUTE       367     0.899       27.PADDI to *R_R20C16.CLKA cpu_clkgen
1282 9 ale500 
                  --------
1283 10 ale500 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1284 9 ale500 
 
1285 
 
1286 10 ale500 
Passed: The following path meets requirements by 0.372ns
1287 9 ale500 
 
1288 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1289 
 
1290 10 ale500 
   Source:         FF         Q              textctrl/x_cnt[3]  (from cpu_clkgen +)
1291 
   Destination:    FF         Data in        textctrl/x_cnt[3]  (to cpu_clkgen +)
1292 9 ale500 
 
1293 10 ale500 
   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.
1294 9 ale500 
 
1295 
 Constraint Details:
1296 
 
1297 10 ale500 
      0.359ns physical path delay textctrl/SLICE_13 to textctrl/SLICE_13 meets
1298 
     -0.013ns DIN_HLD and
1299 9 ale500 
      0.000ns delay constraint less
1300 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.372ns
1301 9 ale500 
 
1302 
 Physical Path Details:
1303 
 
1304 10 ale500 
      Data path textctrl/SLICE_13 to textctrl/SLICE_13:
1305 9 ale500 
 
1306 
   Name    Fanout   Delay (ns)          Site               Resource
1307 10 ale500 
REG_DEL     ---     0.131    R22C10C.CLK to     R22C10C.Q0 textctrl/SLICE_13 (from cpu_clkgen)
1308 
ROUTE         3     0.129     R22C10C.Q0 to     R22C10C.A0 textctrl/x_cnt[3]
1309 
CTOF_DEL    ---     0.099     R22C10C.A0 to     R22C10C.F0 textctrl/SLICE_13
1310 
ROUTE         1     0.000     R22C10C.F0 to    R22C10C.DI0 textctrl/x_cnt_s[3] (to cpu_clkgen)
1311 9 ale500 
                  --------
1312 10 ale500 
                    0.359   (64.1% logic, 35.9% route), 2 logic levels.
1313 9 ale500 
 
1314 
 Clock Skew Details:
1315 
 
1316 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_13:
1317 9 ale500 
 
1318 
   Name    Fanout   Delay (ns)          Site               Resource
1319 10 ale500 
ROUTE       367     0.828       27.PADDI to    R22C10C.CLK cpu_clkgen
1320 9 ale500 
                  --------
1321 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1322 9 ale500 
 
1323 10 ale500 
      Destination Clock Path clk40_i to textctrl/SLICE_13:
1324 9 ale500 
 
1325 
   Name    Fanout   Delay (ns)          Site               Resource
1326 10 ale500 
ROUTE       367     0.828       27.PADDI to    R22C10C.CLK cpu_clkgen
1327 9 ale500 
                  --------
1328 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1329 9 ale500 
 
1330 
Report Summary
1331 
--------------
1332 
----------------------------------------------------------------------------
1333 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1334 
----------------------------------------------------------------------------
1335 
                                        |             |             |
1336 
FREQUENCY NET "cpu_clkgen" 40.000000    |             |             |
1337 
MHz ;                                   |            -|            -|   1
1338 
                                        |             |             |
1339 
----------------------------------------------------------------------------
1340 
 
1341 
 
1342 
All preferences were met.
1343 
 
1344 
 
1345 
Clock Domains Analysis
1346 
------------------------
1347 
 
1348 
Found 1 clocks:
1349 
 
1350 10 ale500 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
1351 9 ale500 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
1352 
 
1353 
 
1354 
Timing summary (Hold):
1355 
---------------
1356 
 
1357 
Timing errors: 0  Score: 0
1358 
Cumulative negative slack: 0
1359 
 
1360 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
1361 9 ale500 
 
1362 
 
1363 
 
1364 
Timing summary (Setup and Hold):
1365 
---------------
1366 
 
1367 
Timing errors: 0 (setup), 0 (hold)
1368 
Score: 0 (setup), 0 (hold)
1369 
Cumulative negative slack: 0 (0+0)
1370 
--------------------------------------------------------------------------------
1371 
 
1372 
--------------------------------------------------------------------------------
1373 
 

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