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<HTML>
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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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</HEAD>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file P6809_P6809_map.ncd.
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Design name: CC3_top
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NCD version: 3.2
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Vendor: LATTICE
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Device: LCMXO2-7000HE
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Package: TQFP144
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Performance: 4
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Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
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Package Status: Final Version 1.36
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Performance Hardware Data Status: Final) Version 23.4
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
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Thu Feb 6 15:35:22 2014
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
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Design file: P6809_P6809_map.ncd
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Preference file: P6809_P6809.prf
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Device,speed: LCMXO2-7000HE,4
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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<FONT COLOR=red><LI><A href='#map_twr_pref_0_0' Target='right'><FONT COLOR=red>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (198 errors)</FONT></A></LI>
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</FONT> 4096 items scored, 198 timing errors detected.
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Warning: 39.118MHz is the maximum frequency for this preference.
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
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4096 items scored, 198 timing errors detected.
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--------------------------------------------------------------------------------
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Error: The following path exceeds requirements by 0.564ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q cpu0/alu/rb_in[0] (from cpu_clkgen +)
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Destination: FF Data in cpu0/regs/SU[15] (to cpu_clkgen +)
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Constraint Details:
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25.000ns delay constraint less
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0.166ns DIN_SET requirement (totaling 24.834ns) by 0.564ns
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Physical Path Details:
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Data path cpu0/alu/SLICE_215 to cpu0/regs/SLICE_55:
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.452 *SLICE_215.CLK to */SLICE_215.Q0 cpu0/alu/SLICE_215 (from cpu_clkgen)
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ROUTE 24 e 1.234 */SLICE_215.Q0 to */SLICE_199.A1 cpu0/alu/rb_in[0]
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CTOF_DEL --- 0.495 */SLICE_199.A1 to */SLICE_199.F1 cpu0/alu/alu16/SLICE_199
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ROUTE 1 e 1.234 */SLICE_199.F1 to *6/SLICE_99.A1 cpu0/alu/alu16/a16/rb_in_i[0]
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C1TOFCO_DE --- 0.889 *6/SLICE_99.A1 to */SLICE_99.FCO cpu0/alu/alu16/a16/SLICE_99
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ROUTE 1 e 0.001 */SLICE_99.FCO to */SLICE_98.FCI cpu0/alu/alu16/a16/un8_q_out_cry_0
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FCITOF0_DE --- 0.585 */SLICE_98.FCI to *6/SLICE_98.F0 cpu0/alu/alu16/a16/SLICE_98
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ROUTE 1 e 1.234 *6/SLICE_98.F0 to *SLICE_1214.A0 cpu0/alu/alu16/a16/un8_q_out[1]
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CTOF_DEL --- 0.495 *SLICE_1214.A0 to *SLICE_1214.F0 cpu0/alu/SLICE_1214
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ROUTE 1 e 1.234 *SLICE_1214.F0 to */SLICE_116.C0 cpu0/alu/alu16/a16/q_out_2_cry_1_0_RNO
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C0TOFCO_DE --- 1.023 */SLICE_116.C0 to *SLICE_116.FCO cpu0/alu/alu16/a16/SLICE_116
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ROUTE 1 e 0.001 *SLICE_116.FCO to *SLICE_115.FCI cpu0/alu/alu16/a16/q_out_2_cry_2
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FCITOFCO_D --- 0.162 *SLICE_115.FCI to *SLICE_115.FCO cpu0/alu/alu16/a16/SLICE_115
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FCITOFCO_D --- 0.162 *SLICE_114.FCI to *SLICE_114.FCO cpu0/alu/alu16/a16/SLICE_114
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ROUTE 1 e 0.001 *SLICE_114.FCO to *SLICE_113.FCI cpu0/alu/alu16/a16/q_out_2_cry_6
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FCITOFCO_D --- 0.162 *SLICE_113.FCI to *SLICE_113.FCO cpu0/alu/alu16/a16/SLICE_113
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ROUTE 1 e 0.001 *SLICE_113.FCO to *SLICE_112.FCI cpu0/alu/alu16/a16/q_out_2_cry_8
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FCITOFCO_D --- 0.162 *SLICE_112.FCI to *SLICE_112.FCO cpu0/alu/alu16/a16/SLICE_112
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ROUTE 1 e 0.001 *SLICE_112.FCO to *SLICE_111.FCI cpu0/alu/alu16/a16/q_out_2_cry_10
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FCITOF1_DE --- 0.643 *SLICE_111.FCI to */SLICE_111.F1 cpu0/alu/alu16/a16/SLICE_111
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ROUTE 1 e 1.234 */SLICE_111.F1 to *SLICE_1048.B0 cpu0/alu/alu16/a16/N_2375
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CTOF_DEL --- 0.495 *SLICE_1048.B0 to *SLICE_1048.F0 cpu0/alu/alu16/SLICE_1048
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ROUTE 1 e 0.480 *SLICE_1048.F0 to *SLICE_1048.A1 cpu0/alu/alu16/arith_q[12]
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CTOF_DEL --- 0.495 *SLICE_1048.A1 to *SLICE_1048.F1 cpu0/alu/alu16/SLICE_1048
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CTOF_DEL --- 0.495 *SLICE_1066.A1 to *SLICE_1066.F1 cpu0/alu/alu16/SLICE_1066
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ROUTE 2 e 1.234 *SLICE_1066.F1 to *SLICE_1082.B0 cpu0/alu/q16_out[12]
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CTOF_DEL --- 0.495 *SLICE_1082.B0 to *SLICE_1082.F0 cpu0/alu/SLICE_1082
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CTOF_DEL --- 0.495 */SLICE_363.A0 to */SLICE_363.F0 cpu0/regs/SLICE_363
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ROUTE 6 e 1.234 */SLICE_363.F0 to *SLICE_1193.B0 cpu0/regs/left_1[12]
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CTOF_DEL --- 0.495 *SLICE_1193.B0 to *SLICE_1193.F0 cpu0/regs/SLICE_1193
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ROUTE 1 e 1.234 *SLICE_1193.F0 to */SLICE_951.A1 cpu0/regs/N_291
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CTOF_DEL --- 0.495 */SLICE_951.A1 to */SLICE_951.F1 cpu0/regs/SLICE_951
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CTOF_DEL --- 0.495 */SLICE_951.B0 to */SLICE_951.F0 cpu0/regs/SLICE_951
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ROUTE 1 e 1.234 */SLICE_951.F0 to *s/SLICE_56.C0 cpu0/regs/SU_219_i1_mux
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C0TOFCO_DE --- 1.023 *s/SLICE_56.C0 to */SLICE_56.FCO cpu0/regs/SLICE_56
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ROUTE 1 e 0.001 */SLICE_56.FCO to */SLICE_55.FCI cpu0/regs/SU_cry[13]
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FCITOF1_DE --- 0.643 */SLICE_55.FCI to *s/SLICE_55.F1 cpu0/regs/SLICE_55
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ROUTE 1 e 0.001 *s/SLICE_55.F1 to */SLICE_55.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
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--------
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25.398 (42.7% logic, 57.3% route), 21 logic levels.
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Warning: 39.118MHz is the maximum frequency for this preference.
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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FREQUENCY NET "cpu_clkgen" 40.000000 | | |
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1 preference(marked by "*" above) not met.
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----------------------------------------------------------------------------
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cpu0/alu/alu16/a16/q_out_2_cry_10 | 1| 178| 89.90%
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149 |
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150 |
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cpu0/alu/alu16/arith_q[12] | 1| 178| 89.90%
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cpu0/alu/alu16/a16/N_2375 | 1| 178| 89.90%
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154 |
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cpu0/datamux_o_dest[12] | 2| 178| 89.90%
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cpu0/regs/left_1[12] | 6| 178| 89.90%
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cpu0/alu/alu16/a16/q_out_2_cry_8 | 1| 124| 62.63%
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160 |
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cpu0/alu/alu16/a16/un8_q_out_cry_4 | 1| 122| 61.62%
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cpu0/alu/alu16/a16/un8_q_out_cry_2 | 1| 106| 53.54%
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164 |
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cpu0/alu/alu16/a16/un8_q_out_cry_6 | 1| 104| 52.53%
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165 |
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166 |
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cpu0/regs/SS_cry[13] | 1| 99| 50.00%
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167 |
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168 |
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cpu0/regs/SU_cry[13] | 1| 99| 50.00%
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169 |
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170 |
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cpu0/regs/N_255 | 1| 89| 44.95%
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cpu0/regs/N_291 | 1| 89| 44.95%
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cpu0/regs/SS_235_i1_mux | 1| 89| 44.95%
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175 |
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176 |
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cpu0/regs/SS_16[12] | 1| 89| 44.95%
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177 |
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178 |
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cpu0/regs/SU_219_i1_mux | 1| 89| 44.95%
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179 |
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180 |
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cpu0/regs/SU_16[12] | 1| 89| 44.95%
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181 |
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182 |
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cpu0/alu/alu16/a16/q_out_2_cry_6 | 1| 78| 39.39%
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184 |
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cpu0/alu/alu16/a16/rb_in_i[0] | 1| 58| 29.29%
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185 |
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186 |
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cpu0/alu/alu16/a16/un8_q_out_cry_0 | 1| 58| 29.29%
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187 |
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188 |
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cpu0/alu/rb_in[0] | 24| 58| 29.29%
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189 |
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190 |
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cpu0/regs/SS_s[15] | 1| 55| 27.78%
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191 |
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192 |
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cpu0/regs/SU_s[15] | 1| 55| 27.78%
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193 |
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194 |
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cpu0/alu/alu16/a16/un8_q_out_cry_8 | 1| 54| 27.27%
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195 |
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196 |
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cpu0/alu/alu16/a16/q_out_2_cry_4 | 1| 46| 23.23%
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197 |
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198 |
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cpu0/regs/SS_s[14] | 1| 44| 22.22%
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199 |
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200 |
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cpu0/regs/SU_s[14] | 1| 44| 22.22%
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201 |
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202 |
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cpu0/alu/alu16/a16/rb_in_i[1] | 1| 34| 17.17%
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203 |
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cpu0/alu/rb_in[1] | 24| 34| 17.17%
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cpu0/alu/alu16/a16/rb_in_i[2] | 1| 32| 16.16%
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cpu0/alu/rb_in[2] | 21| 32| 16.16%
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cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO | 1| 30| 15.15%
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211 |
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212 |
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cpu0/alu/alu16/a16/un8_q_out[9] | 1| 30| 15.15%
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213 |
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214 |
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cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO | 1| 28| 14.14%
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215 |
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216 |
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cpu0/alu/alu16/a16/un8_q_out[7] | 1| 28| 14.14%
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217 |
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218 |
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cpu0/alu/alu16/a16/rb_in_i[4] | 1| 24| 12.12%
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219 |
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220 |
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221 |
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222 |
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cpu0/alu/alu16/a16/q_out_2_cry_9_0_RNO_0| 1| 24| 12.12%
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223 |
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224 |
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cpu0/alu/alu16/a16/un8_q_out[10] | 1| 24| 12.12%
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225 |
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226 |
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cpu0/alu/alu16/a16/q_out_2_cry_7_0_RNO_0| 1| 24| 12.12%
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227 |
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228 |
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cpu0/alu/alu16/a16/un8_q_out[8] | 1| 24| 12.12%
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229 |
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230 |
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cpu0/alu/rb_in[4] | 21| 24| 12.12%
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231 |
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232 |
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cpu0/alu/rb_in[3] | 22| 24| 12.12%
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233 |
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|
234 |
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cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO | 1| 22| 11.11%
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235 |
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236 |
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cpu0/alu/alu16/a16/un8_q_out[5] | 1| 22| 11.11%
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237 |
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|
238 |
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cpu0/alu/alu16/a16/q_out_2_cry_5_0_RNO_0| 1| 20| 10.10%
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239 |
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|
240 |
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cpu0/alu/alu16/a16/un8_q_out[6] | 1| 20| 10.10%
|
241 |
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|
242 |
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cpu0/alu/alu16/a16/q_out_2_cry_3_0_RNO | 1| 20| 10.10%
|
243 |
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244 |
9 |
ale500 |
cpu0/alu/alu16/a16/un8_q_out[3] | 1| 20| 10.10%
|
245 |
10 |
ale500 |
| | |
|
246 |
9 |
ale500 |
----------------------------------------------------------------------------
|
247 |
10 |
ale500 |
|
248 |
9 |
ale500 |
|
249 |
10 |
ale500 |
<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
250 |
9 |
ale500 |
------------------------
|
251 |
10 |
ale500 |
|
252 |
9 |
ale500 |
Found 1 clocks:
|
253 |
10 |
ale500 |
|
254 |
9 |
ale500 |
Clock Domain: cpu_clkgen Source: clk40_i.PAD Loads: 367
|
255 |
10 |
ale500 |
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
256 |
9 |
ale500 |
|
257 |
10 |
ale500 |
|
258 |
9 |
ale500 |
<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
|
259 |
10 |
ale500 |
---------------
|
260 |
9 |
ale500 |
|
261 |
10 |
ale500 |
Timing errors: 198 Score: 60114
|
262 |
9 |
ale500 |
Cumulative negative slack: 60114
|
263 |
10 |
ale500 |
|
264 |
9 |
ale500 |
Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)
|
265 |
10 |
ale500 |
|
266 |
9 |
ale500 |
--------------------------------------------------------------------------------
|
267 |
10 |
ale500 |
<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
|
268 |
9 |
ale500 |
Thu Feb 6 15:35:22 2014
|
269 |
10 |
ale500 |
|
270 |
9 |
ale500 |
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
271 |
10 |
ale500 |
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
272 |
9 |
ale500 |
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
273 |
10 |
ale500 |
Copyright (c) 2001 Agere Systems All rights reserved.
|
274 |
9 |
ale500 |
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
|
275 |
10 |
ale500 |
|
276 |
9 |
ale500 |
<A name="mtw1_hold_ri"></A><B><U><big>Report Information</big></U></B>
|
277 |
10 |
ale500 |
------------------
|
278 |
9 |
ale500 |
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
|
279 |
10 |
ale500 |
Design file: P6809_P6809_map.ncd
|
280 |
9 |
ale500 |
Preference file: P6809_P6809.prf
|
281 |
10 |
ale500 |
Device,speed: LCMXO2-7000HE,M
|
282 |
9 |
ale500 |
Report level: verbose report, limited to 1 item per preference
|
283 |
10 |
ale500 |
--------------------------------------------------------------------------------
|
284 |
9 |
ale500 |
|
285 |
10 |
ale500 |
<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
|
286 |
9 |
ale500 |
|
287 |
10 |
ale500 |
<LI><A href='#map_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI> 4096 items scored, 0 timing errors detected.
|
288 |
9 |
ale500 |
|
289 |
10 |
ale500 |
BLOCK ASYNCPATHS
|
290 |
9 |
ale500 |
BLOCK RESETPATHS
|
291 |
10 |
ale500 |
--------------------------------------------------------------------------------
|
292 |
9 |
ale500 |
|
293 |
10 |
ale500 |
|
294 |
9 |
ale500 |
|
295 |
10 |
ale500 |
================================================================================
|
296 |
9 |
ale500 |
<A name="map_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
297 |
10 |
ale500 |
4096 items scored, 0 timing errors detected.
|
298 |
9 |
ale500 |
--------------------------------------------------------------------------------
|
299 |
10 |
ale500 |
|
300 |
9 |
ale500 |
|
301 |
10 |
ale500 |
Passed: The following path meets requirements by 0.386ns
|
302 |
9 |
ale500 |
|
303 |
10 |
ale500 |
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
|
304 |
9 |
ale500 |
|
305 |
10 |
ale500 |
Source: FF Q reset_cnt[0] (from cpu_clkgen +)
|
306 |
9 |
ale500 |
Destination: FF Data in reset_cnt[0] (to cpu_clkgen +)
|
307 |
10 |
ale500 |
|
308 |
9 |
ale500 |
Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.
|
309 |
10 |
ale500 |
|
310 |
9 |
ale500 |
Constraint Details:
|
311 |
10 |
ale500 |
|
312 |
9 |
ale500 |
0.330ns physical path delay SLICE_444 to SLICE_444 meets
|
313 |
10 |
ale500 |
-0.056ns LSR_HLD and
|
314 |
9 |
ale500 |
0.000ns delay constraint requirement (totaling -0.056ns) by 0.386ns
|
315 |
10 |
ale500 |
|
316 |
9 |
ale500 |
Physical Path Details:
|
317 |
10 |
ale500 |
|
318 |
9 |
ale500 |
Data path SLICE_444 to SLICE_444:
|
319 |
10 |
ale500 |
|
320 |
9 |
ale500 |
Name Fanout Delay (ns) Site Resource
|
321 |
10 |
ale500 |
REG_DEL --- 0.131 SLICE_444.CLK to SLICE_444.Q0 SLICE_444 (from cpu_clkgen)
|
322 |
9 |
ale500 |
ROUTE 5 e 0.199 SLICE_444.Q0 to SLICE_444.LSR reset_cnt[0] (to cpu_clkgen)
|
323 |
10 |
ale500 |
--------
|
324 |
9 |
ale500 |
0.330 (39.7% logic, 60.3% route), 1 logic levels.
|
325 |
10 |
ale500 |
|
326 |
|
|
<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
|
327 |
|
|
--------------
|
328 |
|
|
----------------------------------------------------------------------------
|
329 |
9 |
ale500 |
Preference(MIN Delays) | Constraint| Actual|Levels
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
FREQUENCY NET "cpu_clkgen" 40.000000 | | |
|
333 |
|
|
MHz ; | -| -| 1
|
334 |
|
|
|
335 |
|
|
----------------------------------------------------------------------------
|
336 |
|
|
|
337 |
10 |
ale500 |
|
338 |
9 |
ale500 |
All preferences were met.
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
<A name="mtw1_hold_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
|
342 |
|
|
------------------------
|
343 |
|
|
|
344 |
10 |
ale500 |
Found 1 clocks:
|
345 |
|
|
|
346 |
9 |
ale500 |
|
347 |
10 |
ale500 |
Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
|
348 |
9 |
ale500 |
|
349 |
|
|
|
350 |
|
|
<A name="mtw1_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
|
351 |
10 |
ale500 |
---------------
|
352 |
9 |
ale500 |
|
353 |
|
|
Timing errors: 0 Score: 0
|
354 |
|
|
Cumulative negative slack: 0
|
355 |
|
|
|
356 |
|
|
Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
|
360 |
|
|
<A name="mtw1_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
|
361 |
|
|
---------------
|
362 |
|
|
|
363 |
|
|
Timing errors: 198 (setup), 0 (hold)
|
364 |
|
|
Score: 60114 (setup), 0 (hold)
|
365 |
|
|
Cumulative negative slack: 60114 (60114+0)
|
366 |
|
|
--------------------------------------------------------------------------------
|
367 |
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