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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [P6809_P6809_twr.html] - Blame information for rev 10

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1 9 ale500 
<HTML>
2 
<HEAD><TITLE>Lattice TRACE Report</TITLE>
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9 
<PRE><A name="Par_Twr"></A><B><U><big>Place & Route TRACE Report</big></U></B>
10 
 
11 
Loading design for application trce from file P6809_P6809.ncd.
12 
Design name: CC3_top
13 
NCD version: 3.2
14 
Vendor:      LATTICE
15 
Device:      LCMXO2-7000HE
16 
Package:     TQFP144
17 
Performance: 4
18 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
19 
Package Status:                     Final          Version 1.36
20 
Performance Hardware Data Status:   Final)         Version 23.4
21 
Setup and Hold Report
22 
 
23 
--------------------------------------------------------------------------------
24 
<A name="Par_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101</big></U></B>
25 
Thu Feb  6 15:36:11 2014
26 
 
27 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
28 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
29 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
30 
Copyright (c) 2001 Agere Systems   All rights reserved.
31 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
32 
 
33 
<A name="ptwr_set_ri"></A><B><U><big>Report Information</big></U></B>
34 
------------------
35 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
36 
Design file:     P6809_P6809.ncd
37 
Preference file: P6809_P6809.prf
38 
Device,speed:    LCMXO2-7000HE,4
39 
Report level:    verbose report, limited to 10 items per preference
40 
--------------------------------------------------------------------------------
41 
 
42 
<A name="ptwr_set_ps"></A><B><U><big>Preference Summary</big></U></B>
43 
 
44 
<LI><A href='#par_twr_pref_0_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
45 
Report:   40.406MHz is the maximum frequency for this preference.
46 
 
47 
BLOCK ASYNCPATHS
48 
BLOCK RESETPATHS
49 
--------------------------------------------------------------------------------
50 
 
51 
 
52 
 
53 
================================================================================
54 
<A name="par_twr_pref_0_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
55 
            4096 items scored, 0 timing errors detected.
56 
--------------------------------------------------------------------------------
57 
 
58 
 
59 
Passed: The following path meets requirements by 0.251ns
60 
 
61 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
62 
 
63 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
64 
   Destination:    FF         Data in        cpu0/regs/SU[15]  (to cpu_clkgen +)
65 
 
66 
   Delay:              24.583ns  (36.2% logic, 63.8% route), 18 logic levels.
67 
 
68 
 Constraint Details:
69 
 
70 
     24.583ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
71 
 
72 
      0.000ns skew and
73 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.251ns
74 
 
75 
 Physical Path Details:
76 
 
77 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
78 
 
79 
   Name    Fanout   Delay (ns)          Site               Resource
80 
REG_DEL     ---     0.452    R18C14A.CLK to     R18C14A.Q0 SLICE_260 (from cpu_clkgen)
81 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
82 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
83 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
84 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
85 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
86 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
87 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
88 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
89 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
90 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
91 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
92 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
93 
 
94 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
95 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
96 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
97 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
98 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
99 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
100 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
101 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
102 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
103 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
104 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
105 
 
106 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
107 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
108 10 ale500 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
109 9 ale500 
 
110 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
111 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
112 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
113 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
114 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
115 
 
116 
                  --------
117 
                   24.583   (36.2% logic, 63.8% route), 18 logic levels.
118 
 
119 
 Clock Skew Details:
120 
 
121 
      Source Clock Path clk40_i to SLICE_260:
122 
 
123 
   Name    Fanout   Delay (ns)          Site               Resource
124 
 
125 
                  --------
126 
 
127 
 
128 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
129 9 ale500 
 
130 
   Name    Fanout   Delay (ns)          Site               Resource
131 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
132 
                  --------
133 
 
134 
 
135 
 
136 
Passed: The following path meets requirements by 0.309ns
137 
 
138 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
139 
 
140 
 
141 
 
142 10 ale500 
 
143 9 ale500 
 
144 
 
145 
 
146 10 ale500 
 
147 9 ale500 
     24.525ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
148 
 
149 10 ale500 
      0.000ns skew and
150 9 ale500 
 
151 
 
152 
 
153 10 ale500 
 
154 9 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
155 
 
156 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
157 9 ale500 
 
158 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
159 
 
160 10 ale500 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
161 9 ale500 
 
162 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
163 10 ale500 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
164 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
165 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
166 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
167 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
168 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
169 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
170 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
171 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
172 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
173 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
174 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
175 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
176 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
177 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
178 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
179 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
180 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
181 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
182 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
183 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
184 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
185 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
186 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
187 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
188 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
189 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
190 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
191 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
192 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
193 
                  --------
194 
                   24.525   (36.0% logic, 64.0% route), 18 logic levels.
195 
 
196 
 Clock Skew Details:
197 
 
198 
      Source Clock Path clk40_i to SLICE_260:
199 9 ale500 
 
200 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
201 9 ale500 
 
202 
                  --------
203 
 
204 10 ale500 
 
205 9 ale500 
 
206 
 
207 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
208 9 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
209 
                  --------
210 
 
211 10 ale500 
 
212 9 ale500 
 
213 
Passed: The following path meets requirements by 0.324ns
214 10 ale500 
 
215 9 ale500 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
216 
 
217 
 
218 
 
219 10 ale500 
 
220 9 ale500 
 
221 
 
222 
 
223 10 ale500 
 
224 
     24.510ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
225 9 ale500 
 
226 10 ale500 
      0.000ns skew and
227 9 ale500 
 
228 
 
229 
 
230 10 ale500 
 
231 9 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
232 
 
233 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
234 9 ale500 
 
235 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
236 
 
237 10 ale500 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
238 9 ale500 
 
239 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
240 10 ale500 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
241 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
242 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
243 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
244 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
245 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
246 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
247 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
248 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
249 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
250 
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
251 
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
252 
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
253 
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
254 
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
255 
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
256 
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
257 
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
258 
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
259 
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
260 
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
261 
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
262 
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
263 
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
264 
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
265 
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
266 
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
267 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
268 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
269 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
270 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
271 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
272 
                  --------
273 
                   24.510   (36.1% logic, 63.9% route), 19 logic levels.
274 
 
275 
 Clock Skew Details:
276 9 ale500 
 
277 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
278 9 ale500 
 
279 
   Name    Fanout   Delay (ns)          Site               Resource
280 
 
281 10 ale500 
                  --------
282 9 ale500 
 
283 
 
284 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
285 9 ale500 
 
286 
   Name    Fanout   Delay (ns)          Site               Resource
287 
 
288 10 ale500 
                  --------
289 9 ale500 
 
290 
 
291 10 ale500 
 
292 9 ale500 
Passed: The following path meets requirements by 0.351ns
293 
 
294 
 
295 
 
296 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
297 9 ale500 
 
298 
 
299 
 
300 10 ale500 
 
301 
 Constraint Details:
302 9 ale500 
 
303 10 ale500 
     24.483ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
304 9 ale500 
 
305 
      0.000ns skew and
306 
 
307 10 ale500 
 
308 9 ale500 
 Physical Path Details:
309 
 
310 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
311 9 ale500 
 
312 
   Name    Fanout   Delay (ns)          Site               Resource
313 
 
314 10 ale500 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
315 9 ale500 
 
316 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
317 10 ale500 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
318 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
319 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
320 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
321 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
322 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
323 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
324 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
325 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
326 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
327 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
328 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
329 
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
330 
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
331 
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
332 
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
333 
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
334 
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
335 
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
336 
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
337 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
338 
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
339 
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
340 
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
341 
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
342 
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
343 
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
344 
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
345 
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
346 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
347 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
348 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
349 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
350 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
351 
                  --------
352 
                   24.483   (36.2% logic, 63.8% route), 19 logic levels.
353 
 
354 
 Clock Skew Details:
355 9 ale500 
 
356 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
357 9 ale500 
 
358 
   Name    Fanout   Delay (ns)          Site               Resource
359 
 
360 10 ale500 
                  --------
361 9 ale500 
 
362 
 
363 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
364 9 ale500 
 
365 
   Name    Fanout   Delay (ns)          Site               Resource
366 
 
367 10 ale500 
                  --------
368 9 ale500 
 
369 
 
370 10 ale500 
 
371 9 ale500 
Passed: The following path meets requirements by 0.362ns
372 
 
373 
 
374 
 
375 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[1]  (from cpu_clkgen +)
376 9 ale500 
 
377 
 
378 
 
379 10 ale500 
 
380 
 Constraint Details:
381 9 ale500 
 
382 10 ale500 
     24.472ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
383 9 ale500 
 
384 
      0.000ns skew and
385 
 
386 10 ale500 
 
387 9 ale500 
 Physical Path Details:
388 
 
389 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
390 9 ale500 
 
391 
   Name    Fanout   Delay (ns)          Site               Resource
392 
 
393 10 ale500 
ROUTE        30     1.613     R18C14A.Q1 to     R18C24D.D1 cpu0/k_ind_ea[1]
394 9 ale500 
 
395 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
396 10 ale500 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
397 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
398 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
399 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
400 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
401 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
402 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
403 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
404 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
405 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
406 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
407 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
408 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
409 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
410 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
411 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
412 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
413 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
414 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
415 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
416 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
417 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
418 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
419 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
420 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
421 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
422 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
423 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
424 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
425 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
426 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
427 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
428 
                  --------
429 
                   24.472   (36.3% logic, 63.7% route), 18 logic levels.
430 
 
431 
 Clock Skew Details:
432 
 
433 
      Source Clock Path clk40_i to SLICE_260:
434 9 ale500 
 
435 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
436 9 ale500 
 
437 
                  --------
438 
 
439 10 ale500 
 
440 9 ale500 
 
441 
 
442 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
443 9 ale500 
ROUTE       367     2.399       27.PADDI to    R11C24A.CLK cpu_clkgen
444 
                  --------
445 
 
446 10 ale500 
 
447 9 ale500 
 
448 
Passed: The following path meets requirements by 0.382ns
449 10 ale500 
 
450 9 ale500 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
451 
 
452 
 
453 
 
454 10 ale500 
 
455 9 ale500 
 
456 
 
457 
 
458 10 ale500 
 
459 9 ale500 
     24.452ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
460 
 
461 10 ale500 
      0.000ns skew and
462 9 ale500 
 
463 
 
464 
 
465 10 ale500 
 
466 9 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
467 
 
468 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
469 9 ale500 
 
470 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
471 
 
472 10 ale500 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
473 9 ale500 
 
474 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
475 10 ale500 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
476 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
477 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
478 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
479 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
480 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
481 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
482 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
483 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
484 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
485 
FCITOFCO_D  ---     0.162    R19C19B.FCI to    R19C19B.FCO cpu0/regs/ea/SLICE_40
486 
ROUTE         1     0.000    R19C19B.FCO to    R19C19C.FCI cpu0/regs/ea/eamem_addr_o_cry_10
487 
FCITOF0_DE  ---     0.585    R19C19C.FCI to     R19C19C.F0 cpu0/regs/ea/SLICE_39
488 
ROUTE         4     2.187     R19C19C.F0 to     R16C33D.D0 cpu0/regs_o_eamem_addr[11]
489 
CTOF_DEL    ---     0.495     R16C33D.D0 to     R16C33D.F0 cpu0/regs/SLICE_1180
490 
ROUTE         1     1.004     R16C33D.F0 to     R16C33B.B0 cpu0/regs/ea/N_1415
491 
CTOF_DEL    ---     0.495     R16C33B.B0 to     R16C33B.F0 cpu0/SLICE_901
492 
ROUTE         2     2.179     R16C33B.F0 to     R12C24A.D1 cpu0/datamux_o_dest[11]
493 
CTOF_DEL    ---     0.495     R12C24A.D1 to     R12C24A.F1 cpu0/regs/SLICE_362
494 
ROUTE         6     0.790     R12C24A.F1 to     R12C26C.C0 cpu0/regs/left_1[11]
495 
CTOF_DEL    ---     0.495     R12C26C.C0 to     R12C26C.F0 cpu0/regs/SLICE_1192
496 
ROUTE         1     0.315     R12C26C.F0 to     R12C26A.D1 cpu0/regs/N_290
497 
CTOF_DEL    ---     0.495     R12C26A.D1 to     R12C26A.F1 cpu0/regs/SLICE_950
498 
ROUTE         1     0.626     R12C26A.F1 to     R12C26A.D0 cpu0/regs/SU_16[11]
499 
CTOF_DEL    ---     0.495     R12C26A.D0 to     R12C26A.F0 cpu0/regs/SLICE_950
500 
ROUTE         1     1.506     R12C26A.F0 to     R11C23C.C1 cpu0/regs/SU_218_i1_mux
501 
C1TOFCO_DE  ---     0.889     R11C23C.C1 to    R11C23C.FCO cpu0/regs/SLICE_57
502 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
503 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
504 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
505 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
506 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
507 
                  --------
508 
                   24.452   (36.0% logic, 64.0% route), 19 logic levels.
509 
 
510 
 Clock Skew Details:
511 9 ale500 
 
512 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
513 9 ale500 
 
514 
   Name    Fanout   Delay (ns)          Site               Resource
515 
 
516 10 ale500 
                  --------
517 9 ale500 
 
518 
 
519 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
520 9 ale500 
 
521 
   Name    Fanout   Delay (ns)          Site               Resource
522 
 
523 10 ale500 
                  --------
524 9 ale500 
 
525 
 
526 10 ale500 
 
527 9 ale500 
Passed: The following path meets requirements by 0.391ns
528 
 
529 
 
530 
 
531 10 ale500 
   Source:         FF         Q              cpu0/regs/IY_pipe_14  (from cpu_clkgen +)
532 9 ale500 
 
533 
 
534 
 
535 10 ale500 
 
536 9 ale500 
 Constraint Details:
537 
 
538 10 ale500 
     24.443ns physical path delay cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55 meets
539 9 ale500 
 
540 
      0.000ns skew and
541 
 
542 10 ale500 
 
543 9 ale500 
 Physical Path Details:
544 
 
545 10 ale500 
      Data path cpu0/regs/SLICE_323 to cpu0/regs/SLICE_55:
546 9 ale500 
 
547 
   Name    Fanout   Delay (ns)          Site               Resource
548 
 
549 10 ale500 
ROUTE        16     1.390     R16C22A.Q0 to     R16C25A.A1 cpu0/regs/IY_1_sqmuxaf
550 9 ale500 
 
551 
ROUTE         1     0.693     R16C25A.F1 to     R16C25A.B0 cpu0/regs/N_665
552 10 ale500 
CTOF_DEL    ---     0.495     R16C25A.B0 to     R16C25A.F0 cpu0/regs/SLICE_1012
553 
ROUTE         3     1.435     R16C25A.F0 to     R21C25B.C1 cpu0/regs/IY[0]
554 
CTOOFX_DEL  ---     0.721     R21C25B.C1 to   R21C25B.OFX0 cpu0/regs/ea/ea_reg_3[0]/SLICE_511
555 
ROUTE         5     1.487   R21C25B.OFX0 to     R21C19D.D0 cpu0/regs/ea_reg[0]
556 
CTOF_DEL    ---     0.495     R21C19D.D0 to     R21C19D.F0 cpu0/regs/SLICE_917
557 
ROUTE         2     1.152     R21C19D.F0 to     R19C18A.C1 cpu0/regs/ea/N_72
558 
C1TOFCO_DE  ---     0.889     R19C18A.C1 to    R19C18A.FCO cpu0/regs/ea/SLICE_45
559 
ROUTE         1     0.000    R19C18A.FCO to    R19C18B.FCI cpu0/regs/ea/eamem_addr_o_cry_0
560 
FCITOFCO_D  ---     0.162    R19C18B.FCI to    R19C18B.FCO cpu0/regs/ea/SLICE_44
561 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
562 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
563 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
564 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
565 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
566 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
567 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
568 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
569 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
570 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
571 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
572 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
573 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
574 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
575 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
576 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
577 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
578 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
579 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
580 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
581 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
582 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
583 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
584 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
585 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
586 
FCITOF1_DE  ---     0.643    R11C24A.FCI to     R11C24A.F1 cpu0/regs/SLICE_55
587 
ROUTE         1     0.000     R11C24A.F1 to    R11C24A.DI1 cpu0/regs/SU_s[15] (to cpu_clkgen)
588 
                  --------
589 
                   24.443   (39.4% logic, 60.6% route), 20 logic levels.
590 9 ale500 
 
591 10 ale500 
 Clock Skew Details:
592 9 ale500 
 
593 
      Source Clock Path clk40_i to cpu0/regs/SLICE_323:
594 
 
595 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
596 9 ale500 
 
597 
                  --------
598 10 ale500 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
599 9 ale500 
 
600 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
601 
 
602 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
603 9 ale500 
 
604 
                  --------
605 10 ale500 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
606 9 ale500 
 
607 
 
608 
 
609 
 
610 10 ale500 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
611 9 ale500 
 
612 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
613 
 
614 10 ale500 
 
615 
   Delay:              24.438ns  (36.4% logic, 63.6% route), 18 logic levels.
616 9 ale500 
 
617 10 ale500 
 Constraint Details:
618 9 ale500 
 
619 
     24.438ns physical path delay SLICE_260 to cpu0/regs/SLICE_64 meets
620 
 
621 10 ale500 
      0.000ns skew and
622 9 ale500 
      0.166ns DIN_SET requirement (totaling 24.834ns) by 0.396ns
623 
 
624 10 ale500 
 Physical Path Details:
625 9 ale500 
 
626 
      Data path SLICE_260 to cpu0/regs/SLICE_64:
627 
 
628 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
629 9 ale500 
 
630 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
631 10 ale500 
CTOF_DEL    ---     0.495     R18C24D.C1 to     R18C24D.F1 cpu0/SLICE_337
632 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
633 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
634 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
635 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
636 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
637 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
638 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
639 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
640 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
641 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
642 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
643 
FCITOF1_DE  ---     0.643    R19C19A.FCI to     R19C19A.F1 cpu0/regs/ea/SLICE_41
644 
ROUTE         4     2.403     R19C19A.F1 to     R16C32D.D0 cpu0/regs/ea/regs_o_eamem_addr[8]
645 
CTOF_DEL    ---     0.495     R16C32D.D0 to     R16C32D.F0 cpu0/regs/SLICE_922
646 
ROUTE         1     0.645     R16C32D.F0 to     R14C32C.D0 cpu0/regs/ea/N_1412
647 
CTOF_DEL    ---     0.495     R14C32C.D0 to     R14C32C.F0 cpu0/SLICE_900
648 
ROUTE         2     1.704     R14C32C.F0 to     R12C25C.D0 cpu0/datamux_o_dest[8]
649 
CTOF_DEL    ---     0.495     R12C25C.D0 to     R12C25C.F0 cpu0/regs/SLICE_361
650 
ROUTE         6     0.469     R12C25C.F0 to     R12C25B.C1 cpu0/regs/left_1[8]
651 
CTOF_DEL    ---     0.495     R12C25B.C1 to     R12C25B.F1 cpu0/regs/SLICE_1189
652 
ROUTE         1     1.088     R12C25B.F1 to     R14C25C.B1 cpu0/regs/N_251
653 
CTOF_DEL    ---     0.495     R14C25C.B1 to     R14C25C.F1 cpu0/regs/SLICE_955
654 
ROUTE         1     0.626     R14C25C.F1 to     R14C25C.D0 cpu0/regs/SS_16[8]
655 
CTOF_DEL    ---     0.495     R14C25C.D0 to     R14C25C.F0 cpu0/regs/SLICE_955
656 
ROUTE         1     1.570     R14C25C.F0 to     R10C26B.C0 cpu0/regs/SS_231_i1_mux
657 
C0TOFCO_DE  ---     1.023     R10C26B.C0 to    R10C26B.FCO cpu0/regs/SLICE_67
658 
ROUTE         1     0.000    R10C26B.FCO to    R10C26C.FCI cpu0/regs/SS_cry[9]
659 
FCITOFCO_D  ---     0.162    R10C26C.FCI to    R10C26C.FCO cpu0/regs/SLICE_66
660 
ROUTE         1     0.000    R10C26C.FCO to    R10C26D.FCI cpu0/regs/SS_cry[11]
661 
FCITOFCO_D  ---     0.162    R10C26D.FCI to    R10C26D.FCO cpu0/regs/SLICE_65
662 
ROUTE         1     0.000    R10C26D.FCO to    R10C27A.FCI cpu0/regs/SS_cry[13]
663 
FCITOF1_DE  ---     0.643    R10C27A.FCI to     R10C27A.F1 cpu0/regs/SLICE_64
664 
ROUTE         1     0.000     R10C27A.F1 to    R10C27A.DI1 cpu0/regs/SS_s[15] (to cpu_clkgen)
665 
                  --------
666 
                   24.438   (36.4% logic, 63.6% route), 18 logic levels.
667 
 
668 
 Clock Skew Details:
669 
 
670 
      Source Clock Path clk40_i to SLICE_260:
671 9 ale500 
 
672 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
673 9 ale500 
 
674 
                  --------
675 
 
676 10 ale500 
 
677 9 ale500 
 
678 
 
679 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
680 9 ale500 
ROUTE       367     2.399       27.PADDI to    R10C27A.CLK cpu_clkgen
681 
                  --------
682 
 
683 10 ale500 
 
684 9 ale500 
 
685 
Passed: The following path meets requirements by 0.409ns
686 10 ale500 
 
687 9 ale500 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
688 
 
689 
 
690 
 
691 10 ale500 
 
692 9 ale500 
 
693 
 
694 
 
695 10 ale500 
 
696 
     24.425ns physical path delay SLICE_260 to cpu0/regs/SLICE_55 meets
697 9 ale500 
 
698 10 ale500 
      0.000ns skew and
699 9 ale500 
 
700 
 
701 
 
702 10 ale500 
 
703 9 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_55:
704 
 
705 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
706 9 ale500 
 
707 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
708 
 
709 10 ale500 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
710 9 ale500 
 
711 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
712 10 ale500 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
713 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
714 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
715 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
716 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
717 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
718 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
719 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
720 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
721 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
722 
FCITOF0_DE  ---     0.585    R19C19B.FCI to     R19C19B.F0 cpu0/regs/ea/SLICE_40
723 
ROUTE         4     2.326     R19C19B.F0 to     R16C33D.C1 cpu0/regs/regs_o_eamem_addr[9]
724 
CTOF_DEL    ---     0.495     R16C33D.C1 to     R16C33D.F1 cpu0/regs/SLICE_1180
725 
ROUTE         1     1.023     R16C33D.F1 to     R14C33A.B0 cpu0/regs/N_1413
726 
CTOF_DEL    ---     0.495     R14C33A.B0 to     R14C33A.F0 cpu0/SLICE_974
727 
ROUTE         2     1.971     R14C33A.F0 to     R12C25C.D1 cpu0/datamux_o_dest[9]
728 
CTOF_DEL    ---     0.495     R12C25C.D1 to     R12C25C.F1 cpu0/regs/SLICE_361
729 
ROUTE         6     0.675     R12C25C.F1 to     R12C24B.D0 cpu0/regs/left_1[9]
730 
CTOF_DEL    ---     0.495     R12C24B.D0 to     R12C24B.F0 cpu0/regs/SLICE_1190
731 
ROUTE         1     0.986     R12C24B.F0 to     R11C24D.A1 cpu0/regs/N_288
732 
CTOF_DEL    ---     0.495     R11C24D.A1 to     R11C24D.F1 cpu0/regs/SLICE_948
733 
ROUTE         1     0.436     R11C24D.F1 to     R11C24D.C0 cpu0/regs/SU_16[9]
734 
CTOF_DEL    ---     0.495     R11C24D.C0 to     R11C24D.F0 cpu0/regs/SLICE_948
735 
ROUTE         1     1.163     R11C24D.F0 to     R11C23B.C1 cpu0/regs/SU_216_i1_mux
736 
C1TOFCO_DE  ---     0.889     R11C23B.C1 to    R11C23B.FCO cpu0/regs/SLICE_58
737 
ROUTE         1     0.000    R11C23B.FCO to    R11C23C.FCI cpu0/regs/SU_cry[9]
738 
FCITOFCO_D  ---     0.162    R11C23C.FCI to    R11C23C.FCO cpu0/regs/SLICE_57
739 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
740 
FCITOFCO_D  ---     0.162    R11C23D.FCI to    R11C23D.FCO cpu0/regs/SLICE_56
741 
ROUTE         1     0.000    R11C23D.FCO to    R11C24A.FCI cpu0/regs/SU_cry[13]
742 
FCITOF0_DE  ---     0.585    R11C24A.FCI to     R11C24A.F0 cpu0/regs/SLICE_55
743 
ROUTE         1     0.000     R11C24A.F0 to    R11C24A.DI0 cpu0/regs/SU_s[14] (to cpu_clkgen)
744 
                  --------
745 
                   24.425   (36.0% logic, 64.0% route), 19 logic levels.
746 
 
747 
 Clock Skew Details:
748 9 ale500 
 
749 10 ale500 
      Source Clock Path clk40_i to SLICE_260:
750 9 ale500 
 
751 
   Name    Fanout   Delay (ns)          Site               Resource
752 
 
753 10 ale500 
                  --------
754 9 ale500 
 
755 
 
756 10 ale500 
      Destination Clock Path clk40_i to cpu0/regs/SLICE_55:
757 9 ale500 
 
758 
   Name    Fanout   Delay (ns)          Site               Resource
759 
 
760 
                  --------
761 
 
762 
 
763 10 ale500 
 
764 9 ale500 
Passed: The following path meets requirements by 0.413ns
765 
 
766 
 
767 
 
768 10 ale500 
   Source:         FF         Q              cpu0/k_ind_ea[0]  (from cpu_clkgen +)
769 9 ale500 
 
770 
 
771 
 
772 10 ale500 
 
773 
 Constraint Details:
774 9 ale500 
 
775 10 ale500 
     24.421ns physical path delay SLICE_260 to cpu0/regs/SLICE_56 meets
776 9 ale500 
 
777 
      0.000ns skew and
778 
 
779 10 ale500 
 
780 9 ale500 
 Physical Path Details:
781 
 
782 10 ale500 
      Data path SLICE_260 to cpu0/regs/SLICE_56:
783 9 ale500 
 
784 
   Name    Fanout   Delay (ns)          Site               Resource
785 
 
786 10 ale500 
ROUTE        22     1.724     R18C14A.Q0 to     R18C24D.C1 cpu0/k_ind_ea[0]
787 9 ale500 
 
788 
ROUTE         1     1.959     R18C24D.F1 to     R15C12A.D1 cpu0/noofs7_2[0]
789 10 ale500 
CTOF_DEL    ---     0.495     R15C12A.D1 to     R15C12A.F1 cpu0/SLICE_782
790 
ROUTE        13     2.026     R15C12A.F1 to     R19C20D.D1 cpu0/regs/ea/un1_eamem_addr63_3_1
791 
CTOF_DEL    ---     0.495     R19C20D.D1 to     R19C20D.F1 cpu0/regs/ea/SLICE_1256
792 
ROUTE         5     1.337     R19C20D.F1 to     R19C18B.A0 cpu0/regs/ea/eamem_addr_o
793 
C0TOFCO_DE  ---     1.023     R19C18B.A0 to    R19C18B.FCO cpu0/regs/ea/SLICE_44
794 
ROUTE         1     0.000    R19C18B.FCO to    R19C18C.FCI cpu0/regs/ea/eamem_addr_o_cry_2
795 
FCITOFCO_D  ---     0.162    R19C18C.FCI to    R19C18C.FCO cpu0/regs/ea/SLICE_43
796 
ROUTE         1     0.000    R19C18C.FCO to    R19C18D.FCI cpu0/regs/ea/eamem_addr_o_cry_4
797 
FCITOFCO_D  ---     0.162    R19C18D.FCI to    R19C18D.FCO cpu0/regs/ea/SLICE_42
798 
ROUTE         1     0.000    R19C18D.FCO to    R19C19A.FCI cpu0/regs/ea/eamem_addr_o_cry_6
799 
FCITOFCO_D  ---     0.162    R19C19A.FCI to    R19C19A.FCO cpu0/regs/ea/SLICE_41
800 
ROUTE         1     0.000    R19C19A.FCO to    R19C19B.FCI cpu0/regs/ea/eamem_addr_o_cry_8
801 
FCITOF1_DE  ---     0.643    R19C19B.FCI to     R19C19B.F1 cpu0/regs/ea/SLICE_40
802 
ROUTE         4     2.307     R19C19B.F1 to     R16C30C.C1 cpu0/regs_o_eamem_addr[10]
803 
CTOF_DEL    ---     0.495     R16C30C.C1 to     R16C30C.F1 cpu0/alu/alu16/mulu/SLICE_196
804 
ROUTE         1     1.023     R16C30C.F1 to     R14C30D.B0 cpu0/alu/alu16/mulu/N_1414
805 
CTOF_DEL    ---     0.495     R14C30D.B0 to     R14C30D.F0 cpu0/alu/alu16/SLICE_1054
806 
ROUTE         2     1.640     R14C30D.F0 to     R12C24A.A0 cpu0/datamux_o_dest[10]
807 
CTOF_DEL    ---     0.495     R12C24A.A0 to     R12C24A.F0 cpu0/regs/SLICE_362
808 
ROUTE         6     0.780     R12C24A.F0 to     R11C24B.C0 cpu0/regs/left_1[10]
809 
CTOF_DEL    ---     0.495     R11C24B.C0 to     R11C24B.F0 cpu0/regs/SLICE_1191
810 
ROUTE         1     0.958     R11C24B.F0 to     R10C23D.D1 cpu0/regs/N_289
811 
CTOF_DEL    ---     0.495     R10C23D.D1 to     R10C23D.F1 cpu0/regs/SLICE_949
812 
ROUTE         1     0.436     R10C23D.F1 to     R10C23D.C0 cpu0/regs/SU_16[10]
813 
CTOF_DEL    ---     0.495     R10C23D.C0 to     R10C23D.F0 cpu0/regs/SLICE_949
814 
ROUTE         1     1.506     R10C23D.F0 to     R11C23C.C0 cpu0/regs/SU_217_i1_mux
815 
C0TOFCO_DE  ---     1.023     R11C23C.C0 to    R11C23C.FCO cpu0/regs/SLICE_57
816 
ROUTE         1     0.000    R11C23C.FCO to    R11C23D.FCI cpu0/regs/SU_cry[11]
817 
FCITOF1_DE  ---     0.643    R11C23D.FCI to     R11C23D.F1 cpu0/regs/SLICE_56
818 
ROUTE         1     0.000     R11C23D.F1 to    R11C23D.DI1 cpu0/regs/SU_s[13] (to cpu_clkgen)
819 
                  --------
820 
                   24.421   (35.7% logic, 64.3% route), 17 logic levels.
821 
 
822 
 Clock Skew Details:
823 
 
824 
      Source Clock Path clk40_i to SLICE_260:
825 
 
826 
   Name    Fanout   Delay (ns)          Site               Resource
827 9 ale500 
ROUTE       367     2.399       27.PADDI to    R18C14A.CLK cpu_clkgen
828 10 ale500 
                  --------
829 9 ale500 
 
830 
 
831 
 
832 10 ale500 
 
833 9 ale500 
 
834 
ROUTE       367     2.399       27.PADDI to    R11C23D.CLK cpu_clkgen
835 10 ale500 
                  --------
836 9 ale500 
                    2.399   (0.0% logic, 100.0% route), 0 logic levels.
837 
 
838 
 
839 10 ale500 
 
840 9 ale500 
 
841 
--------------
842 10 ale500 
----------------------------------------------------------------------------
843 9 ale500 
Preference                              |   Constraint|       Actual|Levels
844 
----------------------------------------------------------------------------
845 
 
846 
 
847 10 ale500 
MHz ;                                   |   40.000 MHz|   40.406 MHz|  18
848 9 ale500 
 
849 
----------------------------------------------------------------------------
850 
 
851 10 ale500 
 
852 
All preferences were met.
853 9 ale500 
 
854 10 ale500 
 
855 9 ale500 
 
856 
------------------------
857 
 
858 10 ale500 
Found 1 clocks:
859 9 ale500 
 
860 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
861 10 ale500 
   Covered under: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
862 9 ale500 
 
863 
 
864 
 
865 10 ale500 
---------------
866 9 ale500 
 
867 
Timing errors: 0  Score: 0
868 10 ale500 
Cumulative negative slack: 0
869 
 
870 
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
871 
 
872 
--------------------------------------------------------------------------------
873 
<A name="Par_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101</big></U></B>
874 
Thu Feb  6 15:36:12 2014
875 
 
876 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
877 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
878 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
879 
Copyright (c) 2001 Agere Systems   All rights reserved.
880 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
881 
 
882 
<A name="ptwr_hold_ri"></A><B><U><big>Report Information</big></U></B>
883 
------------------
884 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
885 
Design file:     P6809_P6809.ncd
886 
Preference file: P6809_P6809.prf
887 
Device,speed:    LCMXO2-7000HE,m
888 
Report level:    verbose report, limited to 10 items per preference
889 
--------------------------------------------------------------------------------
890 
 
891 
<A name="ptwr_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
892 
 
893 
<LI><A href='#par_twr_pref_1_0' Target='right'>FREQUENCY NET "cpu_clkgen" 40.000000 MHz (0 errors)</A></LI>            4096 items scored, 0 timing errors detected.
894 
 
895 
BLOCK ASYNCPATHS
896 
BLOCK RESETPATHS
897 
--------------------------------------------------------------------------------
898 
 
899 
 
900 
 
901 
================================================================================
902 9 ale500 
<A name="par_twr_pref_1_0"></A>Preference: FREQUENCY NET "cpu_clkgen" 40.000000 MHz ;
903 10 ale500 
            4096 items scored, 0 timing errors detected.
904 9 ale500 
 
905 
 
906 
 
907 10 ale500 
Passed: The following path meets requirements by 0.217ns
908 9 ale500 
 
909 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
910 10 ale500 
 
911 9 ale500 
   Source:         FF         Q              textctrl/chars_data[6]  (from cpu_clkgen +)
912 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)
913 
 
914 10 ale500 
   Delay:               0.322ns  (40.7% logic, 59.3% route), 1 logic levels.
915 9 ale500 
 
916 
 Constraint Details:
917 10 ale500 
 
918 9 ale500 
      0.322ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
919 
      0.052ns ADDR_HLD and
920 
 
921 10 ale500 
     -0.053ns skew requirement (totaling 0.105ns) by 0.217ns
922 9 ale500 
 
923 
 Physical Path Details:
924 
 
925 
      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
926 
 
927 
   Name    Fanout   Delay (ns)          Site               Resource
928 
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q0 SLICE_454 (from cpu_clkgen)
929 
ROUTE         4     0.191     R14C17C.Q0 to *_R13C16.ADA11 textctrl/chars_data[6] (to cpu_clkgen)
930 10 ale500 
                  --------
931 9 ale500 
                    0.322   (40.7% logic, 59.3% route), 1 logic levels.
932 
 
933 
 
934 
 
935 
      Source Clock Path clk40_i to SLICE_454:
936 
 
937 
 
938 
ROUTE       367     0.846       27.PADDI to    R14C17C.CLK cpu_clkgen
939 
                  --------
940 
 
941 
 
942 
 
943 10 ale500 
 
944 9 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
945 
 
946 
 
947 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
948 
 
949 
 
950 
Passed: The following path meets requirements by 0.234ns
951 
 
952 
 
953 10 ale500 
 
954 9 ale500 
 
955 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_0_3(ASIC)  (to cpu_clkgen +)
956 
 
957 10 ale500 
   Delay:               0.339ns  (38.6% logic, 61.4% route), 1 logic levels.
958 9 ale500 
 
959 
 Constraint Details:
960 
 
961 
      0.339ns physical path delay SLICE_454 to textctrl/font/fontrom_0_0_3 meets
962 
      0.052ns ADDR_HLD and
963 
      0.000ns delay constraint less
964 
 
965 
 
966 
 Physical Path Details:
967 
 
968 
      Data path SLICE_454 to textctrl/font/fontrom_0_0_3:
969 
 
970 
   Name    Fanout   Delay (ns)          Site               Resource
971 
REG_DEL     ---     0.131    R14C17C.CLK to     R14C17C.Q1 SLICE_454 (from cpu_clkgen)
972 
ROUTE         4     0.208     R14C17C.Q1 to *_R13C16.ADA12 textctrl/chars_data[7] (to cpu_clkgen)
973 
 
974 
                    0.339   (38.6% logic, 61.4% route), 1 logic levels.
975 
 
976 
 Clock Skew Details:
977 
 
978 
      Source Clock Path clk40_i to SLICE_454:
979 
 
980 
   Name    Fanout   Delay (ns)          Site               Resource
981 
 
982 
 
983 
 
984 
 
985 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_0_3:
986 
 
987 
   Name    Fanout   Delay (ns)          Site               Resource
988 
 
989 
 
990 10 ale500 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
991 9 ale500 
 
992 
 
993 
 
994 10 ale500 
 
995 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
996 9 ale500 
 
997 10 ale500 
   Source:         FF         Q              reset_cnt[0]  (from cpu_clkgen +)
998 9 ale500 
 
999 
 
1000 
 
1001 10 ale500 
 
1002 
 Constraint Details:
1003 9 ale500 
 
1004 10 ale500 
      0.288ns physical path delay SLICE_444 to SLICE_444 meets
1005 9 ale500 
 
1006 
      0.000ns delay constraint less
1007 
 
1008 10 ale500 
 
1009 9 ale500 
 
1010 
 
1011 10 ale500 
      Data path SLICE_444 to SLICE_444:
1012 
 
1013 9 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
1014 10 ale500 
REG_DEL     ---     0.131     R19C8D.CLK to      R19C8D.Q0 SLICE_444 (from cpu_clkgen)
1015 9 ale500 
 
1016 
                  --------
1017 
 
1018 10 ale500 
 
1019 9 ale500 
 
1020 
 
1021 10 ale500 
      Source Clock Path clk40_i to SLICE_444:
1022 9 ale500 
 
1023 
   Name    Fanout   Delay (ns)          Site               Resource
1024 
 
1025 10 ale500 
                  --------
1026 9 ale500 
 
1027 
 
1028 10 ale500 
      Destination Clock Path clk40_i to SLICE_444:
1029 9 ale500 
 
1030 
   Name    Fanout   Delay (ns)          Site               Resource
1031 
 
1032 
 
1033 10 ale500 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1034 9 ale500 
 
1035 
 
1036 
 
1037 10 ale500 
 
1038 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1039 9 ale500 
 
1040 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[0]  (from cpu_clkgen +)
1041 9 ale500 
 
1042 
 
1043 
 
1044 10 ale500 
 
1045 
 Constraint Details:
1046 9 ale500 
 
1047 10 ale500 
      0.357ns physical path delay textctrl/SLICE_29 to textctrl/SLICE_29 meets
1048 9 ale500 
 
1049 
      0.000ns delay constraint less
1050 
 
1051 10 ale500 
 
1052 9 ale500 
 
1053 
 
1054 10 ale500 
      Data path textctrl/SLICE_29 to textctrl/SLICE_29:
1055 
 
1056 9 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
1057 10 ale500 
REG_DEL     ---     0.131    R25C10A.CLK to     R25C10A.Q1 textctrl/SLICE_29 (from cpu_clkgen)
1058 9 ale500 
 
1059 
CTOF_DEL    ---     0.099     R25C10A.A1 to     R25C10A.F1 textctrl/SLICE_29
1060 
 
1061 10 ale500 
                  --------
1062 9 ale500 
 
1063 
 
1064 10 ale500 
 Clock Skew Details:
1065 9 ale500 
 
1066 
      Source Clock Path clk40_i to textctrl/SLICE_29:
1067 
 
1068 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
1069 9 ale500 
 
1070 
                  --------
1071 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1072 9 ale500 
 
1073 
      Destination Clock Path clk40_i to textctrl/SLICE_29:
1074 
 
1075 
 
1076 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10A.CLK cpu_clkgen
1077 9 ale500 
 
1078 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1079 
 
1080 10 ale500 
 
1081 
Passed: The following path meets requirements by 0.370ns
1082 9 ale500 
 
1083 10 ale500 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1084 9 ale500 
 
1085 
   Source:         FF         Q              textctrl/blink_cnt[4]  (from cpu_clkgen +)
1086 
 
1087 10 ale500 
 
1088 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1089 9 ale500 
 
1090 10 ale500 
 Constraint Details:
1091 9 ale500 
 
1092 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1093 
 
1094 10 ale500 
      0.000ns delay constraint less
1095 9 ale500 
 
1096 
 
1097 10 ale500 
 Physical Path Details:
1098 
 
1099 9 ale500 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1100 10 ale500 
 
1101 9 ale500 
 
1102 
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q1 textctrl/SLICE_27 (from cpu_clkgen)
1103 
 
1104 10 ale500 
CTOF_DEL    ---     0.099     R25C10C.A1 to     R25C10C.F1 textctrl/SLICE_27
1105 9 ale500 
 
1106 
                  --------
1107 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1108 9 ale500 
 
1109 
 Clock Skew Details:
1110 
 
1111 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1112 9 ale500 
 
1113 
   Name    Fanout   Delay (ns)          Site               Resource
1114 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1115 9 ale500 
                  --------
1116 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1117 9 ale500 
 
1118 
 
1119 10 ale500 
 
1120 9 ale500 
 
1121 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1122 
 
1123 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1124 
 
1125 9 ale500 
 
1126 10 ale500 
Passed: The following path meets requirements by 0.370ns
1127 9 ale500 
 
1128 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1129 
 
1130 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[3]  (from cpu_clkgen +)
1131 
   Destination:    FF         Data in        textctrl/blink_cnt[3]  (to cpu_clkgen +)
1132 9 ale500 
 
1133 10 ale500 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1134 9 ale500 
 
1135 
 Constraint Details:
1136 
 
1137 10 ale500 
      0.357ns physical path delay textctrl/SLICE_27 to textctrl/SLICE_27 meets
1138 9 ale500 
 
1139 
      0.000ns delay constraint less
1140 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1141 
 
1142 
 Physical Path Details:
1143 
 
1144 9 ale500 
      Data path textctrl/SLICE_27 to textctrl/SLICE_27:
1145 10 ale500 
 
1146 9 ale500 
 
1147 
REG_DEL     ---     0.131    R25C10C.CLK to     R25C10C.Q0 textctrl/SLICE_27 (from cpu_clkgen)
1148 
 
1149 10 ale500 
CTOF_DEL    ---     0.099     R25C10C.A0 to     R25C10C.F0 textctrl/SLICE_27
1150 9 ale500 
 
1151 
                  --------
1152 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1153 9 ale500 
 
1154 10 ale500 
 Clock Skew Details:
1155 9 ale500 
 
1156 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_27:
1157 9 ale500 
 
1158 
   Name    Fanout   Delay (ns)          Site               Resource
1159 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1160 9 ale500 
                  --------
1161 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1162 9 ale500 
 
1163 
 
1164 10 ale500 
 
1165 9 ale500 
 
1166 
ROUTE       367     0.828       27.PADDI to    R25C10C.CLK cpu_clkgen
1167 
 
1168 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1169 
 
1170 9 ale500 
 
1171 10 ale500 
Passed: The following path meets requirements by 0.370ns
1172 9 ale500 
 
1173 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1174 
 
1175 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[1]  (from cpu_clkgen +)
1176 
   Destination:    FF         Data in        textctrl/blink_cnt[1]  (to cpu_clkgen +)
1177 9 ale500 
 
1178 10 ale500 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1179 9 ale500 
 
1180 
 Constraint Details:
1181 
 
1182 10 ale500 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1183 9 ale500 
 
1184 
      0.000ns delay constraint less
1185 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1186 
 
1187 
 Physical Path Details:
1188 
 
1189 9 ale500 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1190 10 ale500 
 
1191 9 ale500 
 
1192 
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q0 textctrl/SLICE_28 (from cpu_clkgen)
1193 
 
1194 10 ale500 
CTOF_DEL    ---     0.099     R25C10B.A0 to     R25C10B.F0 textctrl/SLICE_28
1195 9 ale500 
 
1196 
                  --------
1197 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1198 9 ale500 
 
1199 10 ale500 
 Clock Skew Details:
1200 9 ale500 
 
1201 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1202 9 ale500 
 
1203 
   Name    Fanout   Delay (ns)          Site               Resource
1204 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1205 9 ale500 
                  --------
1206 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1207 9 ale500 
 
1208 
 
1209 
 
1210 
 
1211 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1212 
 
1213 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1214 
 
1215 9 ale500 
 
1216 
Passed: The following path meets requirements by 0.370ns
1217 
 
1218 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1219 
 
1220 10 ale500 
   Source:         FF         Q              textctrl/blink_cnt[2]  (from cpu_clkgen +)
1221 9 ale500 
   Destination:    FF         Data in        textctrl/blink_cnt[2]  (to cpu_clkgen +)
1222 
 
1223 
   Delay:               0.357ns  (64.4% logic, 35.6% route), 2 logic levels.
1224 
 
1225 
 Constraint Details:
1226 
 
1227 10 ale500 
      0.357ns physical path delay textctrl/SLICE_28 to textctrl/SLICE_28 meets
1228 9 ale500 
 
1229 
      0.000ns delay constraint less
1230 10 ale500 
      0.000ns skew requirement (totaling -0.013ns) by 0.370ns
1231 
 
1232 
 Physical Path Details:
1233 
 
1234 9 ale500 
      Data path textctrl/SLICE_28 to textctrl/SLICE_28:
1235 
 
1236 
 
1237 
REG_DEL     ---     0.131    R25C10B.CLK to     R25C10B.Q1 textctrl/SLICE_28 (from cpu_clkgen)
1238 
 
1239 10 ale500 
CTOF_DEL    ---     0.099     R25C10B.A1 to     R25C10B.F1 textctrl/SLICE_28
1240 9 ale500 
 
1241 
                  --------
1242 10 ale500 
                    0.357   (64.4% logic, 35.6% route), 2 logic levels.
1243 9 ale500 
 
1244 
 Clock Skew Details:
1245 
 
1246 10 ale500 
      Source Clock Path clk40_i to textctrl/SLICE_28:
1247 9 ale500 
 
1248 
   Name    Fanout   Delay (ns)          Site               Resource
1249 10 ale500 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1250 9 ale500 
                  --------
1251 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1252 
 
1253 
 
1254 
 
1255 
 
1256 
ROUTE       367     0.828       27.PADDI to    R25C10B.CLK cpu_clkgen
1257 
 
1258 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1259 
 
1260 
 
1261 
Passed: The following path meets requirements by 0.371ns
1262 
 
1263 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1264 
 
1265 
   Source:         FF         Q              textctrl/chars_data[3]  (from cpu_clkgen +)
1266 
   Destination:    DP8KC      Port           textctrl/font/fontrom_0_3_0(ASIC)  (to cpu_clkgen +)
1267 
 
1268 
   Delay:               0.476ns  (27.5% logic, 72.5% route), 1 logic levels.
1269 
 
1270 
 Constraint Details:
1271 
 
1272 
      0.476ns physical path delay textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0 meets
1273 
 
1274 
      0.000ns delay constraint less
1275 10 ale500 
     -0.053ns skew requirement (totaling 0.105ns) by 0.371ns
1276 
 
1277 
 Physical Path Details:
1278 
 
1279 9 ale500 
      Data path textctrl/SLICE_1231 to textctrl/font/fontrom_0_3_0:
1280 
 
1281 
 
1282 
REG_DEL     ---     0.131    R19C14D.CLK to     R19C14D.Q1 textctrl/SLICE_1231 (from cpu_clkgen)
1283 
 
1284 
                  --------
1285 
 
1286 
 
1287 10 ale500 
 Clock Skew Details:
1288 9 ale500 
 
1289 
      Source Clock Path clk40_i to textctrl/SLICE_1231:
1290 
 
1291 
   Name    Fanout   Delay (ns)          Site               Resource
1292 
 
1293 
                  --------
1294 10 ale500 
                    0.846   (0.0% logic, 100.0% route), 0 logic levels.
1295 9 ale500 
 
1296 
      Destination Clock Path clk40_i to textctrl/font/fontrom_0_3_0:
1297 
 
1298 
 
1299 
ROUTE       367     0.899       27.PADDI to *R_R20C16.CLKA cpu_clkgen
1300 
 
1301 
                    0.899   (0.0% logic, 100.0% route), 0 logic levels.
1302 
 
1303 10 ale500 
 
1304 
Passed: The following path meets requirements by 0.372ns
1305 9 ale500 
 
1306 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
1307 
 
1308 
   Source:         FF         Q              textctrl/x_cnt[3]  (from cpu_clkgen +)
1309 
 
1310 10 ale500 
 
1311 9 ale500 
   Delay:               0.359ns  (64.1% logic, 35.9% route), 2 logic levels.
1312 
 
1313 
 Constraint Details:
1314 
 
1315 
      0.359ns physical path delay textctrl/SLICE_13 to textctrl/SLICE_13 meets
1316 
 
1317 10 ale500 
      0.000ns delay constraint less
1318 9 ale500 
 
1319 
 
1320 10 ale500 
 Physical Path Details:
1321 
 
1322 
      Data path textctrl/SLICE_13 to textctrl/SLICE_13:
1323 
 
1324 9 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
1325 
REG_DEL     ---     0.131    R22C10C.CLK to     R22C10C.Q0 textctrl/SLICE_13 (from cpu_clkgen)
1326 
 
1327 
CTOF_DEL    ---     0.099     R22C10C.A0 to     R22C10C.F0 textctrl/SLICE_13
1328 
 
1329 10 ale500 
                  --------
1330 9 ale500 
 
1331 
 
1332 10 ale500 
 Clock Skew Details:
1333 9 ale500 
 
1334 
      Source Clock Path clk40_i to textctrl/SLICE_13:
1335 
 
1336 10 ale500 
   Name    Fanout   Delay (ns)          Site               Resource
1337 9 ale500 
 
1338 
                  --------
1339 10 ale500 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1340 9 ale500 
 
1341 
      Destination Clock Path clk40_i to textctrl/SLICE_13:
1342 
 
1343 
 
1344 10 ale500 
ROUTE       367     0.828       27.PADDI to    R22C10C.CLK cpu_clkgen
1345 9 ale500 
 
1346 
                    0.828   (0.0% logic, 100.0% route), 0 logic levels.
1347 
 
1348 10 ale500 
<A name="ptwr_hold_rs"></A><B><U><big>Report Summary</big></U></B>
1349 
--------------
1350 9 ale500 
 
1351 10 ale500 
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
1352 9 ale500 
 
1353 
                                        |             |             |
1354 
 
1355 10 ale500 
MHz ;                                   |            -|            -|   1
1356 
                                        |             |             |
1357 9 ale500 
----------------------------------------------------------------------------
1358 10 ale500 
 
1359 9 ale500 
 
1360 
All preferences were met.
1361 
 
1362 10 ale500 
 
1363 9 ale500 
 
1364 
------------------------
1365 10 ale500 
 
1366 
Found 1 clocks:
1367 9 ale500 
 
1368 10 ale500 
Clock Domain: cpu_clkgen   Source: clk40_i.PAD   Loads: 367
1369 9 ale500 
 
1370 
 
1371 
 
1372 10 ale500 
<A name="ptwr_hold_ts"></A><B><U><big>Timing summary (Hold):</big></U></B>
1373 9 ale500 
 
1374 
 
1375 10 ale500 
Timing errors: 0  Score: 0
1376 9 ale500 
Cumulative negative slack: 0
1377 10 ale500 
 
1378 9 ale500 
 
1379 10 ale500 
 
1380 9 ale500 
 
1381 
 
1382 10 ale500 
<A name="ptwr_ts"></A><B><U><big>Timing summary (Setup and Hold):</big></U></B>
1383 9 ale500 
---------------
1384 10 ale500 
 
1385 9 ale500 
 
1386 
 
1387 10 ale500 
Cumulative negative slack: 0 (0+0)
1388 9 ale500 
 
1389 
 
1390 
 
1391 10 ale500 
 
1392 
 
1393 9 ale500 
 
1394 10 ale500 
 
1395 9 ale500 
 
1396 
<BR>
1397 
 
1398 10 ale500 
<BR>
1399 
<BR>
1400 9 ale500 
<BR>
1401 10 ale500 
<BR>
1402 9 ale500 
 
1403 
<BR>
1404 
 
1405 10 ale500 
<BR>
1406 9 ale500 
 
1407 
<BR>
1408 10 ale500 
<BR>
1409 
<BR>
1410 
<BR>
1411 
<BR>
1412 9 ale500 
<BR>
1413 10 ale500 
<BR>
1414 9 ale500 
 
1415 
<BR>
1416 
 
1417 10 ale500 
<BR>
1418 9 ale500 
 
1419 
<BR>
1420 10 ale500 
<BR>
1421 9 ale500 
<BR>
1422 10 ale500 
<BR>
1423 9 ale500 
 
1424 10 ale500 
<BR>
1425 9 ale500 
 
1426 
<BR>
1427 10 ale500 
<BR>
1428 9 ale500 
<BR>
1429 10 ale500 
<BR>
1430 9 ale500 
 
1431 
<BR>
1432 
<BR>
1433 
<BR>
1434 
<BR>
1435 
<BR>
1436 
<BR>
1437 
<BR>
1438 
<BR>
1439 
<BR>
1440 
<BR>
1441 
 
1442 
 
1443 
<BR>
1444 
 
1445 
 
1446 
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1447 
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1448 
 

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