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URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [automake.log] - Blame information for rev 10

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Line No. Rev Author Line
1 4 ale500 
 
2 
synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"
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*****************************************************************
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Warning: You are running on an unsupported platform
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  'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and above
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  current platform: CentOS release 6.4 (Final)
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Kernel \r on an \m
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*****************************************************************
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Running in Lattice mode
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Starting:    /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
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Install:     /usr/local/diamond/2.2_x64/synpbase
19 10 ale500 
Date:        Thu Feb  6 15:34:32 2014
20 4 ale500 
Version:     G-2012.09L-SP1
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Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl
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ProductType: synplify_pro
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log file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"
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33 
Running proj_1|P6809
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35 
Running Compile on proj_1|P6809
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Running Compile Process on proj_1|P6809
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Running Compile Input on proj_1|P6809
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41 
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs
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compiler Completed with warnings
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Return Code: 1
45 10 ale500 
Run Time:00h:00m:06s
46 4 ale500 
 
47 
 
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Job Compile Process completed on proj_1|P6809
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Running Premap on proj_1|P6809
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54 
premap Completed with warnings
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Return Code: 1
56 10 ale500 
Run Time:00h:00m:02s
57 4 ale500 
 
58 
 
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Job Compile completed on proj_1|P6809
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Running Map on proj_1|P6809
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Running Map & Optimize on proj_1|P6809
64 
 
65 
fpga_mapper Completed with warnings
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Return Code: 1
67 10 ale500 
Run Time:00h:00m:31s
68 4 ale500 
 
69 
 
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Job Map completed on proj_1|P6809
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Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
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Job Logic Synthesis completed on proj_1|P6809
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TCL script complete: "P6809_P6809_synplify.tcl"
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exit status=0
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Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.
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Lattice Diamond Version 2.2.0.101
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Child process exit with 0.
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==contents of P6809_P6809.srf
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Thu Feb  6 15:34:32 2014
95 4 ale500 
 
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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100 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
101 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
102 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
103 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
104 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
105 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
106 
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
107 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
108 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
109 
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
110 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
111 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
112 10 ale500 
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":732:23:732:27|Specified digits overflow the number's size
113 4 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
114 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
115 7 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
116 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
117 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
118 4 ale500 
Verilog syntax check successful!
119 10 ale500 
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v changed - recompiling
120 4 ale500 
Selecting top level module CC3_top
121 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":62:7:62:12|Synthesizing module logic8
122 4 ale500 
 
123 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:7:85:12|Synthesizing module arith8
124 6 ale500 
 
125 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":158:7:158:12|Synthesizing module shift8
126 6 ale500 
 
127 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":198:7:198:10|Synthesizing module alu8
128 6 ale500 
 
129 10 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":320:0:320:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
130 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:12:241:13|No assignment to n8
131 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":241:20:241:21|No assignment to z8
132 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":302:0:302:5|Pruning register regq8[7:0]
133 6 ale500 
 
134 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":604:7:604:12|Synthesizing module mul8x8
135 6 ale500 
 
136 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":129:7:129:13|Synthesizing module arith16
137 9 ale500 
 
138 10 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":326:7:326:11|Synthesizing module alu16
139 6 ale500 
 
140 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":412:23:412:29|No assignment to wire arith_h
141 6 ale500 
 
142 10 ale500 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":518:0:518:5|Pruning register regq16[15:0]
143 6 ale500 
 
144 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
145 
 
146 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":191:7:191:13|Synthesizing module calc_ea
147 
 
148 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
149 
 
150 9 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":177:0:177:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
151 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
152 
 
153 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":138:7:138:15|Synthesizing module decode_op
154 4 ale500 
 
155 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":266:7:266:15|Synthesizing module decode_ea
156 4 ale500 
 
157 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":292:7:292:16|Synthesizing module decode_alu
158 4 ale500 
 
159 9 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":365:7:365:20|Synthesizing module test_condition
160 4 ale500 
 
161 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
162 
 
163 10 ale500 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":450:6:450:13|Ignoring system task $display
164 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1074:0:1074:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
165 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":67:11:67:23|No assignment to wire alu8_o_result
166 4 ale500 
 
167 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":68:11:68:20|No assignment to wire alu8_o_CCR
168 6 ale500 
 
169 10 ale500 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
170 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
171 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
172 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
173 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
174 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
175 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
176 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
177 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
178 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
179 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
180 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
181 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
182 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
183 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
184 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
185 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
186 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
187 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
188 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
189 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
190 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
191 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
192 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
193 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
194 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
195 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
196 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
197 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
198 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
199 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
200 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
201 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
202 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit k_mem_dest[1] is always 0, optimizing ...
203 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[1] is always 0, optimizing ...
204 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register bit next_mem_state[2] is always 0, optimizing ...
205 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
206 6 ale500 
 
207 10 ale500 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bit 1 of k_mem_dest[1:0]
208 
 
209 4 ale500 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
210 
 
211 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
212 
 
213 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
214 
 
215 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
216 
 
217 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
218 
 
219 7 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
220 
 
221 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
222 
 
223 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
224 
 
225 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
226 
 
227 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
228 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
229 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
230 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
231 
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
232 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
233 
 
234 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
235 
 
236 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
237 
 
238 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
239 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
240 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
241 
 
242 10 ale500 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:14:37:21|No assignment to clk_div2
243 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|No assignment to wire cpu1_addr_o
244 4 ale500 
 
245 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:40:43:51|No assignment to wire cpu1_data_in
246 4 ale500 
 
247 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|No assignment to wire cpu1_data_out
248 4 ale500 
 
249 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:23:44:29|No assignment to wire cpu1_we
250 4 ale500 
 
251 10 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":44:32:44:38|No assignment to wire cpu1_oe
252 4 ale500 
 
253 10 ale500 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":43:54:43:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
254 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":42:25:42:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
255 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":146:25:146:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
256 7 ale500 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
257 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
258 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
259 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
260 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
261 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
262 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
263 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
264 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
265 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
266 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
267 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
268 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
269 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
270 10 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Pruning register bits 5 to 3 of next_push_state[5:0]
271 4 ale500 
 
272 10 ale500 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":22:12:22:20|Input debug_clk is unused
273 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":369:18:369:20|Input port bits 7 to 4 of CCR[7:0] are unused
274 4 ale500 
 
275 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":294:18:294:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
276 4 ale500 
 
277 9 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":267:18:267:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
278 4 ale500 
 
279 10 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":330:18:330:20|Input port bits 7 to 4 of CCR[7:0] are unused
280 6 ale500 
 
281 10 ale500 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bits 15 to 13 of pipe0[15:0]
282 6 ale500 
 
283 10 ale500 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Register bit pipe0[12] is always 0, optimizing ...
284 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":614:0:614:5|Pruning register bit 12 of pipe0[12:0]
285 6 ale500 
 
286 10 ale500 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":199:12:199:17|Input clk_in is unused
287 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":160:18:160:21|Input b_in is unused
288 4 ale500 
@END
289 10 ale500 
Process took 0h:00m:04s realtime, 0h:00m:02s cputime
290 
# Thu Feb  6 15:34:36 2014
291 4 ale500 
 
292 
###########################################################]
293 
Premap Report
294 
 
295 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
296 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
297 
Product Version G-2012.09L-SP1
298 
 
299 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
300 
 
301 
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
302 
Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
303 
@N: MF248 |Running in 64-bit mode.
304 
@N: MF666 |Clock conversion enabled
305 
 
306 9 ale500 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
307 4 ale500 
 
308 
 
309 9 ale500 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 96MB)
310 4 ale500 
 
311 
 
312 9 ale500 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 110MB)
313 4 ale500 
 
314 
 
315 9 ale500 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 112MB)
316 4 ale500 
 
317 
 
318 
 
319 
Clock Summary
320 
**************
321 
 
322 
Start                             Requested     Requested     Clock                              Clock
323 
Clock                             Frequency     Period        Type                               Group
324 
--------------------------------------------------------------------------------------------------------------------
325 
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
326 10 ale500 
CC3_top|div_derived_clock         1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
327 4 ale500 
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
328 
====================================================================================================================
329 
 
330 10 ale500 
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 95 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
331 4 ale500 
 
332 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
333 
Finished Pre Mapping Phase.Pre-mapping successful!
334 
 
335 9 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 137MB)
336 4 ale500 
 
337 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
338 10 ale500 
# Thu Feb  6 15:34:40 2014
339 4 ale500 
 
340 
###########################################################]
341 
Map & Optimize Report
342 
 
343 
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
344 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
345 
Product Version G-2012.09L-SP1
346 
 
347 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
348 
 
349 
@N: MF248 |Running in 64-bit mode.
350 
@N: MF666 |Clock conversion enabled
351 
 
352 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
353 
 
354 
 
355 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
356 
 
357 
 
358 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
359 
 
360 
 
361 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
362 
 
363 
 
364 
 
365 7 ale500 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
366 4 ale500 
 
367 
 
368 
Available hyper_sources - for debug and ip models
369 
        None Found
370 
 
371 
 
372 10 ale500 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 135MB peak: 136MB)
373 4 ale500 
 
374 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
375 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
376 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
377 9 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SU[15:0]
378 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Found updn counter in view:work.regblock(verilog) inst SS[15:0]
379 7 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
380 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
381 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
382 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
383 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
384 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
385 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
386 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
387 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
388 4 ale500 
 
389 10 ale500 
Finished factoring (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 157MB peak: 159MB)
390 4 ale500 
 
391 10 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
392 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
393 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
394 4 ale500 
 
395 10 ale500 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:04s; CPU Time elapsed 0h:00m:02s; Memory used current: 152MB peak: 160MB)
396 4 ale500 
 
397 
 
398 
 
399 10 ale500 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:03s; Memory used current: 150MB peak: 160MB)
400 4 ale500 
 
401 10 ale500 
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":222:2:222:5|Pipelining module ea_reg_post_o[15:0]
402 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IY[15:0] pushed in.
403 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register IX[15:0] pushed in.
404 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_ind_ea[7:0] pushed in.
405 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register DP[7:0] pushed in.
406 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCB[7:0] pushed in.
407 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register eflag pushed in.
408 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register fflag pushed in.
409 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register hflag pushed in.
410 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register intff pushed in.
411 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register nff pushed in.
412 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register zff pushed in.
413 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register vff pushed in.
414 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register cff pushed in.
415 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register PC[15:0] pushed in.
416 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":123:0:123:5|Register ACCA[7:0] pushed in.
417 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_write_pc pushed in.
418 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":319:0:319:5|Register k_inc_pc pushed in.
419 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":141:35:141:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_1_0[16:0] from cpu0.alu.alu16.a16.un17_q_out[16:0]
420 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":142:35:142:64|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu16.a16.q_out_2[16:0] from cpu0.alu.alu16.a16.un28_q_out[16:0]
421 9 ale500 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":115:19:115:32|Found addmux in view:work.CC3_top(verilog) inst cpu0.regs.right[15:0] from cpu0.regs.pc_plus_1[15:0]
422 4 ale500 
 
423 10 ale500 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:17s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
424 4 ale500 
 
425 
 
426 10 ale500 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 160MB)
427 4 ale500 
 
428 
 
429 10 ale500 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:09s; Memory used current: 151MB peak: 160MB)
430 4 ale500 
 
431 
 
432 10 ale500 
Finished preparing to map (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:11s; Memory used current: 151MB peak: 160MB)
433 4 ale500 
 
434 
 
435 10 ale500 
Finished technology mapping (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:13s; Memory used current: 202MB peak: 230MB)
436 4 ale500 
 
437 
Pass             CPU time               Worst Slack             Luts / Registers
438 
------------------------------------------------------------
439 
Pass             CPU time               Worst Slack             Luts / Registers
440 
------------------------------------------------------------
441 
------------------------------------------------------------
442 
 
443 
 
444 10 ale500 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 230MB)
445 4 ale500 
 
446 
@N: FX164 |The option to pack flops in the IOB has not been specified
447 
 
448 10 ale500 
Finished restoring hierarchy (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:15s; Memory used current: 168MB peak: 230MB)
449 4 ale500 
 
450 
 
451 
 
452 
#### START OF CLOCK OPTIMIZATION REPORT #####[
453 
 
454 10 ale500 
1 non-gated/non-generated clock tree(s) driving 596 clock pin(s) of sequential element(s)
455 4 ale500 
 
456 10 ale500 
264 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
457 4 ale500 
 
458 
=========================== Non-Gated/Non-Generated Clocks ============================
459 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
460 
---------------------------------------------------------------------------------------
461 10 ale500 
@K:CKID0001       clk40_i             port                   596        div
462 4 ale500 
=======================================================================================
463 
===== Gated/Generated Clocks =====
464 
************** None **************
465 
----------------------------------
466 
==================================
467 
 
468 
 
469 
##### END OF CLOCK OPTIMIZATION REPORT ######]
470 
 
471 
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
472 
 
473 10 ale500 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:28s; CPU Time elapsed 0h:00m:16s; Memory used current: 170MB peak: 230MB)
474 4 ale500 
 
475 
Writing EDIF Netlist and constraint files
476 
G-2012.09L-SP1
477 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
478 
 
479 10 ale500 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:29s; CPU Time elapsed 0h:00m:17s; Memory used current: 174MB peak: 230MB)
480 4 ale500 
 
481 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
482 
 
483 
 
484 
 
485 
##### START OF TIMING REPORT #####[
486 10 ale500 
# Timing Report written on Thu Feb  6 15:35:10 2014
487 4 ale500 
#
488 
 
489 
 
490 
Top view:               CC3_top
491 
Requested Frequency:    1.0 MHz
492 
Wire load mode:         top
493 
Paths requested:        5
494 
Constraint File(s):
495 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
496 
 
497 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
498 
 
499 
 
500 
 
501 
Performance Summary
502 
*******************
503 
 
504 
 
505 10 ale500 
Worst slack in design: 978.937
506 4 ale500 
 
507 
                    Requested     Estimated     Requested     Estimated                 Clock        Clock
508 
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group
509 
------------------------------------------------------------------------------------------------------------------------
510 10 ale500 
CC3_top|clk40_i     1.0 MHz       47.5 MHz      1000.000      21.063        978.937     inferred     Inferred_clkgroup_0
511 4 ale500 
========================================================================================================================
512 
 
513 
 
514 
 
515 
 
516 
 
517 
Clock Relationships
518 
*******************
519 
 
520 
Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
521 
--------------------------------------------------------------------------------------------------------------------------
522 
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
523 
--------------------------------------------------------------------------------------------------------------------------
524 10 ale500 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    978.937  |  No paths    -      |  No paths    -      |  No paths    -
525 4 ale500 
==========================================================================================================================
526 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
527 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
528 
 
529 
 
530 
 
531 
Interface Information
532 
*********************
533 
 
534 
No IO constraint found
535 
 
536 
 
537 
 
538 
====================================
539 
Detailed Report for Clock: CC3_top|clk40_i
540 
====================================
541 
 
542 
 
543 
 
544 
Starting Points with Worst Slack
545 
********************************
546 
 
547 9 ale500 
                      Starting                                             Arrival
548 
Instance              Reference           Type        Pin     Net          Time        Slack
549 
                      Clock
550 
----------------------------------------------------------------------------------------------
551 10 ale500 
cpu0.alu.rb_in[0]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[0]     1.296       978.937
552 
cpu0.alu.rb_in[1]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[1]     1.296       979.080
553 
cpu0.alu.rb_in[2]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[2]     1.284       979.092
554 
cpu0.alu.rb_in[3]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[3]     1.288       979.231
555 
cpu0.alu.rb_in[4]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[4]     1.284       979.235
556 
cpu0.alu.ra_in[0]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[0]     1.299       979.502
557 
cpu0.alu.rb_in[5]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[5]     1.284       979.533
558 
cpu0.alu.rb_in[6]     CC3_top|clk40_i     FD1P3AX     Q       rb_in[6]     1.272       979.545
559 
cpu0.alu.ra_in[1]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[1]     1.299       979.645
560 
cpu0.alu.ra_in[2]     CC3_top|clk40_i     FD1P3AX     Q       ra_in[2]     1.299       979.645
561 9 ale500 
==============================================================================================
562 4 ale500 
 
563 
 
564 
Ending Points with Worst Slack
565 
******************************
566 
 
567 6 ale500 
                     Starting                                             Required
568 
Instance             Reference           Type        Pin     Net          Time         Slack
569 
                     Clock
570 
----------------------------------------------------------------------------------------------
571 10 ale500 
cpu0.regs.SS[14]     CC3_top|clk40_i     FD1P3AX     D       SS_s[14]     999.894      978.937
572 
cpu0.regs.SS[15]     CC3_top|clk40_i     FD1P3AX     D       SS_s[15]     999.894      978.937
573 
cpu0.regs.SU[14]     CC3_top|clk40_i     FD1P3AX     D       SU_s[14]     999.894      978.937
574 
cpu0.regs.SU[15]     CC3_top|clk40_i     FD1P3AX     D       SU_s[15]     999.894      978.937
575 
cpu0.regs.SS[12]     CC3_top|clk40_i     FD1P3AX     D       SS_s[12]     999.894      979.080
576 
cpu0.regs.SS[13]     CC3_top|clk40_i     FD1P3AX     D       SS_s[13]     999.894      979.080
577 
cpu0.regs.SU[12]     CC3_top|clk40_i     FD1P3AX     D       SU_s[12]     999.894      979.080
578 
cpu0.regs.SU[13]     CC3_top|clk40_i     FD1P3AX     D       SU_s[13]     999.894      979.080
579 
cpu0.regs.SS[10]     CC3_top|clk40_i     FD1P3AX     D       SS_s[10]     999.894      979.223
580 
cpu0.regs.SS[11]     CC3_top|clk40_i     FD1P3AX     D       SS_s[11]     999.894      979.223
581 6 ale500 
==============================================================================================
582 4 ale500 
 
583 
 
584 
 
585 
Worst Path Information
586 
***********************
587 
 
588 
 
589 
Path information for path number 1:
590 
      Requested Period:                      1000.000
591 6 ale500 
    - Setup time:                            0.106
592 4 ale500 
    + Clock delay at ending point:           0.000 (ideal)
593 6 ale500 
    = Required time:                         999.894
594 4 ale500 
 
595 10 ale500 
    - Propagation time:                      20.957
596 4 ale500 
    - Clock delay at starting point:         0.000 (ideal)
597 10 ale500 
    = Slack (critical) :                     978.937
598 4 ale500 
 
599 10 ale500 
    Number of logic level(s):                22
600 9 ale500 
    Starting point:                          cpu0.alu.rb_in[0] / Q
601 
    Ending point:                            cpu0.regs.SS[15] / D
602 4 ale500 
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
603 
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK
604 
 
605 10 ale500 
Instance / Net                                            Pin      Pin               Arrival     No. of
606 
Name                                         Type         Name     Dir     Delay     Time        Fan Out(s)
607 
-----------------------------------------------------------------------------------------------------------
608 
cpu0.alu.rb_in[0]                            FD1P3AX      Q        Out     1.296     1.296       -
609 
rb_in[0]                                     Net          -        -       -         -           24
610 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          A        In      0.000     1.296       -
611 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0_RNO     INV          Z        Out     0.568     1.864       -
612 
rb_in_i[0]                                   Net          -        -       -         -           1
613 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        A1       In      0.000     1.864       -
614 
cpu0.alu.alu16.a16.un8_q_out_cry_0_0         CCU2D        COUT     Out     1.544     3.408       -
615 
un8_q_out_cry_0                              Net          -        -       -         -           1
616 
cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        CIN      In      0.000     3.408       -
617 
cpu0.alu.alu16.a16.un8_q_out_cry_1_0         CCU2D        S1       Out     1.549     4.957       -
618 
un8_q_out[2]                                 Net          -        -       -         -           1
619 
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     A        In      0.000     4.957       -
620 
cpu0.alu.alu16.a16.q_out_2_cry_1_0_RNO_0     ORCALUT4     Z        Out     1.017     5.974       -
621 
q_out_2_cry_1_0_RNO_0                        Net          -        -       -         -           1
622 
cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        C1       In      0.000     5.974       -
623 
cpu0.alu.alu16.a16.q_out_2_cry_1_0           CCU2D        COUT     Out     1.544     7.519       -
624 
q_out_2_cry_2                                Net          -        -       -         -           1
625 
cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        CIN      In      0.000     7.519       -
626 
cpu0.alu.alu16.a16.q_out_2_cry_3_0           CCU2D        COUT     Out     0.143     7.661       -
627 
q_out_2_cry_4                                Net          -        -       -         -           1
628 
cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        CIN      In      0.000     7.661       -
629 
cpu0.alu.alu16.a16.q_out_2_cry_5_0           CCU2D        COUT     Out     0.143     7.804       -
630 
q_out_2_cry_6                                Net          -        -       -         -           1
631 
cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        CIN      In      0.000     7.804       -
632 
cpu0.alu.alu16.a16.q_out_2_cry_7_0           CCU2D        S0       Out     1.549     9.353       -
633 
N_2370                                       Net          -        -       -         -           1
634 
cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     B        In      0.000     9.353       -
635 
cpu0.alu.alu16.a16.q_out_3[7]                ORCALUT4     Z        Out     1.153     10.506      -
636 
arith_q[7]                                   Net          -        -       -         -           3
637 
cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     A        In      0.000     10.506      -
638 
cpu0.alu.alu16.q_out_1[7]                    ORCALUT4     Z        Out     1.017     11.523      -
639 
N_60                                         Net          -        -       -         -           1
640 
cpu0.alu.alu16.q_out[7]                      PFUMX        ALUT     In      0.000     11.523      -
641 
cpu0.alu.alu16.q_out[7]                      PFUMX        Z        Out     0.286     11.809      -
642 
q16_out[7]                                   Net          -        -       -         -           2
643 
cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     B        In      0.000     11.809      -
644 
cpu0.alu.alu8.datamux_o_dest_bm[7]           ORCALUT4     Z        Out     1.017     12.826      -
645 
datamux_o_dest_bm[7]                         Net          -        -       -         -           1
646 
cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        ALUT     In      0.000     12.826      -
647 
cpu0.alu.alu8.datamux_o_dest[7]              PFUMX        Z        Out     0.286     13.112      -
648 
datamux_o_dest[7]                            Net          -        -       -         -           2
649 
cpu0.regs.left_1[7]                          ORCALUT4     A        In      0.000     13.112      -
650 
cpu0.regs.left_1[7]                          ORCALUT4     Z        Out     1.273     14.385      -
651 
left_1[7]                                    Net          -        -       -         -           9
652 
cpu0.regs.SS_16_0[7]                         ORCALUT4     B        In      0.000     14.385      -
653 
cpu0.regs.SS_16_0[7]                         ORCALUT4     Z        Out     1.017     15.402      -
654 
N_250                                        Net          -        -       -         -           1
655 
cpu0.regs.SS_16[7]                           ORCALUT4     A        In      0.000     15.402      -
656 
cpu0.regs.SS_16[7]                           ORCALUT4     Z        Out     1.017     16.418      -
657 
SS_16[7]                                     Net          -        -       -         -           1
658 
cpu0.regs.SS_230_m3                          ORCALUT4     B        In      0.000     16.418      -
659 
cpu0.regs.SS_230_m3                          ORCALUT4     Z        Out     1.017     17.435      -
660 
SS_230_i1_mux                                Net          -        -       -         -           1
661 
cpu0.regs.SS_cry_0[6]                        CCU2D        C1       In      0.000     17.435      -
662 
cpu0.regs.SS_cry_0[6]                        CCU2D        COUT     Out     1.544     18.980      -
663 
SS_cry[7]                                    Net          -        -       -         -           1
664 
cpu0.regs.SS_cry_0[8]                        CCU2D        CIN      In      0.000     18.980      -
665 
cpu0.regs.SS_cry_0[8]                        CCU2D        COUT     Out     0.143     19.122      -
666 
SS_cry[9]                                    Net          -        -       -         -           1
667 
cpu0.regs.SS_cry_0[10]                       CCU2D        CIN      In      0.000     19.122      -
668 
cpu0.regs.SS_cry_0[10]                       CCU2D        COUT     Out     0.143     19.265      -
669 
SS_cry[11]                                   Net          -        -       -         -           1
670 
cpu0.regs.SS_cry_0[12]                       CCU2D        CIN      In      0.000     19.265      -
671 
cpu0.regs.SS_cry_0[12]                       CCU2D        COUT     Out     0.143     19.408      -
672 
SS_cry[13]                                   Net          -        -       -         -           1
673 
cpu0.regs.SS_cry_0[14]                       CCU2D        CIN      In      0.000     19.408      -
674 
cpu0.regs.SS_cry_0[14]                       CCU2D        S1       Out     1.549     20.957      -
675 
SS_s[15]                                     Net          -        -       -         -           1
676 
cpu0.regs.SS[15]                             FD1P3AX      D        In      0.000     20.957      -
677 
===========================================================================================================
678 4 ale500 
 
679 
 
680 
 
681 
##### END OF TIMING REPORT #####]
682 
 
683 
---------------------------------------
684 
Resource Usage Report
685 
Part: lcmxo2_7000he-4
686 
 
687 10 ale500 
Register bits: 580 of 6864 (8%)
688 4 ale500 
PIC Latch:       0
689 10 ale500 
I/O cells:       69
690 7 ale500 
Block Rams : 10 of 26 (38%)
691 4 ale500 
 
692 
 
693 
Details:
694 10 ale500 
BB:             8
695 
CCU2D:          186
696 7 ale500 
DP8KC:          10
697 10 ale500 
FD1P3AX:        529
698 4 ale500 
FD1P3DX:        6
699 10 ale500 
FD1S3AX:        32
700 
FD1S3IX:        3
701 4 ale500 
GSR:            1
702 
IB:             1
703 10 ale500 
INV:            20
704 
L6MUX21:        16
705 
OB:             60
706 7 ale500 
OFS1P3DX:       9
707 
OFS1P3IX:       1
708 10 ale500 
ORCALUT4:       2014
709 
PFUMX:          226
710 4 ale500 
PUR:            1
711 10 ale500 
VHI:            14
712 9 ale500 
VLO:            20
713 
false:          1
714 10 ale500 
true:           7
715 4 ale500 
Mapper successful!
716 
 
717 10 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:17s; Memory used current: 44MB peak: 230MB)
718 4 ale500 
 
719 10 ale500 
Process took 0h:00m:30s realtime, 0h:00m:17s cputime
720 
# Thu Feb  6 15:35:11 2014
721 4 ale500 
 
722 
###########################################################]
723 
 
724 
 
725 
Synthesis exit by 0.
726 
 
727 
edif2ngd  -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"
728 
edif2ngd:  version Diamond (64-bit) 2.2.0.101
729 
 
730 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
731 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
732 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
733 
Copyright (c) 2001 Agere Systems   All rights reserved.
734 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
735 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
736 10 ale500 
  On or above line 300 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
737 4 ale500 
 
738 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
739 10 ale500 
  On or above line 308 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
740 4 ale500 
 
741 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
742 10 ale500 
  On or above line 1768 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
743 4 ale500 
 
744 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
745 10 ale500 
  On or above line 3762 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
746 4 ale500 
 
747 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
748 10 ale500 
  On or above line 3915 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
749 4 ale500 
 
750 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
751 10 ale500 
  On or above line 4480 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
752 4 ale500 
 
753 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
754 10 ale500 
  On or above line 4636 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
755 4 ale500 
 
756 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
757 10 ale500 
  On or above line 8836 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
758 4 ale500 
 
759 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
760 10 ale500 
  On or above line 10966 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
761 4 ale500 
 
762 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
763 10 ale500 
  On or above line 13581 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
764 4 ale500 
 
765 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
766 10 ale500 
  On or above line 14376 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
767 4 ale500 
 
768 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
769 10 ale500 
  On or above line 15093 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
770 4 ale500 
 
771 6 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
772 10 ale500 
  On or above line 16549 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
773 6 ale500 
 
774 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
775 10 ale500 
  On or above line 17247 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
776 6 ale500 
 
777 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
778 10 ale500 
  On or above line 18117 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
779 6 ale500 
 
780 7 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
781 10 ale500 
  On or above line 18865 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
782 7 ale500 
 
783 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
784 10 ale500 
  On or above line 22005 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
785 7 ale500 
 
786 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
787 10 ale500 
  On or above line 32810 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
788 7 ale500 
 
789 9 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
790 10 ale500 
  On or above line 35408 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
791 9 ale500 
 
792 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
793 10 ale500 
  On or above line 38078 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
794 9 ale500 
 
795 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
796 10 ale500 
  On or above line 38496 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
797 9 ale500 
 
798 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
799 10 ale500 
  On or above line 43706 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
800 9 ale500 
 
801 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
802 10 ale500 
  On or above line 44658 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
803 9 ale500 
 
804 4 ale500 
Writing the design to P6809_P6809.ngo...
805 
 
806 
 
807 
ngdbuild  -a "MachXO2" -d LCMXO2-7000HE  -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data"  -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "P6809_P6809.ngo" "P6809_P6809.ngd"
808 
ngdbuild:  version Diamond (64-bit) 2.2.0.101
809 
 
810 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
811 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
812 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
813 
Copyright (c) 2001 Agere Systems   All rights reserved.
814 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
815 
Reading 'P6809_P6809.ngo' ...
816 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
817 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
818 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
819 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...
820 
 
821 
 
822 
Running DRC...
823 
 
824 10 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_15_0_COUT' has no load
825 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S0' has no load
826 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_cry_0_0_S1' has no load
827 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_15_0_COUT' has no load
828 10 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S0' has no load
829 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/un8_q_out_cry_0_0_S1' has no load
830 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_15_0_COUT' has no load
831 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_1_0_cry_0_0_S0' has no load
832 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_15_0_COUT' has no load
833 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/a16/q_out_2_cry_0_0_S0' has no load
834 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
835 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
836 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
837 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
838 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
839 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no load
840 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no load
841 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no load
842 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no load
843 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no load
844 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no load
845 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no load
846 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no load
847 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no load
848 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no load
849 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no load
850 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
851 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
852 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
853 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
854 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
855 10 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_7_0_COUT' has no load
856 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S0' has no load
857 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/un9_q_out_cry_0_0_S1' has no load
858 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_7_0_COUT' has no load
859 10 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/a8/q_out_1_cry_0_0_S0_0' has no load
860 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_COUT' has no load
861 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_s_15_0_S1' has no load
862 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S0' has no load
863 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/eamem_addr_o_cry_0_0_S1' has no load
864 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_COUT' has no load
865 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_s_15_0_S1' has no load
866 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S0' has no load
867 
WARNING - ngdbuild: logical net 'cpu0/regs/ea/ea_reg_post_o_cry_0_0_S1' has no load
868 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
869 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
870 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
871 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
872 9 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_cry_0_COUT[14]' has no load
873 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S0' has no load
874 
WARNING - ngdbuild: logical net 'cpu0/regs/SU_lcry_0_S1' has no load
875 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_cry_0_COUT[14]' has no load
876 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S0' has no load
877 
WARNING - ngdbuild: logical net 'cpu0/regs/SS_lcry_0_S1' has no load
878 
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_COUT' has no load
879 
WARNING - ngdbuild: logical net 'cpu0/regs/right_s_15_0_S1' has no load
880 
WARNING - ngdbuild: logical net 'cpu0/regs/right_cry_0_0_S0' has no load
881 7 ale500 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
882 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
883 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
884 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
885 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
886 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S0' has no load
887 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S1' has no load
888 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_10_0_COUT' has no load
889 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S0' has no load
890 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S1' has no load
891 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_COUT[5]' has no load
892 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_S0[0]' has no load
893 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_COUT[5]' has no load
894 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_S0[0]' has no load
895 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_COUT[9]' has no load
896 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_S0[0]' has no load
897 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_COUT[5]' has no load
898 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_S1[5]' has no load
899 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_cry_0_S0[0]' has no load
900 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_COUT[9]' has no load
901 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
902 10 ale500 
WARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_s_15_0_COUT' has no load
903 
WARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_s_15_0_S1' has no load
904 
WARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_cry_0_0_S0' has no load
905 
WARNING - ngdbuild: logical net 'cpu0/un1_regs_o_pc_cry_0_0_S1' has no load
906 4 ale500 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
907 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
908 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
909 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
910 10 ale500 
WARNING - ngdbuild: DRC complete with 86 warnings
911 4 ale500 
 
912 
Design Results:
913 10 ale500 
   3156 blocks expanded
914 4 ale500 
complete the first expansion
915 
Writing 'P6809_P6809.ngd' ...
916 
 
917 
map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial   "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0
918 
map:  version Diamond (64-bit) 2.2.0.101
919 
 
920 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
921 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
922 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
923 
Copyright (c) 2001 Agere Systems   All rights reserved.
924 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
925 
   Process the file: P6809_P6809.ngd
926 
   Picdevice="LCMXO2-7000HE"
927 
 
928 
   Pictype="TQFP144"
929 
 
930 
   Picspeed=4
931 
 
932 
   Remove unused logic
933 
 
934 
   Do not produce over sized NCDs.
935 
 
936 
Part used: LCMXO2-7000HETQFP144, Performance used: 4.
937 10 ale500 
WARNING - map: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf (46): Error in LOCATE COMP "wenh_o" SITE "68" ;
938 
: COMP "wenh_o" not found in design. Disbale this preference.
939 
WARNING - map: Preference parsing results:  1 semantic error detected
940 
WARNING - map: There are errors in the preference file, "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf".
941 4 ale500 
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
942 
Package Status:                     Final          Version 1.36
943 
 
944 
Running general design DRC...
945 
Removing unused logic...
946 
Optimizing...
947 9 ale500 
5 CCU2 constant inputs absorbed.
948 7 ale500 
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
949 10 ale500 
WARNING - map: IO buffer missing for top level port data_io[15:0](15)...logic will be discarded.
950 
WARNING - map: IO buffer missing for top level port data_io[15:0](14)...logic will be discarded.
951 
WARNING - map: IO buffer missing for top level port data_io[15:0](13)...logic will be discarded.
952 
WARNING - map: IO buffer missing for top level port data_io[15:0](12)...logic will be discarded.
953 
WARNING - map: IO buffer missing for top level port data_io[15:0](11)...logic will be discarded.
954 
WARNING - map: IO buffer missing for top level port data_io[15:0](10)...logic will be discarded.
955 
WARNING - map: IO buffer missing for top level port data_io[15:0](9)...logic will be discarded.
956 
WARNING - map: IO buffer missing for top level port data_io[15:0](8)...logic will be discarded.
957 7 ale500 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
958 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
959 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
960 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
961 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
962 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
963 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
964 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
965 4 ale500 
WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
966 
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
967 
 
968 
 
969 
 
970 
Design Summary:
971 10 ale500 
   Number of registers:    580
972 
      PFU registers:    570
973 7 ale500 
      PIO registers:    10
974 10 ale500 
   Number of SLICEs:          1208 out of  3432 (35%)
975 4 ale500 
      SLICEs(logic/ROM):       858 out of   858 (100%)
976 10 ale500 
      SLICEs(logic/ROM/RAM):   350 out of  2574 (14%)
977 4 ale500 
          As RAM:            0 out of  2574 (0%)
978 10 ale500 
          As Logic/ROM:    350 out of  2574 (14%)
979 
   Number of logic LUT4s:     2034
980 4 ale500 
   Number of distributed RAM:   0 (0 LUT4s)
981 10 ale500 
   Number of ripple logic:    186 (372 LUT4s)
982 4 ale500 
   Number of shift registers:   0
983 10 ale500 
   Total number of LUT4s:     2406
984 
   Number of PIO sites used: 69 + 4(JTAG) out of 115 (63%)
985 7 ale500 
   Number of block RAMs:  10 out of 26 (38%)
986 4 ale500 
   Number of GSRs:  1 out of 1 (100%)
987 
   EFB used :       No
988 
   JTAG used :      No
989 
   Readback used :  No
990 
   Oscillator used :  No
991 
   Startup used :   No
992 
   POR :            On
993 
   Bandgap :        On
994 
   Number of Power Controller:  0 out of 1 (0%)
995 
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
996 
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
997 
   Number of DCCA:  0 out of 8 (0%)
998 
   Number of DCMA:  0 out of 2 (0%)
999 
   Number of PLLs:  0 out of 2 (0%)
1000 
   Number of DQSDLLs:  0 out of 2 (0%)
1001 
   Number of CLKDIVC:  0 out of 4 (0%)
1002 
   Number of ECLKSYNCA:  0 out of 4 (0%)
1003 
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
1004 
   Notes:-
1005 
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
1006 
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
1007 
   Number of clocks:  1
1008 10 ale500 
     Net cpu_clkgen: 367 loads, 367 rising, 0 falling (Driver: PIO clk40_i )
1009 
   Number of Clock Enables:  37
1010 
     Net cpu0_we: 8 loads, 0 LSLICEs
1011 
     Net textctrl/video_en_RNIFLVI: 8 loads, 0 LSLICEs
1012 
     Net textctrl/N_75_i: 4 loads, 4 LSLICEs
1013 7 ale500 
     Net textctrl/y_cnte: 4 loads, 4 LSLICEs
1014 10 ale500 
     Net textctrl/N_76_i: 4 loads, 4 LSLICEs
1015 7 ale500 
     Net textctrl/N_4: 6 loads, 6 LSLICEs
1016 10 ale500 
     Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
1017 
     Net textctrl/line_cnte: 2 loads, 2 LSLICEs
1018 
     Net textctrl/vsync_cnt_0_sqmuxa: 4 loads, 4 LSLICEs
1019 
     Net un1_bios_en_0: 4 loads, 0 LSLICEs
1020 
     Net cpu0/k_new_pc26_1_i_RNI1GUPD: 3 loads, 3 LSLICEs
1021 6 ale500 
     Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
1022 10 ale500 
     Net cpu0/next_state_0_sqmuxa_4_RNIMOT3B: 3 loads, 3 LSLICEs
1023 
     Net cpu0/G_9: 80 loads, 80 LSLICEs
1024 
     Net cpu0/k_ofshi_1_sqmuxa_RNIHOKL: 4 loads, 4 LSLICEs
1025 
     Net cpu0/k_pp_regs60_RNI18KD3: 4 loads, 4 LSLICEs
1026 
     Net cpu0/state82_RNI5IM34: 4 loads, 4 LSLICEs
1027 
     Net cpu0/k_memhi_0_sqmuxa_RNIN4F02: 4 loads, 4 LSLICEs
1028 
     Net cpu0/un1_state_23_1_RNI2Q3P1: 4 loads, 4 LSLICEs
1029 
     Net cpu0/PC_1_sqmuxa_2_RNIK4633: 37 loads, 37 LSLICEs
1030 
     Net cpu0/k_new_pc28_RNILK8D5: 4 loads, 4 LSLICEs
1031 
     Net cpu0/regs/cff_1_sqmuxa_2_RNI1FDN: 18 loads, 18 LSLICEs
1032 
     Net cpu0/regs/eflag_0_sqmuxa_0_RNIOVLR: 4 loads, 4 LSLICEs
1033 
     Net cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1: 25 loads, 25 LSLICEs
1034 
     Net cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3: 25 loads, 25 LSLICEs
1035 
     Net cpu0/regs/DP_1_sqmuxa_1_1_0_RNIIANF1: 9 loads, 9 LSLICEs
1036 
     Net cpu0/regs/ACCB_0_sqmuxa_1_RNILJP21: 9 loads, 9 LSLICEs
1037 
     Net cpu0/regs/ACCB22_RNIDCT43: 4 loads, 4 LSLICEs
1038 
     Net cpu0/un1_state_85_RNI07AH3: 2 loads, 2 LSLICEs
1039 
     Net cpu0/un1_state_18_2_RNINGR01: 4 loads, 4 LSLICEs
1040 
     Net cpu0/un1_state_7_3_RNIREBA3: 8 loads, 8 LSLICEs
1041 
     Net cpu0/state_3_sqmuxa_5_RNIE8SO9: 8 loads, 8 LSLICEs
1042 
     Net cpu0/un1_state_75_RNISTJ21: 2 loads, 2 LSLICEs
1043 
     Net cpu0/un1_state_21_RNI6VAF: 4 loads, 4 LSLICEs
1044 
     Net cpu0/k_new_pc29_RNILU7S1: 4 loads, 4 LSLICEs
1045 
     Net cpu0/un1_state_101_RNI9RM81: 2 loads, 2 LSLICEs
1046 
     Net cpu0/k_mem_dest_RNO[0]: 1 loads, 1 LSLICEs
1047 7 ale500 
   Number of local set/reset loads for net reset_o_c merged into GSR:  6
1048 10 ale500 
   Number of LSRs:  2
1049 
     Net reset_cnt[0]: 1 loads, 1 LSLICEs
1050 7 ale500 
     Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
1051 4 ale500 
   Number of nets driven by tri-state buffers:  0
1052 
   Top 10 highest fanout non-clock nets:
1053 10 ale500 
     Net cpu0/G_9: 93 loads
1054 
     Net state_o_c[5]: 85 loads
1055 
     Net state_o_c[4]: 79 loads
1056 
     Net state_o_c[1]: 78 loads
1057 9 ale500 
     Net cpu0/use_s_1: 75 loads
1058 10 ale500 
     Net state_o_c[2]: 73 loads
1059 
     Net cpu0/alu/rop_in[1]: 72 loads
1060 
     Net state_o_c[3]: 69 loads
1061 
     Net cpu0/alu/rop_in[0]: 67 loads
1062 
     Net cpu0/k_opcode[3]: 59 loads
1063 4 ale500 
 
1064 10 ale500 
   Number of warnings:  22
1065 4 ale500 
   Number of errors:    0
1066 
 
1067 
 
1068 10 ale500 
Total CPU Time: 1 secs
1069 
Total REAL Time: 5 secs
1070 
Peak Memory Usage: 196 MB
1071 4 ale500 
 
1072 
Dumping design to file P6809_P6809_map.ncd.
1073 
 
1074 
trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"
1075 
trce:  version Diamond (64-bit) 2.2.0.101
1076 
 
1077 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1078 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1079 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1080 
Copyright (c) 2001 Agere Systems   All rights reserved.
1081 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1082 
 
1083 
Loading design for application trce from file P6809_P6809_map.ncd.
1084 
Design name: CC3_top
1085 
NCD version: 3.2
1086 
Vendor:      LATTICE
1087 
Device:      LCMXO2-7000HE
1088 
Package:     TQFP144
1089 
Performance: 4
1090 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1091 
Package Status:                     Final          Version 1.36
1092 
Performance Hardware Data Status:   Final)         Version 23.4
1093 
Setup and Hold Report
1094 
 
1095 
--------------------------------------------------------------------------------
1096 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1097 10 ale500 
Thu Feb  6 15:35:22 2014
1098 4 ale500 
 
1099 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1100 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1101 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1102 
Copyright (c) 2001 Agere Systems   All rights reserved.
1103 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1104 
 
1105 
Report Information
1106 
------------------
1107 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1108 
Design file:     P6809_P6809_map.ncd
1109 
Preference file: P6809_P6809.prf
1110 
Device,speed:    LCMXO2-7000HE,4
1111 
Report level:    verbose report, limited to 1 item per preference
1112 
--------------------------------------------------------------------------------
1113 
 
1114 
BLOCK ASYNCPATHS
1115 
BLOCK RESETPATHS
1116 
--------------------------------------------------------------------------------
1117 
 
1118 
 
1119 
 
1120 
Timing summary (Setup):
1121 
---------------
1122 
 
1123 10 ale500 
Timing errors: 198  Score: 60114
1124 
Cumulative negative slack: 60114
1125 4 ale500 
 
1126 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9190 connections (95.5% coverage)
1127 4 ale500 
 
1128 
--------------------------------------------------------------------------------
1129 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1130 10 ale500 
Thu Feb  6 15:35:22 2014
1131 4 ale500 
 
1132 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1133 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1134 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1135 
Copyright (c) 2001 Agere Systems   All rights reserved.
1136 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1137 
 
1138 
Report Information
1139 
------------------
1140 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1141 
Design file:     P6809_P6809_map.ncd
1142 
Preference file: P6809_P6809.prf
1143 
Device,speed:    LCMXO2-7000HE,M
1144 
Report level:    verbose report, limited to 1 item per preference
1145 
--------------------------------------------------------------------------------
1146 
 
1147 
BLOCK ASYNCPATHS
1148 
BLOCK RESETPATHS
1149 
--------------------------------------------------------------------------------
1150 
 
1151 
 
1152 
 
1153 
Timing summary (Hold):
1154 
---------------
1155 
 
1156 
Timing errors: 0  Score: 0
1157 
Cumulative negative slack: 0
1158 
 
1159 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9531 connections (99.1% coverage)
1160 4 ale500 
 
1161 
 
1162 
 
1163 
Timing summary (Setup and Hold):
1164 
---------------
1165 
 
1166 10 ale500 
Timing errors: 198 (setup), 0 (hold)
1167 
Score: 60114 (setup), 0 (hold)
1168 
Cumulative negative slack: 60114 (60114+0)
1169 4 ale500 
--------------------------------------------------------------------------------
1170 
 
1171 
--------------------------------------------------------------------------------
1172 
 
1173 10 ale500 
Total time: 3 secs
1174 6 ale500 
 
1175 
mpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"
1176 
 
1177 
---- MParTrce Tool ----
1178 
Removing old design directory at request of -rem command line option to this program.
1179 10 ale500 
WARNING - mpartrce: Unable to remove old design directory.
1180 6 ale500 
Running par. Please wait . . .
1181 
 
1182 
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
1183 10 ale500 
Thu Feb  6 15:35:23 2014
1184 6 ale500 
 
1185 
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
1186 
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
1187 
Preference file: P6809_P6809.prf.
1188 
Placement level-cost: 5-1.
1189 
Routing Iterations: 6
1190 
 
1191 
Loading design for application par from file P6809_P6809_map.ncd.
1192 
Design name: CC3_top
1193 
NCD version: 3.2
1194 
Vendor:      LATTICE
1195 
Device:      LCMXO2-7000HE
1196 
Package:     TQFP144
1197 
Performance: 4
1198 
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1199 
Package Status:                     Final          Version 1.36
1200 
Performance Hardware Data Status:   Final)         Version 23.4
1201 
License checked out.
1202 
 
1203 
 
1204 
Ignore Preference Error(s):  True
1205 
Device utilization summary:
1206 
 
1207 10 ale500 
   PIO (prelim)   69+4(JTAG)/336     20% used
1208 
                  69+4(JTAG)/115     60% bonded
1209 7 ale500 
   IOLOGIC           10/336           2% used
1210 6 ale500 
 
1211 10 ale500 
   SLICE           1208/3432         35% used
1212 6 ale500 
 
1213 
   GSR                1/1           100% used
1214 7 ale500 
   EBR               10/26           38% used
1215 6 ale500 
 
1216 
 
1217 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
1218 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
1219 10 ale500 
Number of Signals: 2917
1220 
Number of Connections: 9622
1221 6 ale500 
 
1222 
Pin Constraint Summary:
1223 10 ale500 
   68 out of 68 pins locked (100% locked).
1224 6 ale500 
 
1225 
The following 1 signal is selected to use the primary clock routing resources:
1226 10 ale500 
    cpu_clkgen (driver: clk40_i, clk load #: 367)
1227 6 ale500 
 
1228 
 
1229 10 ale500 
The following 6 signals are selected to use the secondary clock routing resources:
1230 
    cpu0/G_9 (driver: cpu0/SLICE_764, clk load #: 0, sr load #: 0, ce load #: 80)
1231 
    cpu0/PC_1_sqmuxa_2_RNIK4633 (driver: cpu0/regs/SLICE_982, clk load #: 0, sr load #: 0, ce load #: 37)
1232 
    cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1 (driver: cpu0/regs/SLICE_322, clk load #: 0, sr load #: 0, ce load #: 25)
1233 
    cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3 (driver: cpu0/regs/SLICE_927, clk load #: 0, sr load #: 0, ce load #: 25)
1234 
    cpu0/regs/cff_1_sqmuxa_2_RNI1FDN (driver: cpu0/regs/SLICE_1258, clk load #: 0, sr load #: 0, ce load #: 18)
1235 
    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_754, clk load #: 0, sr load #: 0, ce load #: 16)
1236 6 ale500 
 
1237 7 ale500 
Signal reset_o_c is selected as Global Set/Reset.
1238 10 ale500 
.
1239 6 ale500 
Starting Placer Phase 0.
1240 10 ale500 
...........
1241 
Finished Placer Phase 0.  REAL time: 9 secs
1242 6 ale500 
 
1243 
Starting Placer Phase 1.
1244 10 ale500 
.........................
1245 
Placer score = 922601.
1246 
Finished Placer Phase 1.  REAL time: 20 secs
1247 6 ale500 
 
1248 
Starting Placer Phase 2.
1249 
.
1250 10 ale500 
Placer score =  906811
1251 
Finished Placer Phase 2.  REAL time: 21 secs
1252 6 ale500 
 
1253 
 
1254 
------------------ Clock Report ------------------
1255 
 
1256 
Global Clock Resources:
1257 
  CLK_PIN    : 1 out of 8 (12%)
1258 
  PLL        : 0 out of 2 (0%)
1259 
  DCM        : 0 out of 2 (0%)
1260 
  DCC        : 0 out of 8 (0%)
1261 
 
1262 
Quadrants All (TL, TR, BL, BR) - Global Clocks:
1263 10 ale500 
  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 367
1264 
  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_754" on site "R14C18D", clk load = 0, ce load = 16, sr load = 0
1265 
  SECONDARY "cpu0/G_9" from F0 on comp "cpu0/SLICE_764" on site "R21C18A", clk load = 0, ce load = 80, sr load = 0
1266 
  SECONDARY "cpu0/PC_1_sqmuxa_2_RNIK4633" from F0 on comp "cpu0/regs/SLICE_982" on site "R14C20A", clk load = 0, ce load = 37, sr load = 0
1267 
  SECONDARY "cpu0/regs/cff_1_sqmuxa_2_RNI1FDN" from F1 on comp "cpu0/regs/SLICE_1258" on site "R21C18C", clk load = 0, ce load = 18, sr load = 0
1268 
  SECONDARY "cpu0/regs/IY_1_sqmuxa_2_1_0_RNIVEBV1" from F1 on comp "cpu0/regs/SLICE_322" on site "R14C20C", clk load = 0, ce load = 25, sr load = 0
1269 
  SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNI2C2L3" from F1 on comp "cpu0/regs/SLICE_927" on site "R14C20B", clk load = 0, ce load = 25, sr load = 0
1270 6 ale500 
 
1271 
  PRIMARY  : 1 out of 8 (12%)
1272 10 ale500 
  SECONDARY: 6 out of 8 (75%)
1273 6 ale500 
 
1274 
Edge Clocks:
1275 
  No edge clock selected.
1276 
 
1277 
--------------- End of Clock Report ---------------
1278 
 
1279 
 
1280 
I/O Usage Summary (final):
1281 10 ale500 
   69 out of 336 (20.5%) PIO sites used.
1282 
   69 out of 115 (60.0%) bonded PIO sites used.
1283 
   Number of PIO comps: 69; differential: 0
1284 6 ale500 
   Number of Vref pins used: 0
1285 
 
1286 
I/O Bank Usage Summary:
1287 
+----------+----------------+------------+-----------+
1288 
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
1289 
+----------+----------------+------------+-----------+
1290 10 ale500 
| 0        | 11 / 28 ( 39%) | 2.5V       | -         |
1291 6 ale500 
| 1        | 13 / 29 ( 44%) | 2.5V       | -         |
1292 10 ale500 
| 2        | 20 / 29 ( 68%) | 2.5V       | -         |
1293 
| 3        | 8 / 9 ( 88%)   | 2.5V       | -         |
1294 
| 4        | 7 / 10 ( 70%)  | 2.5V       | -         |
1295 
| 5        | 10 / 10 (100%) | 2.5V       | -         |
1296 6 ale500 
+----------+----------------+------------+-----------+
1297 
 
1298 10 ale500 
Total placer CPU time: 15 secs
1299 6 ale500 
 
1300 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1301 
 
1302 10 ale500 
 
1303 6 ale500 
Starting router resource preassignment
1304 
 
1305 10 ale500 
Completed router resource preassignment. Real time: 26 secs
1306 6 ale500 
 
1307 10 ale500 
Start NBR router at Thu Feb 06 15:35:49 CET 2014
1308 6 ale500 
 
1309 
*****************************************************************
1310 
Info: NBR allows conflicts(one node used by more than one signal)
1311 
      in the earlier iterations. In each iteration, it tries to
1312 
      solve the conflicts while keeping the critical connections
1313 
      routed as short as possible. The routing process is said to
1314 
      be completed when no conflicts exist and all connections
1315 
      are routed.
1316 
Note: NBR uses a different method to calculate timing slacks. The
1317 
      worst slack and total negative slack may not be the same as
1318 
      that in TRCE report. You should always run TRCE to verify
1319 
      your design. Thanks.
1320 
*****************************************************************
1321 
 
1322 10 ale500 
Start NBR special constraint process at Thu Feb 06 15:35:49 CET 2014
1323 6 ale500 
 
1324 
Start NBR section for initial routing
1325 
Level 1, iteration 1
1326 10 ale500 
104(0.03%) conflicts; 8076(83.93%) untouched conns; 0 (nbr) score;
1327 
Estimated worst slack/total negative slack: 0.246ns/0.000ns; real time: 29 secs
1328 6 ale500 
Level 2, iteration 1
1329 10 ale500 
75(0.02%) conflicts; 7564(78.61%) untouched conns; 0 (nbr) score;
1330 
Estimated worst slack/total negative slack: 0.101ns/0.000ns; real time: 30 secs
1331 6 ale500 
Level 3, iteration 1
1332 10 ale500 
80(0.02%) conflicts; 6340(65.89%) untouched conns; 0 (nbr) score;
1333 
Estimated worst slack/total negative slack: 0.302ns/0.000ns; real time: 31 secs
1334 6 ale500 
Level 4, iteration 1
1335 10 ale500 
428(0.11%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1336 
Estimated worst slack/total negative slack: 0.257ns/0.000ns; real time: 34 secs
1337 6 ale500 
 
1338 10 ale500 
Info: Initial congestion level at 75% usage is 3
1339 
Info: Initial congestion area  at 75% usage is 41 (4.10%)
1340 6 ale500 
 
1341 
Start NBR section for normal routing
1342 
Level 1, iteration 1
1343 10 ale500 
11(0.00%) conflicts; 624(6.49%) untouched conns; 0 (nbr) score;
1344 
Estimated worst slack/total negative slack: 0.167ns/0.000ns; real time: 35 secs
1345 6 ale500 
Level 4, iteration 1
1346 10 ale500 
131(0.03%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1347 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 37 secs
1348 6 ale500 
Level 4, iteration 2
1349 10 ale500 
62(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1350 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs
1351 6 ale500 
Level 4, iteration 3
1352 10 ale500 
24(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1353 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs
1354 6 ale500 
Level 4, iteration 4
1355 10 ale500 
13(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1356 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 38 secs
1357 6 ale500 
Level 4, iteration 5
1358 10 ale500 
5(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1359 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs
1360 6 ale500 
Level 4, iteration 6
1361 10 ale500 
3(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1362 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs
1363 6 ale500 
Level 4, iteration 7
1364 9 ale500 
2(0.00%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1365 10 ale500 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs
1366 6 ale500 
Level 4, iteration 8
1367 9 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
1368 10 ale500 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs
1369 6 ale500 
 
1370 
Start NBR section for re-routing
1371 
Level 4, iteration 1
1372 9 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score;
1373 10 ale500 
Estimated worst slack/total negative slack: 0.251ns/0.000ns; real time: 39 secs
1374 6 ale500 
 
1375 
Start NBR section for post-routing
1376 
 
1377 
End NBR router with 0 unrouted connection
1378 
 
1379 
NBR Summary
1380 
-----------
1381 
  Number of unrouted connections : 0 (0.00%)
1382 9 ale500 
  Number of connections with timing violations : 0 (0.00%)
1383 10 ale500 
  Estimated worst slack : 0.251ns
1384 9 ale500 
  Timing score : 0
1385 6 ale500 
-----------
1386 
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
1387 
 
1388 
 
1389 
 
1390 9 ale500 
Hold time optimization iteration 0:
1391 
All hold time violations have been successfully corrected in speed grade M
1392 6 ale500 
 
1393 10 ale500 
Total CPU time 31 secs
1394 
Total REAL time: 47 secs
1395 6 ale500 
Completely routed.
1396 10 ale500 
End of route.  9622 routed (100.00%); 0 unrouted.
1397 6 ale500 
Checking DRC ...
1398 
No errors found.
1399 
 
1400 
Hold time timing score: 0, hold timing errors: 0
1401 
 
1402 9 ale500 
Timing score: 0
1403 6 ale500 
 
1404 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1405 
 
1406 
 
1407 
PAR_SUMMARY::Run status = completed
1408 
PAR_SUMMARY::Number of unrouted conns = 0
1409 10 ale500 
PAR_SUMMARY::Worst  slack> = 0.251
1410 9 ale500 
PAR_SUMMARY::Timing score> = 0.000
1411 10 ale500 
PAR_SUMMARY::Worst  slack> = 0.217
1412 9 ale500 
PAR_SUMMARY::Timing score> = 0.000
1413 6 ale500 
 
1414 10 ale500 
Total CPU  time to completion: 32 secs
1415 
Total REAL time to completion: 48 secs
1416 6 ale500 
 
1417 
par done!
1418 
 
1419 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1420 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1421 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1422 
Copyright (c) 2001 Agere Systems   All rights reserved.
1423 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1424 
Exiting par with exit code 0
1425 
Exiting mpartrce with exit code 0
1426 
 
1427 
trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"
1428 
trce:  version Diamond (64-bit) 2.2.0.101
1429 
 
1430 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1431 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1432 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1433 
Copyright (c) 2001 Agere Systems   All rights reserved.
1434 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1435 
 
1436 
Loading design for application trce from file P6809_P6809.ncd.
1437 
Design name: CC3_top
1438 
NCD version: 3.2
1439 
Vendor:      LATTICE
1440 
Device:      LCMXO2-7000HE
1441 
Package:     TQFP144
1442 
Performance: 4
1443 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1444 
Package Status:                     Final          Version 1.36
1445 
Performance Hardware Data Status:   Final)         Version 23.4
1446 
Setup and Hold Report
1447 
 
1448 
--------------------------------------------------------------------------------
1449 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1450 10 ale500 
Thu Feb  6 15:36:11 2014
1451 6 ale500 
 
1452 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1453 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1454 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1455 
Copyright (c) 2001 Agere Systems   All rights reserved.
1456 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1457 
 
1458 
Report Information
1459 
------------------
1460 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1461 
Design file:     P6809_P6809.ncd
1462 
Preference file: P6809_P6809.prf
1463 
Device,speed:    LCMXO2-7000HE,4
1464 
Report level:    verbose report, limited to 10 items per preference
1465 
--------------------------------------------------------------------------------
1466 
 
1467 
BLOCK ASYNCPATHS
1468 
BLOCK RESETPATHS
1469 
--------------------------------------------------------------------------------
1470 
 
1471 
 
1472 
 
1473 
Timing summary (Setup):
1474 
---------------
1475 
 
1476 9 ale500 
Timing errors: 0  Score: 0
1477 
Cumulative negative slack: 0
1478 6 ale500 
 
1479 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
1480 6 ale500 
 
1481 
--------------------------------------------------------------------------------
1482 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1483 10 ale500 
Thu Feb  6 15:36:12 2014
1484 6 ale500 
 
1485 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1486 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1487 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1488 
Copyright (c) 2001 Agere Systems   All rights reserved.
1489 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1490 
 
1491 
Report Information
1492 
------------------
1493 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1494 
Design file:     P6809_P6809.ncd
1495 
Preference file: P6809_P6809.prf
1496 
Device,speed:    LCMXO2-7000HE,m
1497 
Report level:    verbose report, limited to 10 items per preference
1498 
--------------------------------------------------------------------------------
1499 
 
1500 
BLOCK ASYNCPATHS
1501 
BLOCK RESETPATHS
1502 
--------------------------------------------------------------------------------
1503 
 
1504 
 
1505 
 
1506 
Timing summary (Hold):
1507 
---------------
1508 
 
1509 
Timing errors: 0  Score: 0
1510 
Cumulative negative slack: 0
1511 
 
1512 10 ale500 
Constraints cover 1107881 paths, 1 nets, and 9532 connections (99.1% coverage)
1513 6 ale500 
 
1514 
 
1515 
 
1516 
Timing summary (Setup and Hold):
1517 
---------------
1518 
 
1519 9 ale500 
Timing errors: 0 (setup), 0 (hold)
1520 
Score: 0 (setup), 0 (hold)
1521 
Cumulative negative slack: 0 (0+0)
1522 6 ale500 
--------------------------------------------------------------------------------
1523 
 
1524 
--------------------------------------------------------------------------------
1525 
 
1526 
Total time: 0 secs
1527 10 ale500 
 
1528 
bitgen -f "P6809_P6809.t2b" -w "P6809_P6809.ncd" -jedec "P6809_P6809.prf"
1529 
 
1530 
 
1531 
BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101
1532 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1533 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1534 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1535 
Copyright (c) 2001 Agere Systems   All rights reserved.
1536 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1537 
 
1538 
 
1539 
Loading design for application Bitgen from file P6809_P6809.ncd.
1540 
Design name: CC3_top
1541 
NCD version: 3.2
1542 
Vendor:      LATTICE
1543 
Device:      LCMXO2-7000HE
1544 
Package:     TQFP144
1545 
Performance: 4
1546 
Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1547 
Package Status:                     Final          Version 1.36
1548 
Performance Hardware Data Status:   Final)         Version 23.4
1549 
 
1550 
Running DRC.
1551 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
1552 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
1553 
DRC detected 0 errors and 0 warnings.
1554 
Reading Preference File from P6809_P6809.prf...
1555 
 
1556 
Preference Summary:
1557 
+---------------------------------+---------------------------------+
1558 
|  Preference                     |  Current Setting                |
1559 
+---------------------------------+---------------------------------+
1560 
|                         RamCfg  |                        Reset**  |
1561 
+---------------------------------+---------------------------------+
1562 
|                     MCCLK_FREQ  |                         2.08**  |
1563 
+---------------------------------+---------------------------------+
1564 
|                  CONFIG_SECURE  |                          OFF**  |
1565 
+---------------------------------+---------------------------------+
1566 
|                      JTAG_PORT  |                       ENABLE**  |
1567 
+---------------------------------+---------------------------------+
1568 
|                       SDM_PORT  |                      DISABLE**  |
1569 
+---------------------------------+---------------------------------+
1570 
|                 SLAVE_SPI_PORT  |                      DISABLE**  |
1571 
+---------------------------------+---------------------------------+
1572 
|                MASTER_SPI_PORT  |                      DISABLE**  |
1573 
+---------------------------------+---------------------------------+
1574 
|                       I2C_PORT  |                      DISABLE**  |
1575 
+---------------------------------+---------------------------------+
1576 
|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
1577 
+---------------------------------+---------------------------------+
1578 
|                  CONFIGURATION  |                          CFG**  |
1579 
+---------------------------------+---------------------------------+
1580 
|                COMPRESS_CONFIG  |                           ON**  |
1581 
+---------------------------------+---------------------------------+
1582 
|                        MY_ASSP  |                          OFF**  |
1583 
+---------------------------------+---------------------------------+
1584 
|               ONE_TIME_PROGRAM  |                          OFF**  |
1585 
+---------------------------------+---------------------------------+
1586 
|                 ENABLE_TRANSFR  |                      DISABLE**  |
1587 
+---------------------------------+---------------------------------+
1588 
|                  SHAREDEBRINIT  |                      DISABLE**  |
1589 
+---------------------------------+---------------------------------+
1590 
 *  Default setting.
1591 
 ** The specified setting matches the default setting.
1592 
 
1593 
 
1594 
Creating bit map...
1595 
 
1596 
Bitstream Status:   Final           Version 1.83
1597 
 
1598 
Saving bit stream in "P6809_P6809.jed".
1599 
 
1600 
===========
1601 
UFM Summary
1602 
===========
1603 
UFM Size:        2046 Pages (128*2046 Bits)
1604 
UFM Utilization: General Purpose Flash Memory
1605 
 
1606 
Available General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)
1607 
Initialized UFM Pages:                     0 Page
1608 
 

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