OpenCores
URL https://opencores.org/ocsvn/6809_6309_compatible_core/6809_6309_compatible_core/trunk

Subversion Repositories 6809_6309_compatible_core

[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [P6809/] [automake.log] - Blame information for rev 7

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 ale500 
 
2 
synpwrap -prj "P6809_P6809_synplify.tcl" -log "P6809_P6809.srf"
3 
 
4 
*****************************************************************
5 
 
6 
Warning: You are running on an unsupported platform
7 
  'synplify_pro' only supports Red Hat Enterprise Linux 4.0 and above
8 
 
9 
  current platform: CentOS release 6.4 (Final)
10 
Kernel \r on an \m
11 
 
12 
*****************************************************************
13 
 
14 
Running in Lattice mode
15 
 
16 
 
17 
Starting:    /usr/local/diamond/2.2_x64/synpbase/linux_a_64/mbin/synbatch
18 
Install:     /usr/local/diamond/2.2_x64/synpbase
19 7 ale500 
Date:        Sun Jan  5 08:22:47 2014
20 4 ale500 
Version:     G-2012.09L-SP1
21 
 
22 
Arguments:   -product synplify_pro  -batch P6809_P6809_synplify.tcl
23 
ProductType: synplify_pro
24 
 
25 
 
26 
 
27 
 
28 
 
29 
 
30 
log file: "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr"
31 
 
32 
 
33 
Running proj_1|P6809
34 
 
35 
Running Compile on proj_1|P6809
36 
 
37 
Running Compile Process on proj_1|P6809
38 
 
39 
Running Compile Input on proj_1|P6809
40 
 
41 
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/synwork/P6809_P6809_compiler.srs to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srs
42 
 
43 
compiler Completed with warnings
44 
Return Code: 1
45 6 ale500 
Run Time:00h:00m:04s
46 4 ale500 
 
47 
 
48 
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
49 
 
50 
Job Compile Process completed on proj_1|P6809
51 
 
52 
Running Premap on proj_1|P6809
53 
 
54 
premap Completed with warnings
55 
Return Code: 1
56 7 ale500 
Run Time:00h:00m:01s
57 4 ale500 
 
58 
 
59 
Job Compile completed on proj_1|P6809
60 
 
61 
Running Map on proj_1|P6809
62 
 
63 
Running Map & Optimize on proj_1|P6809
64 
 
65 
fpga_mapper Completed with warnings
66 
Return Code: 1
67 7 ale500 
Run Time:00h:00m:17s
68 4 ale500 
 
69 
 
70 
Job Map completed on proj_1|P6809
71 
 
72 
Copied /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srr to /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srf
73 
 
74 
Job Logic Synthesis completed on proj_1|P6809
75 
 
76 
TCL script complete: "P6809_P6809_synplify.tcl"
77 
 
78 
exit status=0
79 
 
80 
 
81 
Copyright (C) 1992-2013 Lattice Semiconductor Corporation. All rights reserved.
82 
Lattice Diamond Version 2.2.0.101
83 
Child process exit with 0.
84 
 
85 
==contents of P6809_P6809.srf
86 
#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
87 
#install: /usr/local/diamond/2.2_x64/synpbase
88 
#OS: Linux
89 
#Hostname: node01.pacito.sys
90 
 
91 
#Implementation: P6809
92 
 
93 
$ Start of Compile
94 7 ale500 
#Sun Jan  5 08:22:47 2014
95 4 ale500 
 
96 
Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
97 
@N|Running in 64-bit mode
98 
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
99 
 
100 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
101 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
102 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
103 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
104 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
105 
@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
106 
@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
107 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v"
108 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v"
109 
@I:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/defs.v"
110 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v"
111 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v"
112 7 ale500 
@W: CG289 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":698:23:698:27|Specified digits overflow the number's size
113 4 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v"
114 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v"
115 7 ale500 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v"
116 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v"
117 
@I::"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v"
118 4 ale500 
Verilog syntax check successful!
119 7 ale500 
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v changed - recompiling
120 
File /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v changed - recompiling
121 4 ale500 
Selecting top level module CC3_top
122 6 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":57:7:57:10|Synthesizing module alu8
123 4 ale500 
 
124 6 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":319:0:319:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
125 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:5:85:12|No assignment to wire cadd16_w
126 
 
127 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:15:85:22|No assignment to wire cadc16_w
128 
 
129 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:25:85:32|No assignment to wire csub16_w
130 
 
131 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":85:35:85:42|No assignment to wire csbc16_w
132 
 
133 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:12:184:13|No assignment to n8
134 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":184:20:184:21|No assignment to z8
135 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":301:0:301:5|Pruning register regq8[7:0]
136 
 
137 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":650:7:650:12|Synthesizing module mul8x8
138 
 
139 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":325:7:325:11|Synthesizing module alu16
140 
 
141 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":645:0:645:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
142 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":433:12:433:18|No assignment to wire q16_mul
143 
 
144 
@W: CL169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":561:0:561:5|Pruning register regq16[15:0]
145 
 
146 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":15:7:15:9|Synthesizing module alu
147 
 
148 
@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:18:32:28|Port-width mismatch for port a_in. Formal has width 16, Actual 8
149 
@W: CS263 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":32:30:32:40|Port-width mismatch for port b_in. Formal has width 16, Actual 8
150 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":7:7:7:14|Synthesizing module regblock
151 
 
152 6 ale500 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":243:0:243:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
153 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":9:7:9:17|Synthesizing module decode_regs
154 
 
155 5 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":131:7:131:15|Synthesizing module decode_op
156 4 ale500 
 
157 5 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":259:7:259:15|Synthesizing module decode_ea
158 4 ale500 
 
159 5 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":285:7:285:16|Synthesizing module decode_alu
160 4 ale500 
 
161 5 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":358:7:358:20|Synthesizing module test_condition
162 4 ale500 
 
163 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":10:7:10:16|Synthesizing module MC6809_cpu
164 
 
165 7 ale500 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":417:6:417:13|Ignoring system task $display
166 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":1033:0:1033:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
167 6 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":64:11:64:23|No assignment to wire alu8_o_result
168 4 ale500 
 
169 6 ale500 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":65:11:65:20|No assignment to wire alu8_o_CCR
170 
 
171 7 ale500 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
172 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
173 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_mem_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
174 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_tfr -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
175 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
176 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
177 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_exg -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
178 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_dest -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
179 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
180 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
181 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[3:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
182 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
183 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
184 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
185 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
186 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
187 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
188 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mul_cnt -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
189 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
190 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
191 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
192 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
193 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
194 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
195 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_forced_mem_size -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
196 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
197 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
198 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
199 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
200 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
201 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
202 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
203 
@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
204 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...
205 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...
206 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[1] is always 0, optimizing ...
207 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...
208 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 2 to 1 of next_mem_state[5:0]
209 6 ale500 
 
210 4 ale500 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
211 
 
212 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
213 
 
214 
@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
215 
 
216 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
217 
 
218 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
219 
 
220 7 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/fontrom.v":8:7:8:13|Synthesizing module fontrom
221 
 
222 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":8:7:8:15|Synthesizing module textmem4k
223 
 
224 
@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/textmem4k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
225 
 
226 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":2:7:2:13|Synthesizing module vgatext
227 
 
228 
@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":133:4:133:11|Ignoring system task $display
229 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":167:6:167:11|System task $write is not supported yet
230 
@N: CG512 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":174:6:174:11|System task $write is not supported yet
231 
@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":184:0:184:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
232 
@W: CG781 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":94:9:94:9|Undriven input DataInA on instance chars, tying to 0
233 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of redr[3:0] -- not in use ...
234 
 
235 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of greenr[3:0] -- not in use ...
236 
 
237 
@W: CL271 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Pruning bits 3 to 1 of bluer[3:0] -- not in use ...
238 
 
239 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element redr.
240 
@N: CL177 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Sharing sequential element greenr.
241 4 ale500 
@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":10:7:10:13|Synthesizing module CC3_top
242 
 
243 
@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":31:14:31:21|No assignment to clk_div2
244 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|No assignment to wire cpu1_addr_o
245 
 
246 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:40:37:51|No assignment to wire cpu1_data_in
247 
 
248 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|No assignment to wire cpu1_data_out
249 
 
250 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:23:38:29|No assignment to wire cpu1_we
251 
 
252 
@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":38:32:38:38|No assignment to wire cpu1_oe
253 
 
254 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":37:54:37:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
255 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":36:25:36:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
256 7 ale500 
@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/CC3_top.v":105:25:105:30|*Input cpu_we to expression [or] has undriven bits that are tied to 0 -- simulation mismatch possible.
257 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[0] is always 1, optimizing ...
258 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[1] is always 1, optimizing ...
259 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[2] is always 0, optimizing ...
260 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[3] is always 0, optimizing ...
261 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[4] is always 0, optimizing ...
262 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[5] is always 0, optimizing ...
263 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_x[6] is always 0, optimizing ...
264 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[0] is always 1, optimizing ...
265 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[1] is always 0, optimizing ...
266 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[2] is always 0, optimizing ...
267 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[3] is always 0, optimizing ...
268 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[4] is always 0, optimizing ...
269 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[5] is always 0, optimizing ...
270 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Register bit cur_y[6] is always 0, optimizing ...
271 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 3 of next_push_state[5:0]
272 4 ale500 
 
273 5 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":362:18:362:20|Input port bits 7 to 4 of CCR[7:0] are unused
274 4 ale500 
 
275 5 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":287:18:287:26|Input port bits 5 to 4 of postbyte0[7:0] are unused
276 4 ale500 
 
277 5 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/decoders.v":260:18:260:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
278 4 ale500 
 
279 6 ale500 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":329:18:329:20|Input port bits 7 to 4 of CCR[7:0] are unused
280 
 
281 
@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bits 15 to 13 of pipe0[15:0]
282 
 
283 
@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Register bit pipe0[12] is always 0, optimizing ...
284 
@W: CL260 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":660:0:660:5|Pruning register bit 12 of pipe0[12:0]
285 
 
286 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":59:19:59:22|Input port bits 15 to 8 of a_in[15:0] are unused
287 
 
288 
@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":60:19:60:22|Input port bits 15 to 8 of b_in[15:0] are unused
289 
 
290 
@W: CL159 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/alu16.v":58:12:58:17|Input clk_in is unused
291 4 ale500 
@END
292 6 ale500 
Process took 0h:00m:02s realtime, 0h:00m:02s cputime
293 7 ale500 
# Sun Jan  5 08:22:49 2014
294 4 ale500 
 
295 
###########################################################]
296 
Premap Report
297 
 
298 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
299 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
300 
Product Version G-2012.09L-SP1
301 
 
302 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
303 
 
304 
@L: /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt
305 
Printing clock  summary report in "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809_scck.rpt" file
306 
@N: MF248 |Running in 64-bit mode.
307 
@N: MF666 |Clock conversion enabled
308 
 
309 7 ale500 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)
310 4 ale500 
 
311 
 
312 7 ale500 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 95MB peak: 95MB)
313 4 ale500 
 
314 
 
315 7 ale500 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 109MB)
316 4 ale500 
 
317 
 
318 7 ale500 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 109MB peak: 111MB)
319 4 ale500 
 
320 
 
321 
 
322 
Clock Summary
323 
**************
324 
 
325 
Start                             Requested     Requested     Clock                              Clock
326 
Clock                             Frequency     Period        Type                               Group
327 
--------------------------------------------------------------------------------------------------------------------
328 
CC3_top|clk40_i                   1.0 MHz       1000.000      inferred                           Inferred_clkgroup_0
329 
CC3_top|cpu_clk_derived_clock     1.0 MHz       1000.000      derived (from CC3_top|clk40_i)     Inferred_clkgroup_0
330 
====================================================================================================================
331 
 
332 7 ale500 
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 83 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
333 4 ale500 
 
334 
syn_allowed_resources : blockrams=26  set on top level netlist CC3_top
335 
Finished Pre Mapping Phase.Pre-mapping successful!
336 
 
337 7 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 136MB)
338 4 ale500 
 
339 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
340 7 ale500 
# Sun Jan  5 08:22:51 2014
341 4 ale500 
 
342 
###########################################################]
343 
Map & Optimize Report
344 
 
345 
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
346 
Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
347 
Product Version G-2012.09L-SP1
348 
 
349 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
350 
 
351 
@N: MF248 |Running in 64-bit mode.
352 
@N: MF666 |Clock conversion enabled
353 
 
354 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
355 
 
356 
 
357 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
358 
 
359 
 
360 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
361 
 
362 
 
363 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 108MB)
364 
 
365 
 
366 
 
367 7 ale500 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
368 4 ale500 
 
369 
 
370 
Available hyper_sources - for debug and ip models
371 
        None Found
372 
 
373 
 
374 7 ale500 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 134MB peak: 136MB)
375 4 ale500 
 
376 7 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
377 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
378 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
379 5 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Found counter in view:work.regblock(verilog) inst PC[15:0]
380 7 ale500 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst x_cnt[6:0]
381 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst y_cnt[6:0]
382 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":118:0:118:5|Found counter in view:work.vgatext(verilog) inst line_cnt[3:0]
383 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst vsync_cnt[10:0]
384 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst blink_cnt[5:0]
385 
@N:"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/vgatext.v":51:0:51:5|Found counter in view:work.vgatext(verilog) inst hsync_cnt[10:0]
386 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
387 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
388 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
389 4 ale500 
 
390 7 ale500 
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 157MB)
391 4 ale500 
 
392 7 ale500 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_nmi[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
393 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_firq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
394 
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
395 4 ale500 
 
396 7 ale500 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 149MB peak: 158MB)
397 4 ale500 
 
398 
 
399 
 
400 7 ale500 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:02s; Memory used current: 148MB peak: 158MB)
401 4 ale500 
 
402 6 ale500 
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":237:2:237:3|Pipelining module un1_ea_reg_2[15:0]
403 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SU[15:0] pushed in.
404 7 ale500 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":287:0:287:5|Register k_ind_ea[7:0] pushed in.
405 5 ale500 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register SS[15:0] pushed in.
406 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IX[15:0] pushed in.
407 
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/regblock.v":182:0:182:5|Register IY[15:0] pushed in.
408 7 ale500 
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/rtl/verilog/MC6809_cpu.v":253:2:253:5|Found addmux in view:work.CC3_top(verilog) inst cpu0.alu.alu8.k_new_pc_4[15:0] from cpu0.un1_regs_o_pc[15:0]
409 4 ale500 
 
410 7 ale500 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
411 4 ale500 
 
412 
 
413 7 ale500 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
414 4 ale500 
 
415 
 
416 7 ale500 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:10s; Memory used current: 149MB peak: 158MB)
417 4 ale500 
 
418 
 
419 7 ale500 
Finished preparing to map (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:11s; Memory used current: 148MB peak: 158MB)
420 4 ale500 
 
421 
 
422 7 ale500 
Finished technology mapping (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 197MB peak: 226MB)
423 4 ale500 
 
424 
Pass             CPU time               Worst Slack             Luts / Registers
425 
------------------------------------------------------------
426 
Pass             CPU time               Worst Slack             Luts / Registers
427 
------------------------------------------------------------
428 
------------------------------------------------------------
429 
 
430 
 
431 7 ale500 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 165MB peak: 226MB)
432 4 ale500 
 
433 
@N: FX164 |The option to pack flops in the IOB has not been specified
434 
 
435 7 ale500 
Finished restoring hierarchy (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 166MB peak: 226MB)
436 4 ale500 
 
437 
 
438 
 
439 
#### START OF CLOCK OPTIMIZATION REPORT #####[
440 
 
441 6 ale500 
1 non-gated/non-generated clock tree(s) driving 504 clock pin(s) of sequential element(s)
442 4 ale500 
 
443 7 ale500 
281 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
444 4 ale500 
 
445 
=========================== Non-Gated/Non-Generated Clocks ============================
446 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
447 
---------------------------------------------------------------------------------------
448 6 ale500 
@K:CKID0001       clk40_i             port                   504        cpu_clk
449 4 ale500 
=======================================================================================
450 
===== Gated/Generated Clocks =====
451 
************** None **************
452 
----------------------------------
453 
==================================
454 
 
455 
 
456 
##### END OF CLOCK OPTIMIZATION REPORT ######]
457 
 
458 
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.srm
459 
 
460 7 ale500 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 169MB peak: 226MB)
461 4 ale500 
 
462 
Writing EDIF Netlist and constraint files
463 
G-2012.09L-SP1
464 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
465 
 
466 7 ale500 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:15s; CPU Time elapsed 0h:00m:15s; Memory used current: 173MB peak: 226MB)
467 4 ale500 
 
468 
@W: MT420 |Found inferred clock CC3_top|clk40_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk40_i"
469 
 
470 
 
471 
 
472 
##### START OF TIMING REPORT #####[
473 7 ale500 
# Timing Report written on Sun Jan  5 08:23:08 2014
474 4 ale500 
#
475 
 
476 
 
477 
Top view:               CC3_top
478 
Requested Frequency:    1.0 MHz
479 
Wire load mode:         top
480 
Paths requested:        5
481 
Constraint File(s):
482 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
483 
 
484 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
485 
 
486 
 
487 
 
488 
Performance Summary
489 
*******************
490 
 
491 
 
492 7 ale500 
Worst slack in design: 979.333
493 4 ale500 
 
494 
                    Requested     Estimated     Requested     Estimated                 Clock        Clock
495 
Starting Clock      Frequency     Frequency     Period        Period        Slack       Type         Group
496 
------------------------------------------------------------------------------------------------------------------------
497 7 ale500 
CC3_top|clk40_i     1.0 MHz       48.4 MHz      1000.000      20.667        979.333     inferred     Inferred_clkgroup_0
498 4 ale500 
========================================================================================================================
499 
 
500 
 
501 
 
502 
 
503 
 
504 
Clock Relationships
505 
*******************
506 
 
507 
Clocks                            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
508 
--------------------------------------------------------------------------------------------------------------------------
509 
Starting         Ending           |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
510 
--------------------------------------------------------------------------------------------------------------------------
511 7 ale500 
CC3_top|clk40_i  CC3_top|clk40_i  |  1000.000    979.333  |  No paths    -      |  No paths    -      |  No paths    -
512 4 ale500 
==========================================================================================================================
513 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
514 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
515 
 
516 
 
517 
 
518 
Interface Information
519 
*********************
520 
 
521 
No IO constraint found
522 
 
523 
 
524 
 
525 
====================================
526 
Detailed Report for Clock: CC3_top|clk40_i
527 
====================================
528 
 
529 
 
530 
 
531 
Starting Points with Worst Slack
532 
********************************
533 
 
534 7 ale500 
                         Starting                                                       Arrival
535 
Instance                 Reference           Type        Pin     Net                    Time        Slack
536 
                         Clock
537 
-----------------------------------------------------------------------------------------------------------
538 
cpu0.regs.SU_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_ea_reg_sn_N_3f     1.268       979.333
539 
cpu0.regs.SS_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SS_pipe_20             1.268       979.397
540 
cpu0.regs.SU_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_19             1.044       979.557
541 
cpu0.regs.SU_pipe_20     CC3_top|clk40_i     FD1P3AX     Q       SU_pipe_20             1.044       979.557
542 
cpu0.k_opcode[1]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[1]            1.387       979.562
543 
cpu0.k_opcode[0]         CC3_top|clk40_i     FD1P3AX     Q       k_opcode[0]            1.358       979.591
544 
cpu0.regs.SS_pipe_18     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[0]          1.044       979.621
545 
cpu0.regs.SS_pipe_19     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[0]          1.044       979.621
546 
cpu0.regs.SS_pipe_21     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m1f[1]          0.972       979.908
547 
cpu0.regs.SS_pipe_22     CC3_top|clk40_i     FD1P3AX     Q       un1_SS_m0f[1]          0.972       979.908
548 
===========================================================================================================
549 4 ale500 
 
550 
 
551 
Ending Points with Worst Slack
552 
******************************
553 
 
554 6 ale500 
                     Starting                                             Required
555 
Instance             Reference           Type        Pin     Net          Time         Slack
556 
                     Clock
557 
----------------------------------------------------------------------------------------------
558 7 ale500 
cpu0.regs.PC[14]     CC3_top|clk40_i     FD1P3AX     D       PC_s[14]     999.894      979.333
559 
cpu0.regs.PC[15]     CC3_top|clk40_i     FD1P3AX     D       PC_s[15]     999.894      979.333
560 
cpu0.regs.PC[12]     CC3_top|clk40_i     FD1P3AX     D       PC_s[12]     999.894      979.476
561 
cpu0.regs.PC[13]     CC3_top|clk40_i     FD1P3AX     D       PC_s[13]     999.894      979.476
562 
cpu0.regs.PC[10]     CC3_top|clk40_i     FD1P3AX     D       PC_s[10]     999.894      979.619
563 
cpu0.regs.PC[11]     CC3_top|clk40_i     FD1P3AX     D       PC_s[11]     999.894      979.619
564 
cpu0.regs.PC[8]      CC3_top|clk40_i     FD1P3AX     D       PC_s[8]      999.894      979.794
565 
cpu0.regs.PC[9]      CC3_top|clk40_i     FD1P3AX     D       PC_s[9]      999.894      979.794
566 
cpu0.regs.PC[6]      CC3_top|clk40_i     FD1P3AX     D       PC_s[6]      999.894      979.937
567 
cpu0.regs.PC[7]      CC3_top|clk40_i     FD1P3AX     D       PC_s[7]      999.894      979.937
568 6 ale500 
==============================================================================================
569 4 ale500 
 
570 
 
571 
 
572 
Worst Path Information
573 
***********************
574 
 
575 
 
576 
Path information for path number 1:
577 
      Requested Period:                      1000.000
578 6 ale500 
    - Setup time:                            0.106
579 4 ale500 
    + Clock delay at ending point:           0.000 (ideal)
580 6 ale500 
    = Required time:                         999.894
581 4 ale500 
 
582 7 ale500 
    - Propagation time:                      20.561
583 4 ale500 
    - Clock delay at starting point:         0.000 (ideal)
584 7 ale500 
    = Slack (critical) :                     979.333
585 4 ale500 
 
586 7 ale500 
    Number of logic level(s):                21
587 
    Starting point:                          cpu0.regs.SU_pipe_21 / Q
588 6 ale500 
    Ending point:                            cpu0.regs.PC[15] / D
589 4 ale500 
    The start point is clocked by            CC3_top|clk40_i [rising] on pin CK
590 
    The end   point is clocked by            CC3_top|clk40_i [rising] on pin CK
591 
 
592 7 ale500 
Instance / Net                                        Pin      Pin               Arrival     No. of
593 
Name                                     Type         Name     Dir     Delay     Time        Fan Out(s)
594 
-------------------------------------------------------------------------------------------------------
595 
cpu0.regs.SU_pipe_21                     FD1P3AX      Q        Out     1.268     1.268       -
596 
un1_ea_reg_sn_N_3f                       Net          -        -       -         -           17
597 
cpu0.regs.un1_ea_reg[0]                  ORCALUT4     C        In      0.000     1.268       -
598 
cpu0.regs.un1_ea_reg[0]                  ORCALUT4     Z        Out     1.153     2.421       -
599 
N_289                                    Net          -        -       -         -           3
600 
cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        B1       In      0.000     2.421       -
601 
cpu0.regs.un1_ea_reg_2_cry_0_0           CCU2D        COUT     Out     1.544     3.965       -
602 
un1_ea_reg_2_cry_0                       Net          -        -       -         -           1
603 
cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        CIN      In      0.000     3.965       -
604 
cpu0.regs.un1_ea_reg_2_cry_1_0           CCU2D        S1       Out     1.765     5.730       -
605 
SU[2]                                    Net          -        -       -         -           6
606 
cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     C        In      0.000     5.730       -
607 
cpu0.regs.ea_reg_3_am[2]                 ORCALUT4     Z        Out     1.017     6.747       -
608 
ea_reg_3_am[2]                           Net          -        -       -         -           1
609 
cpu0.regs.ea_reg_3[2]                    PFUMX        BLUT     In      0.000     6.747       -
610 
cpu0.regs.ea_reg_3[2]                    PFUMX        Z        Out     0.390     7.137       -
611 
ea_reg[2]                                Net          -        -       -         -           4
612 
cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     A        In      0.000     7.137       -
613 
cpu0.regs.un1_PC_1_0[2]                  ORCALUT4     Z        Out     1.017     8.154       -
614 
N_506                                    Net          -        -       -         -           1
615 
cpu0.regs.eamem_addr_cry_1_0             CCU2D        C1       In      0.000     8.154       -
616 
cpu0.regs.eamem_addr_cry_1_0             CCU2D        COUT     Out     1.544     9.698       -
617 
eamem_addr_cry_2                         Net          -        -       -         -           1
618 
cpu0.regs.eamem_addr_cry_3_0             CCU2D        CIN      In      0.000     9.698       -
619 
cpu0.regs.eamem_addr_cry_3_0             CCU2D        COUT     Out     0.143     9.841       -
620 
eamem_addr_cry_4                         Net          -        -       -         -           1
621 
cpu0.regs.eamem_addr_cry_5_0             CCU2D        CIN      In      0.000     9.841       -
622 
cpu0.regs.eamem_addr_cry_5_0             CCU2D        COUT     Out     0.143     9.984       -
623 
eamem_addr_cry_6                         Net          -        -       -         -           1
624 
cpu0.regs.eamem_addr_cry_7_0             CCU2D        CIN      In      0.000     9.984       -
625 
cpu0.regs.eamem_addr_cry_7_0             CCU2D        COUT     Out     0.143     10.127      -
626 
eamem_addr_cry_8                         Net          -        -       -         -           1
627 
cpu0.regs.eamem_addr_cry_9_0             CCU2D        CIN      In      0.000     10.127      -
628 
cpu0.regs.eamem_addr_cry_9_0             CCU2D        S0       Out     1.685     11.812      -
629 
regs_o_eamem_addr[9]                     Net          -        -       -         -           3
630 
cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     A        In      0.000     11.812      -
631 
cpu0.regs.eamem_addr_cry_9_0_RNISAU9     ORCALUT4     Z        Out     1.089     12.901      -
632 
datamux_o_dest_6[9]                      Net          -        -       -         -           2
633 
cpu0.regs.k_new_pc_1[9]                  ORCALUT4     A        In      0.000     12.901      -
634 
cpu0.regs.k_new_pc_1[9]                  ORCALUT4     Z        Out     1.017     13.917      -
635 
N_953                                    Net          -        -       -         -           1
636 
cpu0.regs.k_new_pc_2[9]                  ORCALUT4     A        In      0.000     13.917      -
637 
cpu0.regs.k_new_pc_2[9]                  ORCALUT4     Z        Out     1.017     14.934      -
638 
N_969                                    Net          -        -       -         -           1
639 
cpu0.regs.k_new_pc_5[9]                  ORCALUT4     A        In      0.000     14.934      -
640 
cpu0.regs.k_new_pc_5[9]                  ORCALUT4     Z        Out     1.017     15.951      -
641 
k_new_pc[9]                              Net          -        -       -         -           1
642 
cpu0.regs.PC_11_am[9]                    ORCALUT4     A        In      0.000     15.951      -
643 
cpu0.regs.PC_11_am[9]                    ORCALUT4     Z        Out     1.017     16.968      -
644 
PC_11_am[9]                              Net          -        -       -         -           1
645 
cpu0.regs.PC_11[9]                       PFUMX        BLUT     In      0.000     16.968      -
646 
cpu0.regs.PC_11[9]                       PFUMX        Z        Out     0.214     17.182      -
647 
PC_11[9]                                 Net          -        -       -         -           1
648 
cpu0.regs.PC_cry_0[8]                    CCU2D        B1       In      0.000     17.182      -
649 
cpu0.regs.PC_cry_0[8]                    CCU2D        COUT     Out     1.544     18.727      -
650 
PC_cry[9]                                Net          -        -       -         -           1
651 
cpu0.regs.PC_cry_0[10]                   CCU2D        CIN      In      0.000     18.727      -
652 
cpu0.regs.PC_cry_0[10]                   CCU2D        COUT     Out     0.143     18.869      -
653 
PC_cry[11]                               Net          -        -       -         -           1
654 
cpu0.regs.PC_cry_0[12]                   CCU2D        CIN      In      0.000     18.869      -
655 
cpu0.regs.PC_cry_0[12]                   CCU2D        COUT     Out     0.143     19.012      -
656 
PC_cry[13]                               Net          -        -       -         -           1
657 
cpu0.regs.PC_cry_0[14]                   CCU2D        CIN      In      0.000     19.012      -
658 
cpu0.regs.PC_cry_0[14]                   CCU2D        S1       Out     1.549     20.561      -
659 
PC_s[15]                                 Net          -        -       -         -           1
660 
cpu0.regs.PC[15]                         FD1P3AX      D        In      0.000     20.561      -
661 
=======================================================================================================
662 4 ale500 
 
663 
 
664 
 
665 
##### END OF TIMING REPORT #####]
666 
 
667 
---------------------------------------
668 
Resource Usage Report
669 
Part: lcmxo2_7000he-4
670 
 
671 7 ale500 
Register bits: 488 of 6864 (7%)
672 4 ale500 
PIC Latch:       0
673 
I/O cells:       49
674 7 ale500 
Block Rams : 10 of 26 (38%)
675 4 ale500 
 
676 
 
677 
Details:
678 7 ale500 
CCU2D:          196
679 
DP8KC:          10
680 
FD1P3AX:        441
681 4 ale500 
FD1P3DX:        6
682 6 ale500 
FD1P3IX:        1
683 7 ale500 
FD1S3AX:        28
684 
FD1S3IX:        2
685 4 ale500 
GSR:            1
686 
IB:             1
687 7 ale500 
INV:            20
688 
L6MUX21:        37
689 
OB:             40
690 
OBZ:            8
691 
OFS1P3DX:       9
692 
OFS1P3IX:       1
693 
ORCALUT4:       2025
694 
PFUMX:          273
695 4 ale500 
PUR:            1
696 7 ale500 
VHI:            10
697 
VLO:            16
698 
true:           6
699 4 ale500 
Mapper successful!
700 
 
701 7 ale500 
At Mapper Exit (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:16s; Memory used current: 43MB peak: 226MB)
702 4 ale500 
 
703 7 ale500 
Process took 0h:00m:16s realtime, 0h:00m:16s cputime
704 
# Sun Jan  5 08:23:08 2014
705 4 ale500 
 
706 
###########################################################]
707 
 
708 
 
709 
Synthesis exit by 0.
710 
 
711 
edif2ngd  -l "MachXO2" -d LCMXO2-7000HE -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -path "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi" "P6809_P6809.ngo"
712 
edif2ngd:  version Diamond (64-bit) 2.2.0.101
713 
 
714 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
715 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
716 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
717 
Copyright (c) 2001 Agere Systems   All rights reserved.
718 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
719 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
720 7 ale500 
  On or above line 310 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
721 4 ale500 
 
722 
WARNING - edif2ngd: Unsupported property is_pwr found - ignoring...
723 7 ale500 
  On or above line 318 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
724 4 ale500 
 
725 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
726 7 ale500 
  On or above line 1832 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
727 4 ale500 
 
728 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
729 7 ale500 
  On or above line 4556 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
730 4 ale500 
 
731 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
732 7 ale500 
  On or above line 9109 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
733 4 ale500 
 
734 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
735 7 ale500 
  On or above line 9904 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
736 4 ale500 
 
737 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
738 7 ale500 
  On or above line 10621 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
739 4 ale500 
 
740 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
741 7 ale500 
  On or above line 10919 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
742 4 ale500 
 
743 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
744 7 ale500 
  On or above line 11654 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
745 4 ale500 
 
746 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
747 7 ale500 
  On or above line 12094 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
748 4 ale500 
 
749 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
750 7 ale500 
  On or above line 13053 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
751 4 ale500 
 
752 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
753 7 ale500 
  On or above line 15901 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
754 4 ale500 
 
755 6 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
756 7 ale500 
  On or above line 28685 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
757 6 ale500 
 
758 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
759 7 ale500 
  On or above line 31454 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
760 6 ale500 
 
761 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
762 7 ale500 
  On or above line 34211 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
763 6 ale500 
 
764 7 ale500 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
765 
  On or above line 34629 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
766 
 
767 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
768 
  On or above line 40141 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
769 
 
770 
WARNING - edif2ngd: Unsupported property orig_inst_of found - ignoring...
771 
  On or above line 40954 in file /home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809/P6809_P6809.edi
772 
 
773 4 ale500 
Writing the design to P6809_P6809.ngo...
774 
 
775 
 
776 
ngdbuild  -a "MachXO2" -d LCMXO2-7000HE  -p "/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data"  -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809" -p "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice"  "P6809_P6809.ngo" "P6809_P6809.ngd"
777 
ngdbuild:  version Diamond (64-bit) 2.2.0.101
778 
 
779 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
780 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
781 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
782 
Copyright (c) 2001 Agere Systems   All rights reserved.
783 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
784 
Reading 'P6809_P6809.ngo' ...
785 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00a/data/xo2alib.ngl'...
786 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/xo2c00/data/xo2clib.ngl'...
787 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/mg5g00/data/mg5glib.ngl'...
788 
Loading NGL library '/usr/local/diamond/2.2_x64/ispfpga/or5g00/data/orc5glib.ngl'...
789 
 
790 
 
791 
Running DRC...
792 
 
793 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_COUT' has no load
794 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_8_0_S1' has no load
795 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S0' has no load
796 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_6_cry_0_0_S1' has no load
797 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_COUT' has no load
798 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_s_15_0_S1' has no load
799 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S0' has no load
800 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_cry_0_0_S1' has no load
801 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_8_0_COUT' has no load
802 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S0' has no load
803 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe1_1_4_cry_1_0_S1' has no load
804 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_8_0_COUT' has no load
805 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S0' has no load
806 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_4_cry_1_0_S1' has no load
807 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_8_0_COUT' has no load
808 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S0' has no load
809 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_5_cry_1_0_S1' has no load
810 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_COUT' has no load
811 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_s_11_0_S1' has no load
812 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S0' has no load
813 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/mulu/pipe0_1_cry_2_0_S1' has no load
814 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_15_0_COUT' has no load
815 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sbc16_w_cry_0_0_S0' has no load
816 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_15_0_COUT' has no load
817 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S0' has no load
818 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/sub16_w_cry_0_0_S1' has no load
819 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_15_0_COUT' has no load
820 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S0' has no load
821 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/add16_w_cry_0_0_S1' has no load
822 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_COUT' has no load
823 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_s_15_0_S1' has no load
824 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S0' has no load
825 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_13_0_S1' has no load
826 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S0' has no load
827 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_11_0_S1' has no load
828 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S0' has no load
829 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_9_0_S1' has no load
830 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S0' has no load
831 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_7_0_S1' has no load
832 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S0' has no load
833 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_5_0_S1' has no load
834 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S0' has no load
835 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_3_0_S1' has no load
836 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S0' has no load
837 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_1_0_S1' has no load
838 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S0' has no load
839 
WARNING - ngdbuild: logical net 'cpu0/alu/alu16/adc16_w_cry_0_0_S1' has no load
840 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_7_0_COUT' has no load
841 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S0' has no load
842 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sub8_w_cry_0_0_S1' has no load
843 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_7_0_COUT' has no load
844 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/sbc8_w_cry_0_0_S0' has no load
845 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_7_0_COUT' has no load
846 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S0' has no load
847 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/add8_w_cry_0_0_S1' has no load
848 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_COUT' has no load
849 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_s_7_0_S1' has no load
850 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S0' has no load
851 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/neg8_w_cry_0_0_S1' has no load
852 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_COUT' has no load
853 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_s_7_0_S1' has no load
854 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S0' has no load
855 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_5_0_S1' has no load
856 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S0' has no load
857 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_3_0_S1' has no load
858 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S0' has no load
859 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_1_0_S1' has no load
860 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S0' has no load
861 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/adc8_w_cry_0_0_S1' has no load
862 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_COUT' has no load
863 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_s_15_0_S1' has no load
864 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S0' has no load
865 
WARNING - ngdbuild: logical net 'cpu0/alu/alu8/k_new_pc_4_cry_0_0_S1' has no load
866 4 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_COUT' has no load
867 
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_s_15_0_S1' has no load
868 
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S0' has no load
869 
WARNING - ngdbuild: logical net 'cpu0/regs/eamem_addr_cry_0_0_S1' has no load
870 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_COUT' has no load
871 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_s_15_0_S1' has no load
872 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S0' has no load
873 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_2_cry_0_0_S1' has no load
874 7 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_COUT' has no load
875 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_s_15_0_S1' has no load
876 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S0' has no load
877 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_ea_reg_1_cry_0_0_S1' has no load
878 6 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_COUT' has no load
879 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_s_15_0_S1' has no load
880 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S0' has no load
881 
WARNING - ngdbuild: logical net 'cpu0/regs/un1_SS_1_cry_0_0_S1' has no load
882 4 ale500 
WARNING - ngdbuild: logical net 'cpu0/regs/PC_cry_0_COUT[14]' has no load
883 
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S0' has no load
884 
WARNING - ngdbuild: logical net 'cpu0/regs/PC_lcry_0_S1' has no load
885 7 ale500 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_COUT' has no load
886 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_s_6_0_S1' has no load
887 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S0' has no load
888 
WARNING - ngdbuild: logical net 'textctrl/yptr_5_cry_1_0_S1' has no load
889 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_7_0_COUT' has no load
890 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S0' has no load
891 
WARNING - ngdbuild: logical net 'textctrl/yptr_4_cry_2_0_S1' has no load
892 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_10_0_COUT' has no load
893 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S0' has no load
894 
WARNING - ngdbuild: logical net 'textctrl/yptr_cry_5_0_S1' has no load
895 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_COUT[5]' has no load
896 
WARNING - ngdbuild: logical net 'textctrl/x_cnt_cry_0_S0[0]' has no load
897 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_COUT[5]' has no load
898 
WARNING - ngdbuild: logical net 'textctrl/y_cnt_cry_0_S0[0]' has no load
899 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_COUT[9]' has no load
900 
WARNING - ngdbuild: logical net 'textctrl/vsync_cnt_cry_0_S0[0]' has no load
901 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_COUT[5]' has no load
902 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_s_0_S1[5]' has no load
903 
WARNING - ngdbuild: logical net 'textctrl/blink_cnt_cry_0_S0[0]' has no load
904 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_COUT[9]' has no load
905 
WARNING - ngdbuild: logical net 'textctrl/hsync_cnt_cry_0_S0[0]' has no load
906 4 ale500 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_COUT' has no load
907 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_s_15_0_S1' has no load
908 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S0' has no load
909 
WARNING - ngdbuild: logical net 'cpu0/un1_k_cpu_addr_1_cry_0_0_S1' has no load
910 7 ale500 
WARNING - ngdbuild: DRC complete with 117 warnings
911 4 ale500 
 
912 
Design Results:
913 7 ale500 
   3125 blocks expanded
914 4 ale500 
complete the first expansion
915 
Writing 'P6809_P6809.ngd' ...
916 
 
917 
map -a "MachXO2" -p LCMXO2-7000HE -t TQFP144 -s 4 -oc Commercial   "P6809_P6809.ngd" -o "P6809_P6809_map.ncd" -pr "P6809_P6809.prf" -mp "P6809_P6809.mrp" "/home/pacito/02_Elektronik/020_V6809/6809/opencores/trunk/syn/lattice/P6809.lpf" -c 0
918 
map:  version Diamond (64-bit) 2.2.0.101
919 
 
920 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
921 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
922 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
923 
Copyright (c) 2001 Agere Systems   All rights reserved.
924 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
925 
   Process the file: P6809_P6809.ngd
926 
   Picdevice="LCMXO2-7000HE"
927 
 
928 
   Pictype="TQFP144"
929 
 
930 
   Picspeed=4
931 
 
932 
   Remove unused logic
933 
 
934 
   Do not produce over sized NCDs.
935 
 
936 
Part used: LCMXO2-7000HETQFP144, Performance used: 4.
937 
Loading device for application map from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
938 
Package Status:                     Final          Version 1.36
939 
 
940 
Running general design DRC...
941 
Removing unused logic...
942 
Optimizing...
943 
7 CCU2 constant inputs absorbed.
944 7 ale500 
WARNING - map: Using local reset signal 'reset_o_c' to infer global GSR net.
945 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
946 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
947 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
948 
WARNING - map: The reset of EBR 'textctrl/chars/textmem4k_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
949 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_0_3' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
950 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_1_2' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
951 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_2_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
952 
WARNING - map: The reset of EBR 'textctrl/font/fontrom_0_3_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
953 4 ale500 
WARNING - map: The reset of EBR 'bios/bios2k_0_1_0' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
954 
WARNING - map: The reset of EBR 'bios/bios2k_0_0_1' cannot be controlled. The local reset is not connected to any control signal and set to GND. The global reset is disabled via GSR property. To control the EBR reset, either connect the local reset to a control signal or force the GSR property to be enabled.
955 
 
956 
 
957 
 
958 
Design Summary:
959 7 ale500 
   Number of registers:    488
960 
      PFU registers:    478
961 
      PIO registers:    10
962 
   Number of SLICEs:          1219 out of  3432 (36%)
963 4 ale500 
      SLICEs(logic/ROM):       858 out of   858 (100%)
964 7 ale500 
      SLICEs(logic/ROM/RAM):   361 out of  2574 (14%)
965 4 ale500 
          As RAM:            0 out of  2574 (0%)
966 7 ale500 
          As Logic/ROM:    361 out of  2574 (14%)
967 
   Number of logic LUT4s:     2044
968 4 ale500 
   Number of distributed RAM:   0 (0 LUT4s)
969 7 ale500 
   Number of ripple logic:    196 (392 LUT4s)
970 4 ale500 
   Number of shift registers:   0
971 7 ale500 
   Total number of LUT4s:     2436
972 4 ale500 
   Number of PIO sites used: 49 + 4(JTAG) out of 115 (46%)
973 7 ale500 
   Number of block RAMs:  10 out of 26 (38%)
974 4 ale500 
   Number of GSRs:  1 out of 1 (100%)
975 
   EFB used :       No
976 
   JTAG used :      No
977 
   Readback used :  No
978 
   Oscillator used :  No
979 
   Startup used :   No
980 
   POR :            On
981 
   Bandgap :        On
982 
   Number of Power Controller:  0 out of 1 (0%)
983 
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
984 
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
985 
   Number of DCCA:  0 out of 8 (0%)
986 
   Number of DCMA:  0 out of 2 (0%)
987 
   Number of PLLs:  0 out of 2 (0%)
988 
   Number of DQSDLLs:  0 out of 2 (0%)
989 
   Number of CLKDIVC:  0 out of 4 (0%)
990 
   Number of ECLKSYNCA:  0 out of 4 (0%)
991 
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
992 
   Notes:-
993 
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic)
994 
      2. Number of logic LUT4s does not include count of distributed RAM and ripple logic.
995 
   Number of clocks:  1
996 7 ale500 
     Net cpu_clkgen: 305 loads, 305 rising, 0 falling (Driver: PIO clk40_i )
997 
   Number of Clock Enables:  35
998 
     Net cpu_clk: 97 loads, 97 LSLICEs
999 6 ale500 
     Net leds_r_cnv[0]: 8 loads, 0 LSLICEs
1000 7 ale500 
     Net textctrl/un1_CPU_OE_EN_0_a2: 8 loads, 0 LSLICEs
1001 
     Net textctrl/line_cnte: 2 loads, 2 LSLICEs
1002 
     Net textctrl/y_cnte: 4 loads, 4 LSLICEs
1003 
     Net textctrl/x_cnte: 4 loads, 4 LSLICEs
1004 
     Net textctrl/N_4: 6 loads, 6 LSLICEs
1005 
     Net textctrl/tshift_1_sqmuxa: 4 loads, 4 LSLICEs
1006 
     Net textctrl/N_103_i_0: 4 loads, 4 LSLICEs
1007 
     Net textctrl/vsync_cnt_0_sqmuxa_4: 4 loads, 4 LSLICEs
1008 
     Net un1_bios_en_0_a2: 4 loads, 0 LSLICEs
1009 
     Net cpu0/un1_state_23_RNIKLF8L: 3 loads, 3 LSLICEs
1010 
     Net cpu0/un1_state_53_RNIKL6IT: 4 loads, 4 LSLICEs
1011 
     Net cpu0/k_memhi_0_sqmuxa_RNIS2L63: 4 loads, 4 LSLICEs
1012 6 ale500 
     Net cpu0/k_ealo_cnv_0[0]: 16 loads, 16 LSLICEs
1013 7 ale500 
     Net cpu0/un1_state_12_1_RNIGGP7P: 4 loads, 4 LSLICEs
1014 
     Net cpu0/un1_cpu_reset_6_0_a3_1_RNI3DL77: 3 loads, 3 LSLICEs
1015 
     Net cpu0/next_state10_RNIVT0PU: 2 loads, 2 LSLICEs
1016 
     Net cpu0/un1_dest_reg44_1_0_a2_1_0_RNIUSPTD1: 8 loads, 8 LSLICEs
1017 
     Net cpu0/un1_cpu_reset_5_0_a3_2_RNIUKBUL: 2 loads, 2 LSLICEs
1018 
     Net cpu0/un1_state_82_1_RNICEGM2: 4 loads, 4 LSLICEs
1019 
     Net cpu0/un1_cpu_reset_10_0_a3_0_0_RNIDMV84: 2 loads, 2 LSLICEs
1020 5 ale500 
     Net cpu0/regs/eflag_RNO: 1 loads, 1 LSLICEs
1021 7 ale500 
     Net cpu0/un1_state_18_2_RNI7CC51: 4 loads, 4 LSLICEs
1022 
     Net cpu0/un1_state_56_RNI0KNU2: 8 loads, 8 LSLICEs
1023 
     Net cpu0/regs/cff_0_sqmuxa_1_0_RNI212L: 7 loads, 7 LSLICEs
1024 
     Net cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1: 17 loads, 17 LSLICEs
1025 
     Net cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1: 19 loads, 19 LSLICEs
1026 
     Net cpu0/regs/DP_1_sqmuxa_0_RNI70L71: 5 loads, 5 LSLICEs
1027 
     Net cpu0/regs/ACCB_0_sqmuxa_1_RNIHOBV: 4 loads, 4 LSLICEs
1028 
     Net cpu0/regs/ACCB45_RNIMT5N2: 4 loads, 4 LSLICEs
1029 
     Net cpu0/un1_state_18_2_RNI3MPQ: 4 loads, 4 LSLICEs
1030 
     Net cpu0/k_ofshi_cnv[0]: 4 loads, 4 LSLICEs
1031 
     Net cpu0/state_RNIGVAO2[5]: 4 loads, 4 LSLICEs
1032 
     Net cpu0/un1_state_84_1_RNITNQJ9: 4 loads, 4 LSLICEs
1033 
   Number of local set/reset loads for net reset_o_c merged into GSR:  6
1034 
   Number of LSRs:  2
1035 
     Net textctrl.vsync_cnt[10]: 3 loads, 2 LSLICEs
1036 
     Net cpu0/G_7: 1 loads, 1 LSLICEs
1037 4 ale500 
   Number of nets driven by tri-state buffers:  0
1038 
   Top 10 highest fanout non-clock nets:
1039 7 ale500 
     Net cpu_clk: 117 loads
1040 
     Net state_o_c[1]: 103 loads
1041 
     Net cpu0/dec_o_alu_opcode[0]: 92 loads
1042 
     Net state_o_c[4]: 81 loads
1043 
     Net state_o_c[2]: 74 loads
1044 
     Net cpu0/k_opcode[1]: 72 loads
1045 
     Net cpu0/dec_o_p1_mode[0]: 70 loads
1046 6 ale500 
     Net cpu0/dec_o_alu_opcode[4]: 66 loads
1047 7 ale500 
     Net cpu0/dec_o_alu_opcode[3]: 63 loads
1048 
     Net cpu0/k_opcode[3]: 63 loads
1049 4 ale500 
 
1050 7 ale500 
   Number of warnings:  11
1051 4 ale500 
   Number of errors:    0
1052 
 
1053 
 
1054 6 ale500 
Total CPU Time: 0 secs
1055 4 ale500 
Total REAL Time: 0 secs
1056 7 ale500 
Peak Memory Usage: 195 MB
1057 4 ale500 
 
1058 
Dumping design to file P6809_P6809_map.ncd.
1059 
 
1060 
trce -f "P6809_P6809.mt" -o "P6809_P6809.tw1" "P6809_P6809_map.ncd" "P6809_P6809.prf"
1061 
trce:  version Diamond (64-bit) 2.2.0.101
1062 
 
1063 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1064 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1065 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1066 
Copyright (c) 2001 Agere Systems   All rights reserved.
1067 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1068 
 
1069 
Loading design for application trce from file P6809_P6809_map.ncd.
1070 
Design name: CC3_top
1071 
NCD version: 3.2
1072 
Vendor:      LATTICE
1073 
Device:      LCMXO2-7000HE
1074 
Package:     TQFP144
1075 
Performance: 4
1076 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1077 
Package Status:                     Final          Version 1.36
1078 
Performance Hardware Data Status:   Final)         Version 23.4
1079 
Setup and Hold Report
1080 
 
1081 
--------------------------------------------------------------------------------
1082 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1083 7 ale500 
Sun Jan  5 08:23:12 2014
1084 4 ale500 
 
1085 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1086 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1087 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1088 
Copyright (c) 2001 Agere Systems   All rights reserved.
1089 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1090 
 
1091 
Report Information
1092 
------------------
1093 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1094 
Design file:     P6809_P6809_map.ncd
1095 
Preference file: P6809_P6809.prf
1096 
Device,speed:    LCMXO2-7000HE,4
1097 
Report level:    verbose report, limited to 1 item per preference
1098 
--------------------------------------------------------------------------------
1099 
 
1100 
BLOCK ASYNCPATHS
1101 
BLOCK RESETPATHS
1102 
--------------------------------------------------------------------------------
1103 
 
1104 
 
1105 
 
1106 
Timing summary (Setup):
1107 
---------------
1108 
 
1109 7 ale500 
Timing errors: 1702  Score: 686102
1110 
Cumulative negative slack: 686102
1111 4 ale500 
 
1112 7 ale500 
Constraints cover 3270002 paths, 1 nets, and 9158 connections (96.1% coverage)
1113 4 ale500 
 
1114 
--------------------------------------------------------------------------------
1115 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1116 7 ale500 
Sun Jan  5 08:23:12 2014
1117 4 ale500 
 
1118 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1119 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1120 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1121 
Copyright (c) 2001 Agere Systems   All rights reserved.
1122 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1123 
 
1124 
Report Information
1125 
------------------
1126 
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o P6809_P6809.tw1 P6809_P6809_map.ncd P6809_P6809.prf
1127 
Design file:     P6809_P6809_map.ncd
1128 
Preference file: P6809_P6809.prf
1129 
Device,speed:    LCMXO2-7000HE,M
1130 
Report level:    verbose report, limited to 1 item per preference
1131 
--------------------------------------------------------------------------------
1132 
 
1133 
BLOCK ASYNCPATHS
1134 
BLOCK RESETPATHS
1135 
--------------------------------------------------------------------------------
1136 
 
1137 
 
1138 
 
1139 
Timing summary (Hold):
1140 
---------------
1141 
 
1142 
Timing errors: 0  Score: 0
1143 
Cumulative negative slack: 0
1144 
 
1145 7 ale500 
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
1146 4 ale500 
 
1147 
 
1148 
 
1149 
Timing summary (Setup and Hold):
1150 
---------------
1151 
 
1152 7 ale500 
Timing errors: 1702 (setup), 0 (hold)
1153 
Score: 686102 (setup), 0 (hold)
1154 
Cumulative negative slack: 686102 (686102+0)
1155 4 ale500 
--------------------------------------------------------------------------------
1156 
 
1157 
--------------------------------------------------------------------------------
1158 
 
1159 
Total time: 0 secs
1160 6 ale500 
 
1161 
mpartrce -p "P6809_P6809.p2t" -f "P6809_P6809.p3t" -tf "P6809_P6809.pt" "P6809_P6809_map.ncd" "P6809_P6809.ncd"
1162 
 
1163 
---- MParTrce Tool ----
1164 
Removing old design directory at request of -rem command line option to this program.
1165 
Running par. Please wait . . .
1166 
 
1167 
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
1168 7 ale500 
Sun Jan  5 08:23:12 2014
1169 6 ale500 
 
1170 
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
1171 
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
1172 
Preference file: P6809_P6809.prf.
1173 
Placement level-cost: 5-1.
1174 
Routing Iterations: 6
1175 
 
1176 
Loading design for application par from file P6809_P6809_map.ncd.
1177 
Design name: CC3_top
1178 
NCD version: 3.2
1179 
Vendor:      LATTICE
1180 
Device:      LCMXO2-7000HE
1181 
Package:     TQFP144
1182 
Performance: 4
1183 
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1184 
Package Status:                     Final          Version 1.36
1185 
Performance Hardware Data Status:   Final)         Version 23.4
1186 
License checked out.
1187 
 
1188 
 
1189 
Ignore Preference Error(s):  True
1190 
Device utilization summary:
1191 
 
1192 
   PIO (prelim)   49+4(JTAG)/336     14% used
1193 
                  49+4(JTAG)/115     42% bonded
1194 7 ale500 
   IOLOGIC           10/336           2% used
1195 6 ale500 
 
1196 7 ale500 
   SLICE           1219/3432         35% used
1197 6 ale500 
 
1198 
   GSR                1/1           100% used
1199 7 ale500 
   EBR               10/26           38% used
1200 6 ale500 
 
1201 
 
1202 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
1203 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
1204 7 ale500 
Number of Signals: 2800
1205 
Number of Connections: 9525
1206 6 ale500 
 
1207 
Pin Constraint Summary:
1208 
   49 out of 49 pins locked (100% locked).
1209 
 
1210 
The following 1 signal is selected to use the primary clock routing resources:
1211 7 ale500 
    cpu_clkgen (driver: clk40_i, clk load #: 305)
1212 6 ale500 
 
1213 
 
1214 7 ale500 
The following 4 signals are selected to use the secondary clock routing resources:
1215 
    cpu_clk (driver: SLICE_407, clk load #: 0, sr load #: 0, ce load #: 97)
1216 
    cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1 (driver: cpu0/SLICE_803, clk load #: 0, sr load #: 0, ce load #: 19)
1217 
    cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1 (driver: cpu0/SLICE_804, clk load #: 0, sr load #: 0, ce load #: 17)
1218 
    cpu0/k_ealo_cnv_0[0] (driver: cpu0/SLICE_793, clk load #: 0, sr load #: 0, ce load #: 16)
1219 6 ale500 
 
1220 7 ale500 
Signal reset_o_c is selected as Global Set/Reset.
1221 6 ale500 
Starting Placer Phase 0.
1222 
...........
1223 
Finished Placer Phase 0.  REAL time: 5 secs
1224 
 
1225 
Starting Placer Phase 1.
1226 
......................
1227 7 ale500 
Placer score = 869535.
1228 
Finished Placer Phase 1.  REAL time: 13 secs
1229 6 ale500 
 
1230 
Starting Placer Phase 2.
1231 
.
1232 7 ale500 
Placer score =  857738
1233 
Finished Placer Phase 2.  REAL time: 14 secs
1234 6 ale500 
 
1235 
 
1236 
------------------ Clock Report ------------------
1237 
 
1238 
Global Clock Resources:
1239 
  CLK_PIN    : 1 out of 8 (12%)
1240 
  PLL        : 0 out of 2 (0%)
1241 
  DCM        : 0 out of 2 (0%)
1242 
  DCC        : 0 out of 8 (0%)
1243 
 
1244 
Quadrants All (TL, TR, BL, BR) - Global Clocks:
1245 7 ale500 
  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 305
1246 
  SECONDARY "cpu_clk" from Q0 on comp "SLICE_407" on site "R21C20C", clk load = 0, ce load = 97, sr load = 0
1247 
  SECONDARY "cpu0/k_ealo_cnv_0[0]" from F1 on comp "cpu0/SLICE_793" on site "R25C35A", clk load = 0, ce load = 16, sr load = 0
1248 
  SECONDARY "cpu0/regs/IY_0_sqmuxa_1_RNI1CVH1" from F1 on comp "cpu0/SLICE_804" on site "R14C20A", clk load = 0, ce load = 17, sr load = 0
1249 
  SECONDARY "cpu0/regs/IX_0_sqmuxa_1_1_RNIGA2K1" from F1 on comp "cpu0/SLICE_803" on site "R14C18D", clk load = 0, ce load = 19, sr load = 0
1250 6 ale500 
 
1251 
  PRIMARY  : 1 out of 8 (12%)
1252 7 ale500 
  SECONDARY: 4 out of 8 (50%)
1253 6 ale500 
 
1254 
Edge Clocks:
1255 
  No edge clock selected.
1256 
 
1257 
--------------- End of Clock Report ---------------
1258 
 
1259 
 
1260 
I/O Usage Summary (final):
1261 
   49 out of 336 (14.6%) PIO sites used.
1262 
   49 out of 115 (42.6%) bonded PIO sites used.
1263 
   Number of PIO comps: 49; differential: 0
1264 
   Number of Vref pins used: 0
1265 
 
1266 
I/O Bank Usage Summary:
1267 
+----------+----------------+------------+-----------+
1268 
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
1269 
+----------+----------------+------------+-----------+
1270 
| 0        | 12 / 28 ( 42%) | 2.5V       | -         |
1271 
| 1        | 13 / 29 ( 44%) | 2.5V       | -         |
1272 
| 2        | 23 / 29 ( 79%) | 2.5V       | -         |
1273 
| 3        | 1 / 9 ( 11%)   | 2.5V       | -         |
1274 
| 4        | 0 / 10 (  0%)  | -          | -         |
1275 
| 5        | 0 / 10 (  0%)  | -          | -         |
1276 
+----------+----------------+------------+-----------+
1277 
 
1278 7 ale500 
Total placer CPU time: 13 secs
1279 6 ale500 
 
1280 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1281 
 
1282 7 ale500 
 
1283 6 ale500 
Starting router resource preassignment
1284 
 
1285 7 ale500 
Completed router resource preassignment. Real time: 17 secs
1286 6 ale500 
 
1287 7 ale500 
Start NBR router at Sun Jan 05 08:23:29 CET 2014
1288 6 ale500 
 
1289 
*****************************************************************
1290 
Info: NBR allows conflicts(one node used by more than one signal)
1291 
      in the earlier iterations. In each iteration, it tries to
1292 
      solve the conflicts while keeping the critical connections
1293 
      routed as short as possible. The routing process is said to
1294 
      be completed when no conflicts exist and all connections
1295 
      are routed.
1296 
Note: NBR uses a different method to calculate timing slacks. The
1297 
      worst slack and total negative slack may not be the same as
1298 
      that in TRCE report. You should always run TRCE to verify
1299 
      your design. Thanks.
1300 
*****************************************************************
1301 
 
1302 7 ale500 
Start NBR special constraint process at Sun Jan 05 08:23:29 CET 2014
1303 6 ale500 
 
1304 
Start NBR section for initial routing
1305 
Level 1, iteration 1
1306 7 ale500 
126(0.03%) conflicts; 8022(84.22%) untouched conns; 0 (nbr) score;
1307 
Estimated worst slack/total negative slack: 0.040ns/0.000ns; real time: 19 secs
1308 6 ale500 
Level 2, iteration 1
1309 7 ale500 
102(0.03%) conflicts; 7583(79.61%) untouched conns; 0 (nbr) score;
1310 
Estimated worst slack/total negative slack: 0.119ns/0.000ns; real time: 20 secs
1311 6 ale500 
Level 3, iteration 1
1312 7 ale500 
64(0.02%) conflicts; 5994(62.93%) untouched conns; 0 (nbr) score;
1313 
Estimated worst slack/total negative slack: 0.026ns/0.000ns; real time: 21 secs
1314 6 ale500 
Level 4, iteration 1
1315 7 ale500 
315(0.08%) conflicts; 0(0.00%) untouched conn; 58 (nbr) score;
1316 
Estimated worst slack/total negative slack: -0.003ns/-0.058ns; real time: 22 secs
1317 6 ale500 
 
1318 7 ale500 
Info: Initial congestion level at 75% usage is 0
1319 
Info: Initial congestion area  at 75% usage is 24 (2.40%)
1320 6 ale500 
 
1321 
Start NBR section for normal routing
1322 
Level 1, iteration 1
1323 7 ale500 
21(0.01%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score;
1324 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
1325 
Level 2, iteration 1
1326 
17(0.00%) conflicts; 420(4.41%) untouched conns; 0 (nbr) score;
1327 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
1328 
Level 3, iteration 1
1329 
22(0.01%) conflicts; 410(4.30%) untouched conns; 0 (nbr) score;
1330 
Estimated worst slack/total negative slack: 0.064ns/0.000ns; real time: 23 secs
1331 6 ale500 
Level 4, iteration 1
1332 7 ale500 
171(0.05%) conflicts; 0(0.00%) untouched conn; 59 (nbr) score;
1333 
Estimated worst slack/total negative slack: -0.003ns/-0.059ns; real time: 24 secs
1334 6 ale500 
Level 4, iteration 2
1335 7 ale500 
101(0.03%) conflicts; 0(0.00%) untouched conn; 97 (nbr) score;
1336 
Estimated worst slack/total negative slack: -0.005ns/-0.097ns; real time: 24 secs
1337 6 ale500 
Level 4, iteration 3
1338 7 ale500 
61(0.02%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1339 
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 24 secs
1340 6 ale500 
Level 4, iteration 4
1341 7 ale500 
39(0.01%) conflicts; 0(0.00%) untouched conn; 0 (nbr) score;
1342 
Estimated worst slack/total negative slack: 0.001ns/0.000ns; real time: 25 secs
1343 6 ale500 
Level 4, iteration 5
1344 7 ale500 
11(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score;
1345 
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs
1346 6 ale500 
Level 4, iteration 6
1347 7 ale500 
7(0.00%) conflicts; 0(0.00%) untouched conn; 2436 (nbr) score;
1348 
Estimated worst slack/total negative slack: -0.101ns/-2.436ns; real time: 25 secs
1349 6 ale500 
Level 4, iteration 7
1350 7 ale500 
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score;
1351 
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs
1352 6 ale500 
Level 4, iteration 8
1353 7 ale500 
3(0.00%) conflicts; 0(0.00%) untouched conn; 2252 (nbr) score;
1354 
Estimated worst slack/total negative slack: -0.094ns/-2.252ns; real time: 25 secs
1355 6 ale500 
Level 4, iteration 9
1356 7 ale500 
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
1357 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs
1358 6 ale500 
Level 4, iteration 10
1359 7 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
1360 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 25 secs
1361 6 ale500 
 
1362 
Start NBR section for performance tunning (iteration 1)
1363 
Level 4, iteration 1
1364 7 ale500 
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score;
1365 
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs
1366 6 ale500 
Level 4, iteration 2
1367 7 ale500 
2(0.00%) conflicts; 0(0.00%) untouched conn; 1916 (nbr) score;
1368 
Estimated worst slack/total negative slack: -0.094ns/-1.916ns; real time: 26 secs
1369 6 ale500 
Level 4, iteration 3
1370 7 ale500 
1(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
1371 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
1372 6 ale500 
Level 4, iteration 4
1373 7 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
1374 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
1375 6 ale500 
 
1376 
Start NBR section for re-routing
1377 
Level 4, iteration 1
1378 7 ale500 
0(0.00%) conflict; 0(0.00%) untouched conn; 2316 (nbr) score;
1379 
Estimated worst slack/total negative slack: -0.094ns/-2.316ns; real time: 26 secs
1380 6 ale500 
 
1381 
Start NBR section for post-routing
1382 
 
1383 
End NBR router with 0 unrouted connection
1384 
 
1385 
NBR Summary
1386 
-----------
1387 
  Number of unrouted connections : 0 (0.00%)
1388 7 ale500 
  Number of connections with timing violations : 28 (0.29%)
1389 
  Estimated worst slack : -0.094ns
1390 
  Timing score : 281
1391 6 ale500 
-----------
1392 
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
1393 
 
1394 
 
1395 
 
1396 
------------------------------------------------------------------------------------------------------------------------------------
1397 7 ale500 
WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-0.094ns) is worse than the default value(0.000ns).
1398 6 ale500 
------------------------------------------------------------------------------------------------------------------------------------
1399 
 
1400 
Total CPU time 26 secs
1401 
Total REAL time: 27 secs
1402 
Completely routed.
1403 7 ale500 
End of route.  9525 routed (100.00%); 0 unrouted.
1404 6 ale500 
Checking DRC ...
1405 
No errors found.
1406 
 
1407 
Hold time timing score: 0, hold timing errors: 0
1408 
 
1409 7 ale500 
Timing score: 281
1410 6 ale500 
 
1411 
Dumping design to file P6809_P6809.dir/5_1.ncd.
1412 
 
1413 
 
1414 
PAR_SUMMARY::Run status = completed
1415 
PAR_SUMMARY::Number of unrouted conns = 0
1416 7 ale500 
PAR_SUMMARY::Worst  slack> = -0.094
1417 
PAR_SUMMARY::Timing score> = 0.281
1418 6 ale500 
PAR_SUMMARY::Worst  slack> =
1419 
PAR_SUMMARY::Timing score> =
1420 
 
1421 
Total CPU  time to completion: 27 secs
1422 
Total REAL time to completion: 28 secs
1423 
 
1424 
par done!
1425 
 
1426 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1427 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1428 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1429 
Copyright (c) 2001 Agere Systems   All rights reserved.
1430 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1431 
Exiting par with exit code 0
1432 
Exiting mpartrce with exit code 0
1433 
 
1434 
trce -f "P6809_P6809.pt" -o "P6809_P6809.twr" "P6809_P6809.ncd" "P6809_P6809.prf"
1435 
trce:  version Diamond (64-bit) 2.2.0.101
1436 
 
1437 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1438 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1439 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1440 
Copyright (c) 2001 Agere Systems   All rights reserved.
1441 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1442 
 
1443 
Loading design for application trce from file P6809_P6809.ncd.
1444 
Design name: CC3_top
1445 
NCD version: 3.2
1446 
Vendor:      LATTICE
1447 
Device:      LCMXO2-7000HE
1448 
Package:     TQFP144
1449 
Performance: 4
1450 
Loading device for application trce from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1451 
Package Status:                     Final          Version 1.36
1452 
Performance Hardware Data Status:   Final)         Version 23.4
1453 
Setup and Hold Report
1454 
 
1455 
--------------------------------------------------------------------------------
1456 
Lattice TRACE Report - Setup, Version Diamond (64-bit) 2.2.0.101
1457 7 ale500 
Sun Jan  5 08:23:43 2014
1458 6 ale500 
 
1459 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1460 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1461 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1462 
Copyright (c) 2001 Agere Systems   All rights reserved.
1463 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1464 
 
1465 
Report Information
1466 
------------------
1467 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1468 
Design file:     P6809_P6809.ncd
1469 
Preference file: P6809_P6809.prf
1470 
Device,speed:    LCMXO2-7000HE,4
1471 
Report level:    verbose report, limited to 10 items per preference
1472 
--------------------------------------------------------------------------------
1473 
 
1474 
BLOCK ASYNCPATHS
1475 
BLOCK RESETPATHS
1476 
--------------------------------------------------------------------------------
1477 
 
1478 
 
1479 
 
1480 
Timing summary (Setup):
1481 
---------------
1482 
 
1483 7 ale500 
Timing errors: 6  Score: 281
1484 
Cumulative negative slack: 281
1485 6 ale500 
 
1486 7 ale500 
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
1487 6 ale500 
 
1488 
--------------------------------------------------------------------------------
1489 
Lattice TRACE Report - Hold, Version Diamond (64-bit) 2.2.0.101
1490 7 ale500 
Sun Jan  5 08:23:43 2014
1491 6 ale500 
 
1492 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1493 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1494 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1495 
Copyright (c) 2001 Agere Systems   All rights reserved.
1496 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1497 
 
1498 
Report Information
1499 
------------------
1500 
Command line:    trce -v 10 -gt -sethld -sp 4 -sphld m -o P6809_P6809.twr P6809_P6809.ncd P6809_P6809.prf
1501 
Design file:     P6809_P6809.ncd
1502 
Preference file: P6809_P6809.prf
1503 
Device,speed:    LCMXO2-7000HE,m
1504 
Report level:    verbose report, limited to 10 items per preference
1505 
--------------------------------------------------------------------------------
1506 
 
1507 
BLOCK ASYNCPATHS
1508 
BLOCK RESETPATHS
1509 
--------------------------------------------------------------------------------
1510 
 
1511 
 
1512 
 
1513 
Timing summary (Hold):
1514 
---------------
1515 
 
1516 
Timing errors: 0  Score: 0
1517 
Cumulative negative slack: 0
1518 
 
1519 7 ale500 
Constraints cover 3270002 paths, 1 nets, and 9437 connections (99.1% coverage)
1520 6 ale500 
 
1521 
 
1522 
 
1523 
Timing summary (Setup and Hold):
1524 
---------------
1525 
 
1526 7 ale500 
Timing errors: 6 (setup), 0 (hold)
1527 
Score: 281 (setup), 0 (hold)
1528 
Cumulative negative slack: 281 (281+0)
1529 6 ale500 
--------------------------------------------------------------------------------
1530 
 
1531 
--------------------------------------------------------------------------------
1532 
 
1533 
Total time: 0 secs
1534 7 ale500 
 
1535 
bitgen -f "P6809_P6809.t2b" -w "P6809_P6809.ncd" -jedec "P6809_P6809.prf"
1536 
 
1537 
 
1538 
BITGEN: Bitstream Generator Diamond (64-bit) 2.2.0.101
1539 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
1540 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
1541 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
1542 
Copyright (c) 2001 Agere Systems   All rights reserved.
1543 
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
1544 
 
1545 
 
1546 
Loading design for application Bitgen from file P6809_P6809.ncd.
1547 
Design name: CC3_top
1548 
NCD version: 3.2
1549 
Vendor:      LATTICE
1550 
Device:      LCMXO2-7000HE
1551 
Package:     TQFP144
1552 
Performance: 4
1553 
Loading device for application Bitgen from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
1554 
Package Status:                     Final          Version 1.36
1555 
Performance Hardware Data Status:   Final)         Version 23.4
1556 
 
1557 
Running DRC.
1558 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
1559 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
1560 
DRC detected 0 errors and 0 warnings.
1561 
Reading Preference File from P6809_P6809.prf...
1562 
 
1563 
Preference Summary:
1564 
+---------------------------------+---------------------------------+
1565 
|  Preference                     |  Current Setting                |
1566 
+---------------------------------+---------------------------------+
1567 
|                         RamCfg  |                        Reset**  |
1568 
+---------------------------------+---------------------------------+
1569 
|                     MCCLK_FREQ  |                         2.08**  |
1570 
+---------------------------------+---------------------------------+
1571 
|                  CONFIG_SECURE  |                          OFF**  |
1572 
+---------------------------------+---------------------------------+
1573 
|                      JTAG_PORT  |                       ENABLE**  |
1574 
+---------------------------------+---------------------------------+
1575 
|                       SDM_PORT  |                      DISABLE**  |
1576 
+---------------------------------+---------------------------------+
1577 
|                 SLAVE_SPI_PORT  |                      DISABLE**  |
1578 
+---------------------------------+---------------------------------+
1579 
|                MASTER_SPI_PORT  |                      DISABLE**  |
1580 
+---------------------------------+---------------------------------+
1581 
|                       I2C_PORT  |                      DISABLE**  |
1582 
+---------------------------------+---------------------------------+
1583 
|        MUX_CONFIGURATION_PORTS  |                      DISABLE**  |
1584 
+---------------------------------+---------------------------------+
1585 
|                  CONFIGURATION  |                          CFG**  |
1586 
+---------------------------------+---------------------------------+
1587 
|                COMPRESS_CONFIG  |                           ON**  |
1588 
+---------------------------------+---------------------------------+
1589 
|                        MY_ASSP  |                          OFF**  |
1590 
+---------------------------------+---------------------------------+
1591 
|               ONE_TIME_PROGRAM  |                          OFF**  |
1592 
+---------------------------------+---------------------------------+
1593 
|                 ENABLE_TRANSFR  |                      DISABLE**  |
1594 
+---------------------------------+---------------------------------+
1595 
|                  SHAREDEBRINIT  |                      DISABLE**  |
1596 
+---------------------------------+---------------------------------+
1597 
 *  Default setting.
1598 
 ** The specified setting matches the default setting.
1599 
 
1600 
 
1601 
Creating bit map...
1602 
 
1603 
Bitstream Status:   Final           Version 1.83
1604 
 
1605 
Saving bit stream in "P6809_P6809.jed".
1606 
 
1607 
===========
1608 
UFM Summary
1609 
===========
1610 
UFM Size:        2046 Pages (128*2046 Bits)
1611 
UFM Utilization: General Purpose Flash Memory
1612 
 
1613 
Available General Purpose Flash Memory: 2046 Pages (Page 0 to Page 2045)
1614 
Initialized UFM Pages:                     0 Page
1615 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.