| 1 |
12 |
ale500 |
<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to 'C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/hdla_gen_hierarchy.html'.
|
| 2 |
|
|
Starting: parse design source files
|
| 3 |
|
|
INFO - (VHDL-1504) The default vhdl library search path is now "C:/lscc/diamond/3.1_x64/cae_library/vhdl_packages/vdbs"
|
| 4 |
|
|
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v
|
| 5 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v
|
| 6 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v
|
| 7 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(12,10-12,18) (VERI-1328) analyzing included file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v
|
| 8 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v
|
| 9 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(8,10-8,18) (VERI-1328) analyzing included file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v
|
| 10 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v
|
| 11 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v
|
| 12 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(9,10-9,18) (VERI-1328) analyzing included file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v
|
| 13 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v
|
| 14 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(4,10-4,18) (VERI-1328) analyzing included file C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v
|
| 15 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v
|
| 16 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v
|
| 17 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v
|
| 18 |
|
|
(VERI-1482) Analyzing Verilog file C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v
|
| 19 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,8-10,15) (VERI-1018) compiling module CC3_top
|
| 20 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v(10,1-175,10) (VERI-9000) elaborating module 'CC3_top'
|
| 21 |
13 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v(10,1-1137,10) (VERI-9000) elaborating module 'MC6809_cpu_uniq_1'
|
| 22 |
12 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v(8,1-171,10) (VERI-9000) elaborating module 'bios2k_uniq_1'
|
| 23 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v(2,1-192,10) (VERI-9000) elaborating module 'vgatext_uniq_1'
|
| 24 |
13 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(15,1-61,10) (VERI-9000) elaborating module 'alu_uniq_1'
|
| 25 |
12 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(7,1-188,10) (VERI-9000) elaborating module 'regblock_uniq_1'
|
| 26 |
13 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(9,1-152,10) (VERI-9000) elaborating module 'decode_regs_uniq_1'
|
| 27 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(155,1-281,10) (VERI-9000) elaborating module 'decode_op_uniq_1'
|
| 28 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(286,1-310,10) (VERI-9000) elaborating module 'decode_ea_uniq_1'
|
| 29 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(312,1-383,10) (VERI-9000) elaborating module 'decode_alu_uniq_1'
|
| 30 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v(385,1-422,10) (VERI-9000) elaborating module 'test_condition_uniq_1'
|
| 31 |
12 |
ale500 |
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_1'
|
| 32 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_1'
|
| 33 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_2'
|
| 34 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_1'
|
| 35 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v(8,1-295,10) (VERI-9000) elaborating module 'fontrom_uniq_1'
|
| 36 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v(8,1-305,10) (VERI-9000) elaborating module 'textmem4k_uniq_1'
|
| 37 |
13 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(604,1-628,10) (VERI-9000) elaborating module 'mul8x8_uniq_1'
|
| 38 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(202,1-326,10) (VERI-9000) elaborating module 'alu8_uniq_1'
|
| 39 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(329,1-602,10) (VERI-9000) elaborating module 'alu16_uniq_1'
|
| 40 |
12 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v(191,1-285,10) (VERI-9000) elaborating module 'calc_ea_uniq_1'
|
| 41 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_2'
|
| 42 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) (VERI-9000) elaborating module 'VHI_uniq_3'
|
| 43 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_3'
|
| 44 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_4'
|
| 45 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_5'
|
| 46 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_6'
|
| 47 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_7'
|
| 48 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_8'
|
| 49 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_9'
|
| 50 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) (VERI-9000) elaborating module 'DP8KC_uniq_10'
|
| 51 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_2'
|
| 52 |
|
|
INFO - C:/lscc/diamond/3.1_x64/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) (VERI-9000) elaborating module 'VLO_uniq_3'
|
| 53 |
13 |
ale500 |
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(66,1-83,10) (VERI-9000) elaborating module 'logic8_uniq_1'
|
| 54 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(89,1-127,10) (VERI-9000) elaborating module 'arith8_uniq_1'
|
| 55 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(162,1-199,10) (VERI-9000) elaborating module 'shift8_uniq_1'
|
| 56 |
|
|
INFO - C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v(133,1-160,10) (VERI-9000) elaborating module 'arith16_uniq_1'
|
| 57 |
12 |
ale500 |
Done: design load finished with (0) errors, and (0) warnings
|
| 58 |
4 |
ale500 |
|
| 59 |
|
|
</PRE></BODY></HTML>
|
