Subversion Repositories 6809_6309_compatible_core

#--  Synopsys, Inc.

#--  Version I-2013.09L

#--  Project file C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809\scratchproject.prs

#project files

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/CC3_top.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/alu16.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/decoders.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/defs.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/MC6809_cpu.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/../../rtl/verilog/regblock.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/bios2k.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/vgatext.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/fontrom.v"

add_file -verilog "C:/02_Elektronik/020_V6809/trunk/syn/lattice/textmem4k.v"

#implementation: "P6809"

impl -add C:\02_Elektronik\020_V6809\trunk\syn\lattice\P6809 -type fpga

#

#implementation attributes

set_option -vlog_std v2001

set_option -project_relative_includes 1

set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/}

set_option -include_path {C:/02_Elektronik/020_V6809/trunk/syn/lattice}

#device options

set_option -technology MACHXO2

set_option -part LCMXO2_7000HE

set_option -package TG144C

set_option -speed_grade -4

set_option -part_companion ""

#compilation/mapping options

set_option -top_module "CC3_top"

# mapper_options

set_option -frequency 1

set_option -write_verilog 0

set_option -write_vhdl 0

set_option -srs_instrumentation 1

# Lattice XP

set_option -maxfan 1000

set_option -disable_io_insertion 0

set_option -retiming 0

set_option -pipe 1

set_option -forcegsr false

set_option -fix_gated_and_generated_clocks 1

set_option -RWCheckOnRam 1

set_option -update_models_cp 0

set_option -syn_edif_array_rename 1

# sequential_optimization_options

set_option -symbolic_fsm_compiler 1

# Compiler Options

set_option -compiler_compatible 0

set_option -resource_sharing 1

set_option -multi_file_compilation_unit 1

#automatic place and route (vendor) options

set_option -write_apr_constraint 1

#set result format/file last

project -result_file "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.edi"

#set log file

set_option log_file "C:/02_Elektronik/020_V6809/trunk/syn/lattice/P6809/P6809_P6809.srf"

impl -active "P6809"