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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [lattice/] [logs/] [P6809_P6809_par.html] - Blame information for rev 2

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<HTML>
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<HEAD><TITLE>Place & Route Report</TITLE>
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 2.2.0.101.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
11 
Copyright (c) 1995 AT&T Corp.   All rights reserved.
12 
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
15 
Wed Dec 25 17:50:32 2013
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/usr/local/diamond/2.2_x64/ispfpga/bin/lin64/par -f P6809_P6809.p2t
18 
P6809_P6809_map.ncd P6809_P6809.dir P6809_P6809.prf
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21 
Preference file: P6809_P6809.prf.
22 
 
23 
<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/      Number      Worst       Timing      Run         NCD
25 
Cost [ncd]  Unrouted    Slack       Score       Time        Status
26 
----------  --------    -----       --------    -----       ------
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5_1   *     0           -4.091      12558270    28          Complete
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29 
 
30 
* : Design saved.
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32 
Total (real) run time for 1-seed: 28 secs
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34 
par done!
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36 
Lattice Place and Route Report for Design "P6809_P6809_map.ncd"
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Wed Dec 25 17:50:32 2013
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39 
 
40 
<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
41 
PAR: Place And Route Diamond (64-bit) 2.2.0.101.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF P6809_P6809_map.ncd P6809_P6809.dir/5_1.ncd P6809_P6809.prf
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Preference file: P6809_P6809.prf.
44 
Placement level-cost: 5-1.
45 
Routing Iterations: 6
46 
 
47 
Loading design for application par from file P6809_P6809_map.ncd.
48 
Design name: CC3_top
49 
NCD version: 3.2
50 
Vendor:      LATTICE
51 
Device:      LCMXO2-7000HE
52 
Package:     TQFP144
53 
Performance: 4
54 
Loading device for application par from file 'xo2c7000.nph' in environment: /usr/local/diamond/2.2_x64/ispfpga.
55 
Package Status:                     Final          Version 1.36
56 
Performance Hardware Data Status:   Final)         Version 23.4
57 
License checked out.
58 
 
59 
 
60 
Ignore Preference Error(s):  True
61 
 
62 
<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
63 
 
64 
   PIO (prelim)   49+4(JTAG)/336     14% used
65 
                  49+4(JTAG)/115     42% bonded
66 
   IOLOGIC            8/336           2% used
67 
 
68 
   SLICE           1163/3432         33% used
69 
 
70 
   GSR                1/1           100% used
71 
 
72 
 
73 
 
74 
INFO: Design contains EBR with ASYNC Reset Mode that has a limitation: The use of the EBR block asynchronous reset requires that certain timing be met between the clock and the reset within the memory block. See the device specific datasheet for additional details.
75 
INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
76 
Number of Signals: 2675
77 
Number of Connections: 8924
78 
 
79 
Pin Constraint Summary:
80 
   49 out of 49 pins locked (100% locked).
81 
 
82 
The following 1 signal is selected to use the primary clock routing resources:
83 
    cpu_clkgen (driver: clk40_i, clk load #: 315)
84 
 
85 
 
86 
The following 6 signals are selected to use the secondary clock routing resources:
87 
    cpu_clk (driver: SLICE_477, clk load #: 0, sr load #: 0, ce load #: 95)
88 
    cpu0/cff_1_sqmuxa_0_RNIL5DT (driver: cpu0/SLICE_865, clk load #: 0, sr load #: 0, ce load #: 43)
89 
    cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1 (driver: cpu0/regs/SLICE_829, clk load #: 0, sr load #: 0, ce load #: 12)
90 
    cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1 (driver: cpu0/regs/SLICE_830, clk load #: 0, sr load #: 0, ce load #: 12)
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    cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2 (driver: cpu0/regs/SLICE_887, clk load #: 0, sr load #: 0, ce load #: 12)
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    cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2 (driver: cpu0/regs/SLICE_886, clk load #: 0, sr load #: 0, ce load #: 12)
93 
 
94 
Signal cpu0.cpu_reset_i_2_i is selected as Global Set/Reset.
95 
Starting Placer Phase 0.
96 
..........
97 
Finished Placer Phase 0.  REAL time: 4 secs
98 
 
99 
 
100 
......................
101 
Placer score = 808498.
102 
 
103 
 
104 
Starting Placer Phase 2.
105 
 
106 
Placer score =  797364
107 
Finished Placer Phase 2.  REAL time: 13 secs
108 
 
109 
 
110 
 
111 
 
112 
 
113 
Global Clock Resources:
114 
 
115 
  PLL        : 0 out of 2 (0%)
116 
 
117 
  DCC        : 0 out of 8 (0%)
118 
 
119 
Quadrants All (TL, TR, BL, BR) - Global Clocks:
120 
  PRIMARY "cpu_clkgen" from comp "clk40_i" on CLK_PIN site "27 (PL22A)", clk load = 315
121 
 
122 
 
123 
  SECONDARY "cpu0/regs/regh[4]_1_sqmuxa_1_1_RNI7MAL1" from F1 on comp "cpu0/regs/SLICE_829" on site "R21C18C", clk load = 0, ce load = 12, sr load = 0
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  SECONDARY "cpu0/regs/regh[3]_1_sqmuxa_3_0_RNI9DKR1" from F1 on comp "cpu0/regs/SLICE_830" on site "R14C18D", clk load = 0, ce load = 12, sr load = 0
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  SECONDARY "cpu0/regs/regh[2]_0_sqmuxa_i_a2_1_RNIJL6H2" from F0 on comp "cpu0/regs/SLICE_887" on site "R14C18B", clk load = 0, ce load = 12, sr load = 0
126 
  SECONDARY "cpu0/regs/regh[1]_0_sqmuxa_1_i_a2_2_RNI192E2" from F0 on comp "cpu0/regs/SLICE_886" on site "R14C18C", clk load = 0, ce load = 12, sr load = 0
127 
 
128 
  PRIMARY  : 1 out of 8 (12%)
129 
 
130 
 
131 
Edge Clocks:
132 
  No edge clock selected.
133 
 
134 
 
135 
 
136 
 
137 
I/O Usage Summary (final):
138 
   49 out of 336 (14.6%) PIO sites used.
139 
   49 out of 115 (42.6%) bonded PIO sites used.
140 
   Number of PIO comps: 49; differential: 0
141 
 
142 
 
143 
I/O Bank Usage Summary:
144 
 
145 
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
146 
 
147 
| 0        | 12 / 28 ( 42%) | 2.5V       | -         |
148 
| 1        | 13 / 29 ( 44%) | 2.5V       | -         |
149 
| 2        | 23 / 29 ( 79%) | 2.5V       | -         |
150 
 
151 
| 4        | 0 / 10 (  0%)  | -          | -         |
152 
 
153 
+----------+----------------+------------+-----------+
154 
 
155 
 
156 
 
157 
Dumping design to file P6809_P6809.dir/5_1.ncd.
158 
 
159 
0 connections routed; 8924 unrouted.
160 
Starting router resource preassignment
161 
 
162 
Completed router resource preassignment. Real time: 16 secs
163 
 
164 
 
165 
 
166 
*****************************************************************
167 
 
168 
 
169 
      solve the conflicts while keeping the critical connections
170 
      routed as short as possible. The routing process is said to
171 
      be completed when no conflicts exist and all connections
172 
      are routed.
173 
Note: NBR uses a different method to calculate timing slacks. The
174 
      worst slack and total negative slack may not be the same as
175 
      that in TRCE report. You should always run TRCE to verify
176 
 
177 
*****************************************************************
178 
 
179 
Start NBR special constraint process at Wed Dec 25 17:50:48 CET 2013
180 
 
181 
 
182 
Level 1, iteration 1
183 
137(0.04%) conflicts; 7446(83.44%) untouched conns; 1425225 (nbr) score;
184 
Estimated worst slack/total negative slack: -3.332ns/-1425.225ns; real time: 18 secs
185 
Level 2, iteration 1
186 
 
187 
Estimated worst slack/total negative slack: -3.339ns/-1178.363ns; real time: 19 secs
188 
Level 3, iteration 1
189 
89(0.02%) conflicts; 5385(60.34%) untouched conns; 1500920 (nbr) score;
190 
Estimated worst slack/total negative slack: -3.347ns/-1500.921ns; real time: 20 secs
191 
 
192 
 
193 
 
194 
 
195 
 
196 
Info: Initial congestion area  at 75% usage is 5 (0.50%)
197 
 
198 
Start NBR section for normal routing
199 
Level 1, iteration 1
200 
88(0.02%) conflicts; 402(4.50%) untouched conns; 1210645 (nbr) score;
201 
 
202 
Level 4, iteration 1
203 
237(0.06%) conflicts; 0(0.00%) untouched conn; 1243629 (nbr) score;
204 
Estimated worst slack/total negative slack: -3.155ns/-1243.630ns; real time: 22 secs
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Level 4, iteration 2
206 
131(0.03%) conflicts; 0(0.00%) untouched conn; 1252609 (nbr) score;
207 
Estimated worst slack/total negative slack: -3.245ns/-1252.609ns; real time: 23 secs
208 
Level 4, iteration 3
209 
97(0.03%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score;
210 
 
211 
Level 4, iteration 4
212 
71(0.02%) conflicts; 0(0.00%) untouched conn; 1308083 (nbr) score;
213 
 
214 
Level 4, iteration 5
215 
71(0.02%) conflicts; 0(0.00%) untouched conn; 1426563 (nbr) score;
216 
 
217 
 
218 
 
219 
 
220 
Level 4, iteration 7
221 
30(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score;
222 
Estimated worst slack/total negative slack: -3.626ns/-1480.394ns; real time: 24 secs
223 
Level 4, iteration 8
224 
23(0.01%) conflicts; 0(0.00%) untouched conn; 1480393 (nbr) score;
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226 
Level 4, iteration 9
227 
17(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score;
228 
Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs
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Level 4, iteration 10
230 
16(0.00%) conflicts; 0(0.00%) untouched conn; 1550078 (nbr) score;
231 
Estimated worst slack/total negative slack: -3.626ns/-1550.079ns; real time: 24 secs
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Level 4, iteration 11
233 
15(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score;
234 
Estimated worst slack/total negative slack: -3.656ns/-1549.790ns; real time: 25 secs
235 
Level 4, iteration 12
236 
17(0.00%) conflicts; 0(0.00%) untouched conn; 1549789 (nbr) score;
237 
 
238 
Level 4, iteration 13
239 
 
240 
Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs
241 
 
242 
 
243 
Estimated worst slack/total negative slack: -3.634ns/-1540.316ns; real time: 25 secs
244 
 
245 
6(0.00%) conflicts; 0(0.00%) untouched conn; 1564368 (nbr) score;
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247 
Level 4, iteration 16
248 
 
249 
Estimated worst slack/total negative slack: -3.626ns/-1564.369ns; real time: 25 secs
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Level 4, iteration 17
251 
6(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score;
252 
Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs
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Level 4, iteration 18
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7(0.00%) conflicts; 0(0.00%) untouched conn; 1543739 (nbr) score;
255 
Estimated worst slack/total negative slack: -3.634ns/-1543.739ns; real time: 25 secs
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Level 4, iteration 19
257 
6(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score;
258 
Estimated worst slack/total negative slack: -3.626ns/-1539.701ns; real time: 25 secs
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Level 4, iteration 20
260 
4(0.00%) conflicts; 0(0.00%) untouched conn; 1539700 (nbr) score;
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Level 4, iteration 21
263 
 
264 
Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 25 secs
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Level 4, iteration 22
266 
2(0.00%) conflicts; 0(0.00%) untouched conn; 1541625 (nbr) score;
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Estimated worst slack/total negative slack: -3.627ns/-1541.626ns; real time: 26 secs
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Level 4, iteration 23
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1(0.00%) conflict; 0(0.00%) untouched conn; 1553537 (nbr) score;
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Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs
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Level 4, iteration 24
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5(0.00%) conflicts; 0(0.00%) untouched conn; 1553537 (nbr) score;
273 
Estimated worst slack/total negative slack: -3.627ns/-1553.538ns; real time: 26 secs
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Level 4, iteration 25
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3(0.00%) conflicts; 0(0.00%) untouched conn; 1631557 (nbr) score;
276 
Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs
277 
 
278 
1(0.00%) conflict; 0(0.00%) untouched conn; 1631557 (nbr) score;
279 
Estimated worst slack/total negative slack: -3.805ns/-1631.557ns; real time: 26 secs
280 
 
281 
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
282 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
283 
Level 4, iteration 28
284 
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
285 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 29
287 
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
288 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 30
290 
1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
291 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 31
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1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
294 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 32
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1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
297 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 33
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1(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
300 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
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Level 4, iteration 34
302 
0(0.00%) conflict; 0(0.00%) untouched conn; 1553196 (nbr) score;
303 
Estimated worst slack/total negative slack: -3.627ns/-1553.197ns; real time: 26 secs
304 
 
305 
Start NBR section for performance tunning (iteration 1)
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Level 4, iteration 1
307 
4(0.00%) conflicts; 0(0.00%) untouched conn; 1791659 (nbr) score;
308 
Estimated worst slack/total negative slack: -4.091ns/-1791.660ns; real time: 27 secs
309 
 
310 
Start NBR section for re-routing
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 1793776 (nbr) score;
313 
Estimated worst slack/total negative slack: -4.091ns/-1793.777ns; real time: 27 secs
314 
 
315 
Start NBR section for post-routing
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317 
End NBR router with 0 unrouted connection
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NBR Summary
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-----------
321 
  Number of unrouted connections : 0 (0.00%)
322 
  Number of connections with timing violations : 938 (10.51%)
323 
  Estimated worst slack : -4.091ns
324 
  Timing score : 12558270
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-----------
326 
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
327 
 
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330 
------------------------------------------------------------------------------------------------------------------------------------
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WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-4.091ns) is worse than the default value(0.000ns).
332 
------------------------------------------------------------------------------------------------------------------------------------
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334 
Total CPU time 28 secs
335 
Total REAL time: 28 secs
336 
Completely routed.
337 
End of route.  8924 routed (100.00%); 0 unrouted.
338 
Checking DRC ...
339 
No errors found.
340 
 
341 
Hold time timing score: 0, hold timing errors: 0
342 
 
343 
Timing score: 12558270
344 
 
345 
Dumping design to file P6809_P6809.dir/5_1.ncd.
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347 
 
348 
All signals are completely routed.
349 
 
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351 
PAR_SUMMARY::Run status = completed
352 
PAR_SUMMARY::Number of unrouted conns = 0
353 
PAR_SUMMARY::Worst  slack<setup/<ns>> = -4.091
354 
PAR_SUMMARY::Timing score<setup/<ns>> = 12558.270
355 
PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
356 
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
357 
 
358 
Total CPU  time to completion: 28 secs
359 
Total REAL time to completion: 28 secs
360 
 
361 
par done!
362 
 
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
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