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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
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#install: /usr/local/diamond/2.2_x64/synpbase
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#OS: Linux
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#Hostname: node01.pacito.sys
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#Implementation: P6809
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$ Start of Compile
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#Wed Dec 25 17:50:10 2013
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Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
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@N|Running in 64-bit mode
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Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/machxo2.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/lucent/pmi_def.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/umr_capim.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_objects.v"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/scemi_pipes.svh"
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@I::"/usr/local/diamond/2.2_x64/synpbase/lib/vlog/hypermods.v"
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@I::"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v"
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@I:"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":"/home/pacito/02_Elektronik/020_V6809/6809/defs.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v"
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@I::"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v"
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Verilog syntax check successful!
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File /home/pacito/02_Elektronik/020_V6809/6809/decoders.v changed - recompiling
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File /home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v changed - recompiling
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File /home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v changed - recompiling
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Selecting top level module CC3_top
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":13:7:13:11|Synthesizing module alu16
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":493:0:493:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":7:7:7:14|Synthesizing module regblock
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":225:0:225:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:10:50:13|No assignment to regh[7]
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":50:21:50:24|No assignment to regl[6]
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":9:7:9:17|Synthesizing module decode_regs
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":108:7:108:15|Synthesizing module decode_op
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":236:7:236:15|Synthesizing module decode_ea
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":262:7:262:16|Synthesizing module decode_alu
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":334:7:334:20|Synthesizing module test_condition
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":25:7:25:16|Synthesizing module MC6809_cpu
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@N: CG793 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":405:6:405:13|Ignoring system task $display
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@W: CG532 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":961:0:961:6|Initial statement will only initialize memories through the usage of $readmemh and $readmemb. Everything else is ignored
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal next_push_state[5:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_post_incdec -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_write_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_set_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_regs[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_pp_active_reg[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_postbyte0[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p3_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_p2_valid -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_opcode[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofslo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ofshi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_new_pc[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memlo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_memhi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_mem_dest[1:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ind_ea[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_inc_pc -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_ealo[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_eahi[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_dec_su -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_we -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_oe -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_data_o[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_cpu_addr[15:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@A: CL282 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Feedback mux created for signal k_clear_e -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[0] is always 1, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit k_mem_dest[1] is always 0, optimizing ...
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@W: CL189 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Register bit next_mem_state[2] is always 0, optimizing ...
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1120:7:1120:9|Synthesizing module VHI
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1291:7:1291:11|Synthesizing module DP8KC
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@N: CG364 :"/usr/local/diamond/2.2_x64/cae_library/synthesis/verilog/machxo2.v":1124:7:1124:9|Synthesizing module VLO
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":8:7:8:12|Synthesizing module bios2k
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@W: CL168 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":28:8:28:21|Pruning instance scuba_vhi_inst -- not in use ...
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@N: CG364 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":7:7:7:13|Synthesizing module CC3_top
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@W: CG133 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":28:14:28:21|No assignment to clk_div2
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|No assignment to wire cpu1_addr_o
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:40:34:51|No assignment to wire cpu1_data_in
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|No assignment to wire cpu1_data_out
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:23:35:29|No assignment to wire cpu1_we
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@W: CG360 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":35:32:35:38|No assignment to wire cpu1_oe
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":34:54:34:66|*Input cpu1_data_out[7:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL156 :"/home/pacito/02_Elektronik/020_V6809/6809/CC3_top.v":33:25:33:35|*Input cpu1_addr_o[10:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible.
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@W: CL279 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Pruning register bits 5 to 2 of next_push_state[5:0]
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":338:18:338:20|Input port bits 7 to 4 of CCR[7:0] are unused
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@W: CL246 :"/home/pacito/02_Elektronik/020_V6809/6809/decoders.v":237:18:237:27|Input port bits 6 to 5 of eapostbyte[7:0] are unused
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@END
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# Wed Dec 25 17:50:12 2013
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###########################################################]
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Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.
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@L: /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt
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Printing clock summary report in "/home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 94MB peak: 94MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 109MB)
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159 |
|
|
|
160 |
|
|
|
161 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 108MB peak: 111MB)
|
162 |
|
|
|
163 |
|
|
|
164 |
|
|
|
165 |
|
|
Clock Summary
|
166 |
|
|
**************
|
167 |
|
|
|
168 |
|
|
Start Requested Requested Clock Clock
|
169 |
|
|
Clock Frequency Period Type Group
|
170 |
|
|
--------------------------------------------------------------------------------------------------------------------
|
171 |
|
|
CC3_top|clk40_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0
|
172 |
|
|
CC3_top|cpu_clk_derived_clock 1.0 MHz 1000.000 derived (from CC3_top|clk40_i) Inferred_clkgroup_0
|
173 |
|
|
====================================================================================================================
|
174 |
|
|
|
175 |
|
|
@W: MT529 :"/home/pacito/02_Elektronik/020_V6809/6809/lattice/bios2k.v":74:10:74:21|Found inferred clock CC3_top|clk40_i which controls 1 sequential elements including bios.bios2k_0_0_1. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
176 |
|
|
|
177 |
|
|
syn_allowed_resources : blockrams=26 set on top level netlist CC3_top
|
178 |
|
|
Finished Pre Mapping Phase.Pre-mapping successful!
|
179 |
|
|
|
180 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 136MB)
|
181 |
|
|
|
182 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
183 |
|
|
|
184 |
|
|
|
185 |
|
|
|
186 |
|
|
Map & Optimize Report
|
187 |
|
|
|
188 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:13:46
|
189 |
|
|
|
190 |
|
|
Product Version G-2012.09L-SP1
|
191 |
|
|
|
192 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
193 |
|
|
|
194 |
|
|
@N: MF248 |Running in 64-bit mode.
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 91MB peak: 92MB)
|
198 |
|
|
|
199 |
|
|
|
200 |
|
|
|
201 |
|
|
|
202 |
|
|
|
203 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 105MB peak: 106MB)
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
|
210 |
|
|
|
211 |
|
|
|
212 |
|
|
|
213 |
|
|
Available hyper_sources - for debug and ip models
|
214 |
|
|
|
215 |
|
|
|
216 |
|
|
|
217 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 133MB peak: 135MB)
|
218 |
|
|
|
219 |
|
|
@N:"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Found counter in view:work.MC6809_cpu(verilog) inst k_cpu_addr[15:0]
|
220 |
|
|
|
221 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
222 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_nmi[0] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
223 |
|
|
|
224 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_set_e in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
225 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_firq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
226 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance k_reg_irq[1] in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
227 |
|
|
|
228 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.fflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
229 |
|
|
|
230 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Removing sequential instance regs.eflag in hierarchy view:work.MC6809_cpu(verilog) because there are no references to its outputs
|
231 |
|
|
|
232 |
|
|
Finished factoring (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 154MB peak: 156MB)
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
@N: BN362 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":287:0:287:5|Removing sequential instance cpu0.k_reg_irq[2] in hierarchy view:work.CC3_top(verilog) because there are no references to its outputs
|
236 |
|
|
|
237 |
|
|
|
238 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 150MB peak: 157MB)
|
239 |
|
|
|
240 |
|
|
|
241 |
|
|
|
242 |
|
|
|
243 |
|
|
|
244 |
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":205:24:205:32|Pipelining module un63_regl[15:0]
|
245 |
|
|
|
246 |
|
|
|
247 |
|
|
|
248 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
|
249 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq16[15:0] pushed in.
|
250 |
|
|
|
251 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register reg_n_in pushed in.
|
252 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register vff pushed in.
|
253 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register zff pushed in.
|
254 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register nff pushed in.
|
255 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register hflag pushed in.
|
256 |
|
|
@N: FA113 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":180:19:180:32|Pipelining module daa_lnm9
|
257 |
|
|
|
258 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/alu16.v":376:0:376:5|Register regq8[7:0] pushed in.
|
259 |
|
|
|
260 |
|
|
@N: MF169 :"/home/pacito/02_Elektronik/020_V6809/6809/regblock.v":172:0:172:5|Register cff pushed in.
|
261 |
|
|
@N: FX404 :"/home/pacito/02_Elektronik/020_V6809/6809/MC6809_cpu.v":289:2:289:3|Found addmux in view:work.CC3_top(verilog) inst cpu0.dec_regs.k_new_pc_17_2_i_m2[15:0] from cpu0.un1_regs_o_pc[15:0]
|
262 |
|
|
|
263 |
|
|
|
264 |
|
|
|
265 |
|
|
|
266 |
|
|
|
267 |
|
|
|
268 |
|
|
|
269 |
|
|
|
270 |
|
|
|
271 |
|
|
|
272 |
|
|
|
273 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:09s; CPU Time elapsed 0h:00m:09s; Memory used current: 152MB peak: 167MB)
|
274 |
|
|
|
275 |
|
|
|
276 |
|
|
|
277 |
|
|
|
278 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
279 |
|
|
|
280 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
281 |
|
|
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
|
289 |
|
|
Finished restoring hierarchy (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:13s; Memory used current: 168MB peak: 229MB)
|
290 |
|
|
|
291 |
|
|
|
292 |
|
|
|
293 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
|
297 |
|
|
274 @K:conv_instances converted, 0 sequential instances remain driven by gated/generated clocks
|
298 |
|
|
|
299 |
|
|
|
300 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
301 |
|
|
|
302 |
|
|
@K:CKID0001 clk40_i port 473 cpu_clk
|
303 |
|
|
=======================================================================================
|
304 |
|
|
===== Gated/Generated Clocks =====
|
305 |
|
|
************** None **************
|
306 |
|
|
----------------------------------
|
307 |
|
|
==================================
|
308 |
|
|
|
309 |
|
|
|
310 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
311 |
|
|
|
312 |
|
|
Writing Analyst data base /home/pacito/02_Elektronik/020_V6809/6809/lattice/P6809/P6809_P6809.srm
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
|
317 |
|
|
G-2012.09L-SP1
|
318 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
# Timing Report written on Wed Dec 25 17:50:28 2013
|
328 |
|
|
#
|
329 |
|
|
|
330 |
|
|
|
331 |
|
|
Top view: CC3_top
|
332 |
|
|
Requested Frequency: 1.0 MHz
|
333 |
|
|
Wire load mode: top
|
334 |
|
|
Paths requested: 5
|
335 |
|
|
Constraint File(s):
|
336 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
337 |
|
|
|
338 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
339 |
|
|
|
340 |
|
|
|
341 |
|
|
|
342 |
|
|
Performance Summary
|
343 |
|
|
*******************
|
344 |
|
|
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
|
348 |
|
|
|
349 |
|
|
|
350 |
|
|
------------------------------------------------------------------------------------------------------------------------
|
351 |
|
|
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
|
355 |
|
|
|
356 |
|
|
|
357 |
|
|
|
358 |
|
|
|
359 |
|
|
*******************
|
360 |
|
|
|
361 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
362 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
363 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
364 |
|
|
--------------------------------------------------------------------------------------------------------------------------
|
365 |
|
|
CC3_top|clk40_i CC3_top|clk40_i | 1000.000 975.177 | No paths - | No paths - | No paths -
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
Interface Information
|
373 |
|
|
|
374 |
|
|
|
375 |
|
|
|
376 |
|
|
|
377 |
|
|
|
378 |
|
|
|
379 |
|
|
|
380 |
|
|
Detailed Report for Clock: CC3_top|clk40_i
|
381 |
|
|
|
382 |
|
|
|
383 |
|
|
|
384 |
|
|
|
385 |
|
|
Starting Points with Worst Slack
|
386 |
|
|
********************************
|
387 |
|
|
|
388 |
|
|
Starting Arrival
|
389 |
|
|
Instance Reference Type Pin Net Time Slack
|
390 |
|
|
Clock
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
cpu0.k_opcode[7] CC3_top|clk40_i FD1P3AX Q k_opcode[7] 1.344 975.183
|
394 |
|
|
|
395 |
|
|
cpu0.k_opcode[5] CC3_top|clk40_i FD1P3AX Q k_opcode[5] 1.288 975.239
|
396 |
|
|
|
397 |
|
|
cpu0.k_pp_active_reg[1] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[1] 1.188 975.356
|
398 |
|
|
|
399 |
|
|
cpu0.k_pp_active_reg[2] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[2] 1.180 975.364
|
400 |
|
|
cpu0.k_pp_active_reg[4] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[4] 1.180 975.364
|
401 |
|
|
cpu0.k_pp_active_reg[5] CC3_top|clk40_i FD1P3AX Q k_pp_active_reg[5] 1.180 975.364
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
|
405 |
|
|
Ending Points with Worst Slack
|
406 |
|
|
|
407 |
|
|
|
408 |
|
|
|
409 |
|
|
Instance Reference Type Pin Net Time Slack
|
410 |
|
|
Clock
|
411 |
|
|
---------------------------------------------------------------------------------------------------
|
412 |
|
|
|
413 |
|
|
|
414 |
|
|
cpu0.alu.regq16_pipe_22 CC3_top|clk40_i FD1P3AX D N_710 1000.089 975.319
|
415 |
|
|
cpu0.alu.regq16_pipe_33 CC3_top|clk40_i FD1P3AX D N_709 1000.089 975.462
|
416 |
|
|
cpu0.alu.regq16_pipe_44 CC3_top|clk40_i FD1P3AX D N_708 1000.089 975.462
|
417 |
|
|
cpu0.alu.regq16_pipe_55 CC3_top|clk40_i FD1P3AX D N_707 1000.089 975.605
|
418 |
|
|
cpu0.alu.regq16_pipe_66 CC3_top|clk40_i FD1P3AX D N_706 1000.089 975.605
|
419 |
|
|
cpu0.alu.cff_pipe_5 CC3_top|clk40_i FD1P3AX D N_1009 1000.089 975.676
|
420 |
|
|
|
421 |
|
|
cpu0.alu.regq16_pipe_77 CC3_top|clk40_i FD1P3AX D N_705 1000.089 975.748
|
422 |
|
|
|
423 |
|
|
|
424 |
|
|
|
425 |
|
|
|
426 |
|
|
Worst Path Information
|
427 |
|
|
|
428 |
|
|
|
429 |
|
|
|
430 |
|
|
|
431 |
|
|
Requested Period: 1000.000
|
432 |
|
|
- Setup time: -0.089
|
433 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
434 |
|
|
= Required time: 1000.089
|
435 |
|
|
|
436 |
|
|
|
437 |
|
|
|
438 |
|
|
|
439 |
|
|
|
440 |
|
|
|
441 |
|
|
Starting point: cpu0.k_opcode[1] / Q
|
442 |
|
|
Ending point: cpu0.alu.regq16_pipe / D
|
443 |
|
|
|
444 |
|
|
The end point is clocked by CC3_top|clk40_i [rising] on pin CK
|
445 |
|
|
|
446 |
|
|
Instance / Net Pin Pin Arrival No. of
|
447 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
448 |
|
|
-----------------------------------------------------------------------------------------------------------------------------
|
449 |
|
|
cpu0.k_opcode[1] FD1P3AX Q Out 1.350 1.350 -
|
450 |
|
|
k_opcode[1] Net - - - - 48
|
451 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2_1 ORCALUT4 A In 0.000 1.350 -
|
452 |
|
|
|
453 |
|
|
|
454 |
|
|
|
455 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_a6_2 ORCALUT4 Z Out 1.017 3.384 -
|
456 |
|
|
N_372 Net - - - - 1
|
457 |
|
|
|
458 |
|
|
cpu0.dec_regs.un1_dest_reg_2_sqmuxa_1_1_2 ORCALUT4 Z Out 1.017 4.401 -
|
459 |
|
|
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
un1_dest_reg_2_sqmuxa_1_0 Net - - - - 4
|
463 |
|
|
cpu0.dec_regs.path_left_addr[0] ORCALUT4 D In 0.000 5.593 -
|
464 |
|
|
cpu0.dec_regs.path_left_addr[0] ORCALUT4 Z Out 0.449 6.042 -
|
465 |
|
|
|
466 |
|
|
|
467 |
|
|
|
468 |
|
|
N_959 Net - - - - 5
|
469 |
|
|
cpu0.regs.datamux_o_alu_in_left_path_addr_1_0_RNIB1K51[0] ORCALUT4 B In 0.000 7.267 -
|
470 |
|
|
|
471 |
|
|
datamux_o_alu_in_left_path_addr_1[0] Net - - - - 55
|
472 |
|
|
cpu0.regs.path_left_data_7_am_1[0] ORCALUT4 A In 0.000 8.673 -
|
473 |
|
|
cpu0.regs.path_left_data_7_am_1[0] ORCALUT4 Z Out 1.017 9.690 -
|
474 |
|
|
path_left_data_7_am_1[0] Net - - - - 1
|
475 |
|
|
cpu0.regs.path_left_data_7_am[0] ORCALUT4 B In 0.000 9.690 -
|
476 |
|
|
cpu0.regs.path_left_data_7_am[0] ORCALUT4 Z Out 1.017 10.707 -
|
477 |
|
|
path_left_data_7_am[0] Net - - - - 1
|
478 |
|
|
cpu0.regs.path_left_data_7[0] PFUMX BLUT In 0.000 10.707 -
|
479 |
|
|
cpu0.regs.path_left_data_7[0] PFUMX Z Out -0.033 10.674 -
|
480 |
|
|
N_401 Net - - - - 1
|
481 |
|
|
cpu0.regs.path_left_data[0] L6MUX21 D0 In 0.000 10.674 -
|
482 |
|
|
cpu0.regs.path_left_data[0] L6MUX21 Z Out 0.868 11.542 -
|
483 |
|
|
regs_o_left_path_data[0] Net - - - - 3
|
484 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 C In 0.000 11.542 -
|
485 |
|
|
cpu0.alu.datamux_o_alu_in_left_path_data[0] ORCALUT4 Z Out 1.384 12.926 -
|
486 |
|
|
|
487 |
|
|
|
488 |
|
|
cpu0.alu.mul16_w_madd_0_cry_0_0 CCU2D COUT Out 1.544 14.470 -
|
489 |
|
|
mul16_w_madd_0_cry_0 Net - - - - 1
|
490 |
|
|
|
491 |
|
|
cpu0.alu.mul16_w_madd_0_cry_1_0 CCU2D S0 Out 1.621 16.091 -
|
492 |
|
|
mul16_w_madd_4 Net - - - - 2
|
493 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D A1 In 0.000 16.091 -
|
494 |
|
|
cpu0.alu.mul16_w_madd_4_cry_0_0 CCU2D COUT Out 1.544 17.636 -
|
495 |
|
|
mul16_w_madd_4_cry_0 Net - - - - 1
|
496 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D CIN In 0.000 17.636 -
|
497 |
|
|
cpu0.alu.mul16_w_madd_4_cry_1_0 CCU2D S1 Out 1.621 19.257 -
|
498 |
|
|
mul16_w_madd Net - - - - 2
|
499 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D A1 In 0.000 19.257 -
|
500 |
|
|
cpu0.alu.mul16_w_madd_cry_0_0 CCU2D COUT Out 1.544 20.801 -
|
501 |
|
|
mul16_w_madd_cry_0 Net - - - - 1
|
502 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D CIN In 0.000 20.801 -
|
503 |
|
|
cpu0.alu.mul16_w_madd_cry_1_0 CCU2D COUT Out 0.143 20.944 -
|
504 |
|
|
mul16_w_madd_cry_2 Net - - - - 1
|
505 |
|
|
cpu0.alu.mul16_w_madd_cry_3_0 CCU2D CIN In 0.000 20.944 -
|
506 |
|
|
|
507 |
|
|
|
508 |
|
|
|
509 |
|
|
cpu0.alu.mul16_w_madd_cry_5_0 CCU2D COUT Out 0.143 21.230 -
|
510 |
|
|
mul16_w_madd_cry_6 Net - - - - 1
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
mul16_w_madd_cry_8 Net - - - - 1
|
514 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D CIN In 0.000 21.372 -
|
515 |
|
|
cpu0.alu.mul16_w_madd_cry_9_0 CCU2D COUT Out 0.143 21.515 -
|
516 |
|
|
mul16_w_madd_cry_10 Net - - - - 1
|
517 |
|
|
cpu0.alu.mul16_w_madd_s_11_0 CCU2D CIN In 0.000 21.515 -
|
518 |
|
|
|
519 |
|
|
mul16_w[15] Net - - - - 1
|
520 |
|
|
cpu0.alu.q16_11_bm[15] ORCALUT4 A In 0.000 23.064 -
|
521 |
|
|
cpu0.alu.q16_11_bm[15] ORCALUT4 Z Out 1.017 24.081 -
|
522 |
|
|
|
523 |
|
|
cpu0.alu.q16_11[15] PFUMX ALUT In 0.000 24.081 -
|
524 |
|
|
cpu0.alu.q16_11[15] PFUMX Z Out 0.214 24.295 -
|
525 |
|
|
N_696 Net - - - - 1
|
526 |
|
|
cpu0.alu.q16_12[15] ORCALUT4 B In 0.000 24.295 -
|
527 |
|
|
cpu0.alu.q16_12[15] ORCALUT4 Z Out 0.617 24.912 -
|
528 |
|
|
|
529 |
|
|
cpu0.alu.regq16_pipe FD1P3AX D In 0.000 24.912 -
|
530 |
|
|
=============================================================================================================================
|
531 |
|
|
|
532 |
|
|
|
533 |
|
|
|
534 |
|
|
##### END OF TIMING REPORT #####]
|
535 |
|
|
|
536 |
|
|
---------------------------------------
|
537 |
|
|
Resource Usage Report
|
538 |
|
|
Part: lcmxo2_7000he-4
|
539 |
|
|
|
540 |
|
|
Register bits: 469 of 6864 (7%)
|
541 |
|
|
PIC Latch: 0
|
542 |
|
|
I/O cells: 49
|
543 |
|
|
Block Rams : 2 of 26 (7%)
|
544 |
|
|
|
545 |
|
|
|
546 |
|
|
Details:
|
547 |
|
|
CCU2D: 205
|
548 |
|
|
DP8KC: 2
|
549 |
|
|
FD1P3AX: 449
|
550 |
|
|
FD1P3DX: 6
|
551 |
|
|
FD1P3IX: 1
|
552 |
|
|
FD1P3JX: 4
|
553 |
|
|
FD1S3AX: 1
|
554 |
|
|
GSR: 1
|
555 |
|
|
IB: 1
|
556 |
|
|
INV: 5
|
557 |
|
|
L6MUX21: 21
|
558 |
|
|
OB: 48
|
559 |
|
|
OFS1P3DX: 8
|
560 |
|
|
ORCALUT4: 1904
|
561 |
|
|
PFUMX: 224
|
562 |
|
|
PUR: 1
|
563 |
|
|
VHI: 4
|
564 |
|
|
VLO: 10
|
565 |
|
|
true: 6
|
566 |
|
|
Mapper successful!
|
567 |
|
|
|
568 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:14s; CPU Time elapsed 0h:00m:14s; Memory used current: 44MB peak: 229MB)
|
569 |
|
|
|
570 |
|
|
Process took 0h:00m:14s realtime, 0h:00m:14s cputime
|
571 |
|
|
# Wed Dec 25 17:50:28 2013
|
572 |
|
|
|
573 |
|
|
###########################################################]
|
574 |
|
|
|
575 |
|
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|
576 |
|
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|
577 |
|
|
<BR>
|
578 |
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|
579 |
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|
580 |
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|
581 |
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|
582 |
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|
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|
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|
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|
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|
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|
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|
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|
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|
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617 |
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|
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|
619 |
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|
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|
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|
629 |
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|
630 |
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