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ale500 |
Release 10.1 par K.31 (lin)
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Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
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node01.pacito.sys:: Wed Dec 25 11:42:55 2013
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par -w -intstyle ise -ol std -t 1 CC3_top_x_map.ncd CC3_top_x.ncd CC3_top_x.pcf
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Constraints file: CC3_top_x.pcf.
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Loading device for application Rf_Device from file 'v100.nph' in environment /home/pacito/Xilinx/10.1/ISE.
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"CC3_top_x" is an NCD, version 3.2, device xc2s100, package pq208, speed -5
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Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing voltage to 2.375 Volts. (default - Range: 2.375 to 2.625 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
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the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
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balance between the fastest runtime and best performance, set the effort level to "med".
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Device speed data version: "PRODUCTION 1.27 2008-01-09".
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Device Utilization Summary:
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Number of BLOCKRAMs 1 out of 10 10%
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Number of GCLKs 1 out of 4 25%
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Number of External GCLKIOBs 1 out of 4 25%
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Number of LOCed GCLKIOBs 0 out of 1 0%
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Number of External IOBs 26 out of 140 18%
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Number of LOCed IOBs 0 out of 26 0%
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Number of SLICEs 1198 out of 1200 99%
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Overall effort level (-ol): Standard
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): Standard
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Starting Placer
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Phase 1.1
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Phase 1.1 (Checksum:98c581) REAL time: 0 secs
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Phase 2.7
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Phase 2.7 (Checksum:1312cfe) REAL time: 0 secs
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Phase 3.31
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Phase 3.31 (Checksum:1c9c37d) REAL time: 0 secs
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Phase 4.23
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Phase 4.23 (Checksum:26259fc) REAL time: 0 secs
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Phase 5.3
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...
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Phase 5.3 (Checksum:2faf07b) REAL time: 0 secs
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Phase 6.5
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Phase 6.5 (Checksum:39386fa) REAL time: 0 secs
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Phase 7.8
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..........
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.............................................................
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....................
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..............................................................................................................
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..................................
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....................................
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Phase 7.8 (Checksum:e43d41) REAL time: 4 secs
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Phase 8.5
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Phase 8.5 (Checksum:4c4b3f8) REAL time: 4 secs
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Phase 9.18
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Phase 9.18 (Checksum:55d4a77) REAL time: 6 secs
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Phase 10.5
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Phase 10.5 (Checksum:5f5e0f6) REAL time: 6 secs
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REAL time consumed by placer: 6 secs
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CPU time consumed by placer: 6 secs
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Writing design to file CC3_top_x.ncd
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Total REAL time to Placer completion: 6 secs
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Total CPU time to Placer completion: 6 secs
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Starting Router
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Phase 1: 8784 unrouted; REAL time: 6 secs
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Phase 2: 8535 unrouted; REAL time: 7 secs
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Phase 3: 2951 unrouted; REAL time: 7 secs
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Phase 4: 2951 unrouted; (958) REAL time: 7 secs
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Phase 5: 2960 unrouted; (0) REAL time: 7 secs
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Phase 6: 0 unrouted; (0) REAL time: 8 secs
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Phase 7: 0 unrouted; (0) REAL time: 9 secs
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Phase 8: 0 unrouted; (0) REAL time: 9 secs
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Phase 9: 0 unrouted; (0) REAL time: 9 secs
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Total REAL time to Router completion: 9 secs
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Total CPU time to Router completion: 9 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| clk32_i_BUFGP | GCLKBUF1| No | 249 | 0.481 | 0.677 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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Timing Score: 0
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
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requested value.
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net clk | SETUP | N/A| 66.168ns| N/A| 0
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32_i_BUFGP | HOLD | 2.524ns| | 0| 0
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------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
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constraint does not cover any paths or that it has no requested value.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 10 secs
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Total CPU time to PAR completion: 10 secs
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Peak Memory Usage: 120 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 2
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Writing design to file CC3_top_x.ncd
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PAR done!
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