| 1 |
2 |
ale500 |
Release 10.1 Map K.31 (lin)
|
| 2 |
|
|
Xilinx Map Application Log File for Design 'CC3_top_x'
|
| 3 |
|
|
|
| 4 |
|
|
Design Information
|
| 5 |
|
|
------------------
|
| 6 |
|
|
Command Line : map -ise
|
| 7 |
|
|
/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise
|
| 8 |
|
|
-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd
|
| 9 |
|
|
CC3_top_x.ngd CC3_top_x.pcf
|
| 10 |
|
|
Target Device : xc2s100
|
| 11 |
|
|
Target Package : pq208
|
| 12 |
|
|
Target Speed : -5
|
| 13 |
|
|
Mapper Version : spartan2 -- $Revision: 1.46 $
|
| 14 |
|
|
Mapped Date : Wed Dec 25 11:42:53 2013
|
| 15 |
|
|
|
| 16 |
|
|
Mapping design into LUTs...
|
| 17 |
|
|
Running directed packing...
|
| 18 |
|
|
Running delay-based LUT packing...
|
| 19 |
|
|
Running related packing...
|
| 20 |
|
|
|
| 21 |
|
|
Design Summary
|
| 22 |
|
|
--------------
|
| 23 |
|
|
|
| 24 |
|
|
Design Summary:
|
| 25 |
|
|
Number of errors: 0
|
| 26 |
|
|
Number of warnings: 6
|
| 27 |
|
|
Logic Utilization:
|
| 28 |
|
|
Number of Slice Flip Flops: 301 out of 2,400 12%
|
| 29 |
|
|
Number of 4 input LUTs: 2,239 out of 2,400 93%
|
| 30 |
|
|
Logic Distribution:
|
| 31 |
|
|
Number of occupied Slices: 1,198 out of 1,200 99%
|
| 32 |
|
|
Number of Slices containing only related logic: 1,198 out of 1,198 100%
|
| 33 |
|
|
Number of Slices containing unrelated logic: 0 out of 1,198 0%
|
| 34 |
|
|
*See NOTES below for an explanation of the effects of unrelated logic
|
| 35 |
|
|
Total Number of 4 input LUTs: 2,291 out of 2,400 95%
|
| 36 |
|
|
Number used as logic: 2,239
|
| 37 |
|
|
Number used as a route-thru: 52
|
| 38 |
|
|
Number of bonded IOBs: 26 out of 140 18%
|
| 39 |
|
|
Number of Block RAMs: 1 out of 10 10%
|
| 40 |
|
|
Number of GCLKs: 1 out of 4 25%
|
| 41 |
|
|
Number of GCLKIOBs: 1 out of 4 25%
|
| 42 |
|
|
|
| 43 |
|
|
Peak Memory Usage: 148 MB
|
| 44 |
|
|
Total REAL time to MAP completion: 2 secs
|
| 45 |
|
|
Total CPU time to MAP completion: 2 secs
|
| 46 |
|
|
|
| 47 |
|
|
NOTES:
|
| 48 |
|
|
|
| 49 |
|
|
Related logic is defined as being logic that shares connectivity - e.g. two
|
| 50 |
|
|
LUTs are "related" if they share common inputs. When assembling slices,
|
| 51 |
|
|
Map gives priority to combine logic that is related. Doing so results in
|
| 52 |
|
|
the best timing performance.
|
| 53 |
|
|
|
| 54 |
|
|
Unrelated logic shares no connectivity. Map will only begin packing
|
| 55 |
|
|
unrelated logic into a slice once 99% of the slices are occupied through
|
| 56 |
|
|
related logic packing.
|
| 57 |
|
|
|
| 58 |
|
|
Note that once logic distribution reaches the 99% level through related
|
| 59 |
|
|
logic packing, this does not mean the device is completely utilized.
|
| 60 |
|
|
Unrelated logic packing will then begin, continuing until all usable LUTs
|
| 61 |
|
|
and FFs are occupied. Depending on your timing budget, increased levels of
|
| 62 |
|
|
unrelated logic packing may adversely affect the overall timing performance
|
| 63 |
|
|
of your design.
|
| 64 |
|
|
|
| 65 |
|
|
Mapping completed.
|
| 66 |
|
|
See MAP report file "CC3_top_x_map.mrp" for details.
|
