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Release 10.1 Map K.31 (lin)
Xilinx Mapping Report File for Design 'CC3_top_x'
 
Design Information
------------------
Command Line   : map -ise
/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise
-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd
CC3_top_x.ngd CC3_top_x.pcf
Target Device  : xc2s100
Target Package : pq208
Target Speed   : -5
Mapper Version : spartan2 -- $Revision: 1.46 $
Mapped Date    : Wed Dec 25 11:42:53 2013
 
Design Summary
--------------
Number of errors:      0
Number of warnings:    6
Logic Utilization:
  Number of Slice Flip Flops:       301 out of  2,400   12%
  Number of 4 input LUTs:         2,239 out of  2,400   93%
Logic Distribution:
    Number of occupied Slices:                       1,198 out of  1,200   99%
    Number of Slices containing only related logic:  1,198 out of  1,198  100%
    Number of Slices containing unrelated logic:         0 out of  1,198    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:        2,291 out of  2,400   95%
      Number used as logic:                     2,239
      Number used as a route-thru:                 52
   Number of bonded IOBs:            26 out of    140   18%
   Number of Block RAMs:              1 out of     10   10%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
 
Peak Memory Usage:  148 MB
Total REAL time to MAP completion:  2 secs
Total CPU time to MAP completion:   2 secs
 
NOTES:
 
   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.
 
   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.
 
   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.
 
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
 
Section 1 - Errors
------------------
 
Section 2 - Warnings
--------------------
WARNING:Pack:266 - The function generator cpu/k_pp_active_reg_mux0000<3>11
   failed to merge with F5 multiplexer cpu/state_mux0000<1>1_f5.  There is a
   conflict for the FXMUX.  The design will exhibit suboptimal timing.
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
        cpu/alu/Mmult_mul16_w_Madd1_cy<8>
        cpu/alu/Mmult_mul16_w_Madd1_cy<9>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
        cpu/alu/Mmult_mul16_w_Madd_cy<7>
        cpu/alu/Mmult_mul16_w_Madd_cy<8>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
        cpu/alu/Mmult_mul16_w_Madd3_cy<11>
        cpu/alu/Mmult_mul16_w_Madd3_cy<12>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
        cpu/alu/Mmult_mul16_w_Madd5_cy<5>
        cpu/alu/Mmult_mul16_w_Madd5_cy<6>
WARNING:Pack:249 - The following adjacent carry multiplexers occupy different
   slice components.  The resulting carry chain will have suboptimal timing.
        cpu/alu/Mmult_mul16_w_Madd2_cy<7>
        cpu/alu/Mmult_mul16_w_Madd2_cy<8>
 
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs.
 
Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) optimized away
 
Section 5 - Removed Logic
-------------------------
 
Optimized Block(s):
TYPE            BLOCK
GND             XST_GND
VCC             XST_VCC
 
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
 
Section 6 - IOB Properties
--------------------------
 
+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk32_i                            | GCLKIOB | INPUT     | LVTTL       |          |      |          |          |       |
| mem_addr_o<0>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<1>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<2>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<3>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<4>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<5>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<6>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<7>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<8>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<9>                      | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<10>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<11>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<12>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<13>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<14>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_addr_o<15>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<0>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<1>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<2>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<3>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<4>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<5>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<6>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_data_io<7>                     | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_oe_n                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
| mem_we_n                           | IOB     | OUTPUT    | LVTTL       | 12       | SLOW |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+
 
Section 7 - RPMs
----------------
 
Section 8 - Guide Report
------------------------
Guide not run on this design.
 
Section 9 - Area Group and Partition Summary
--------------------------------------------
 
Area Group Information
----------------------
 
  No area groups were found in this design.
 
----------------------
 
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
 
Section 11 - Timing Report
--------------------------
No timing report for this architecture.
 
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
 
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.

Line No.	Rev	Author	Line
1	2	ale500	`Release 10.1 Map K.31 (lin)`
2			`Xilinx Mapping Report File for Design 'CC3_top_x'`
3
4			`Design Information`
5			`------------------`
6			`Command Line : map -ise`
7			`/home/pacito/02_Elektronik/020_V6809/6809/xilinx/P6809/P6809.ise -intstyle ise`
8			`-p xc2s100-pq208-5 -cm area -pr off -k 4 -c 100 -tx off -o CC3_top_x_map.ncd`
9			`CC3_top_x.ngd CC3_top_x.pcf`
10			`Target Device : xc2s100`
11			`Target Package : pq208`
12			`Target Speed : -5`
13			`Mapper Version : spartan2 -- $Revision: 1.46 $`
14			`Mapped Date : Wed Dec 25 11:42:53 2013`
15
16			`Design Summary`
17			`--------------`
18			`Number of errors: 0`
19			`Number of warnings: 6`
20			`Logic Utilization:`
21			`Number of Slice Flip Flops: 301 out of 2,400 12%`
22			`Number of 4 input LUTs: 2,239 out of 2,400 93%`
23			`Logic Distribution:`
24			`Number of occupied Slices: 1,198 out of 1,200 99%`
25			`Number of Slices containing only related logic: 1,198 out of 1,198 100%`
26			`Number of Slices containing unrelated logic: 0 out of 1,198 0%`
27			`*See NOTES below for an explanation of the effects of unrelated logic`
28			`Total Number of 4 input LUTs: 2,291 out of 2,400 95%`
29			`Number used as logic: 2,239`
30			`Number used as a route-thru: 52`
31			`Number of bonded IOBs: 26 out of 140 18%`
32			`Number of Block RAMs: 1 out of 10 10%`
33			`Number of GCLKs: 1 out of 4 25%`
34			`Number of GCLKIOBs: 1 out of 4 25%`
35
36			`Peak Memory Usage: 148 MB`
37			`Total REAL time to MAP completion: 2 secs`
38			`Total CPU time to MAP completion: 2 secs`
39
40			`NOTES:`
41
42			`Related logic is defined as being logic that shares connectivity - e.g. two`
43			`LUTs are "related" if they share common inputs. When assembling slices,`
44			`Map gives priority to combine logic that is related. Doing so results in`
45			`the best timing performance.`
46
47			`Unrelated logic shares no connectivity. Map will only begin packing`
48			`unrelated logic into a slice once 99% of the slices are occupied through`
49			`related logic packing.`
50
51			`Note that once logic distribution reaches the 99% level through related`
52			`logic packing, this does not mean the device is completely utilized.`
53			`Unrelated logic packing will then begin, continuing until all usable LUTs`
54			`and FFs are occupied. Depending on your timing budget, increased levels of`
55			`unrelated logic packing may adversely affect the overall timing performance`
56			`of your design.`
57
58			`Table of Contents`
59			`-----------------`
60			`Section 1 - Errors`
61			`Section 2 - Warnings`
62			`Section 3 - Informational`
63			`Section 4 - Removed Logic Summary`
64			`Section 5 - Removed Logic`
65			`Section 6 - IOB Properties`
66			`Section 7 - RPMs`
67			`Section 8 - Guide Report`
68			`Section 9 - Area Group and Partition Summary`
69			`Section 10 - Modular Design Summary`
70			`Section 11 - Timing Report`
71			`Section 12 - Configuration String Information`
72			`Section 13 - Control Set Information`
73			`Section 14 - Utilization by Hierarchy`
74
75			`Section 1 - Errors`
76			`------------------`
77
78			`Section 2 - Warnings`
79			`--------------------`
80			`WARNING:Pack:266 - The function generator cpu/k_pp_active_reg_mux0000<3>11`
81			`failed to merge with F5 multiplexer cpu/state_mux0000<1>1_f5. There is a`
82			`conflict for the FXMUX. The design will exhibit suboptimal timing.`
83			`WARNING:Pack:249 - The following adjacent carry multiplexers occupy different`
84			`slice components. The resulting carry chain will have suboptimal timing.`
85			`cpu/alu/Mmult_mul16_w_Madd1_cy<8>`
86			`cpu/alu/Mmult_mul16_w_Madd1_cy<9>`
87			`WARNING:Pack:249 - The following adjacent carry multiplexers occupy different`
88			`slice components. The resulting carry chain will have suboptimal timing.`
89			`cpu/alu/Mmult_mul16_w_Madd_cy<7>`
90			`cpu/alu/Mmult_mul16_w_Madd_cy<8>`
91			`WARNING:Pack:249 - The following adjacent carry multiplexers occupy different`
92			`slice components. The resulting carry chain will have suboptimal timing.`
93			`cpu/alu/Mmult_mul16_w_Madd3_cy<11>`
94			`cpu/alu/Mmult_mul16_w_Madd3_cy<12>`
95			`WARNING:Pack:249 - The following adjacent carry multiplexers occupy different`
96			`slice components. The resulting carry chain will have suboptimal timing.`
97			`cpu/alu/Mmult_mul16_w_Madd5_cy<5>`
98			`cpu/alu/Mmult_mul16_w_Madd5_cy<6>`
99			`WARNING:Pack:249 - The following adjacent carry multiplexers occupy different`
100			`slice components. The resulting carry chain will have suboptimal timing.`
101			`cpu/alu/Mmult_mul16_w_Madd2_cy<7>`
102			`cpu/alu/Mmult_mul16_w_Madd2_cy<8>`
103
104			`Section 3 - Informational`
105			`-------------------------`
106			`INFO:MapLib:562 - No environment variables are currently set.`
107			`INFO:LIT:244 - All of the single ended outputs in this design are using slew`
108			`rate limited output drivers. The delay on speed critical single ended outputs`
109			`can be dramatically reduced by designating them as fast outputs.`
110
111			`Section 4 - Removed Logic Summary`
112			`---------------------------------`
113			`2 block(s) optimized away`
114
115			`Section 5 - Removed Logic`
116			`-------------------------`
117
118			`Optimized Block(s):`
119			`TYPE BLOCK`
120			`GND XST_GND`
121			`VCC XST_VCC`
122
123			`To enable printing of redundant blocks removed and signals merged, set the`
124			`detailed map report option and rerun map.`
125
126			`Section 6 - IOB Properties`
127			`--------------------------`
128
129			`+------------------------------------------------------------------------------------------------------------------------+`
130			`\| IOB Name \| Type \| Direction \| IO Standard \| Drive \| Slew \| Reg (s) \| Resistor \| IOB \|`
131			`\| \| \| \| \| Strength \| Rate \| \| \| Delay \|`
132			`+------------------------------------------------------------------------------------------------------------------------+`
133			`\| clk32_i \| GCLKIOB \| INPUT \| LVTTL \| \| \| \| \| \|`
134			`\| mem_addr_o<0> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
135			`\| mem_addr_o<1> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
136			`\| mem_addr_o<2> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
137			`\| mem_addr_o<3> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
138			`\| mem_addr_o<4> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
139			`\| mem_addr_o<5> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
140			`\| mem_addr_o<6> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
141			`\| mem_addr_o<7> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
142			`\| mem_addr_o<8> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
143			`\| mem_addr_o<9> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
144			`\| mem_addr_o<10> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
145			`\| mem_addr_o<11> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
146			`\| mem_addr_o<12> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
147			`\| mem_addr_o<13> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
148			`\| mem_addr_o<14> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
149			`\| mem_addr_o<15> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
150			`\| mem_data_io<0> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
151			`\| mem_data_io<1> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
152			`\| mem_data_io<2> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
153			`\| mem_data_io<3> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
154			`\| mem_data_io<4> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
155			`\| mem_data_io<5> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
156			`\| mem_data_io<6> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
157			`\| mem_data_io<7> \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
158			`\| mem_oe_n \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
159			`\| mem_we_n \| IOB \| OUTPUT \| LVTTL \| 12 \| SLOW \| \| \| \|`
160			`+------------------------------------------------------------------------------------------------------------------------+`
161
162			`Section 7 - RPMs`
163			`----------------`
164
165			`Section 8 - Guide Report`
166			`------------------------`
167			`Guide not run on this design.`
168
169			`Section 9 - Area Group and Partition Summary`
170			`--------------------------------------------`
171
172			`Area Group Information`
173			`----------------------`
174
175			`No area groups were found in this design.`
176
177			`----------------------`
178
179			`Section 10 - Modular Design Summary`
180			`-----------------------------------`
181			`Modular Design not used for this design.`
182
183			`Section 11 - Timing Report`
184			`--------------------------`
185			`No timing report for this architecture.`
186
187			`Section 12 - Configuration String Details`
188			`-----------------------------------------`
189			`Use the "-detail" map option to print out Configuration Strings`
190
191			`Section 13 - Control Set Information`
192			`------------------------------------`
193			`No control set information for this architecture.`

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[/] [6809_6309_compatible_core/] [trunk/] [syn/] [xilinx/] [logs/] [CC3_top_x_map.mrp] - Blame information for rev 2