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entactogen |
-- Copyright (c) 2010 Antonio de la Piedra
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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-- A VHDL model of the IEEE 802.15.4 physical layer.
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.numeric_std.ALL;
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entity chip_gen is
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Port( chip_gen_rst : IN STD_LOGIC;
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chip_gen_clk : IN STD_LOGIC;
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chip_gen_symbol: IN STD_LOGIC_VECTOR(3 downto 0);
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chip_gen_iOut: OUT STD_LOGIC;
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chip_gen_qOut: OUT STD_LOGIC);
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end chip_gen;
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architecture Behavioral of chip_gen is
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TYPE symbol_array is ARRAY (7 downto 0) OF STD_LOGIC_VECTOR (3 downto 0);
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CONSTANT symbols: symbol_array := ( "0111",
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"0110",
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"0101",
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"0100",
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"0011",
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"0010",
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"0001",
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"0000");
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CONSTANT symbol_zero_i : STD_LOGIC_VECTOR (15 downto 0) := "1010100100010111";
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CONSTANT symbol_zero_q : STD_LOGIC_VECTOR (15 downto 0) := "1101100111000010";
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SIGNAL muxIout, muxQout: STD_LOGIC;
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SIGNAL sr1, sr2 : STD_LOGIC_VECTOR(15 downto 0);
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begin
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shr: process(chip_gen_clk, chip_gen_rst)
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begin
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IF (chip_gen_rst = '1') then
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sr1 <= symbol_zero_i;
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sr2 <= symbol_zero_q;
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elsif rising_edge(chip_gen_clk) then
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sr1 <= std_logic_vector(unsigned(sr1) rol 1);
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sr2 <= std_logic_vector(unsigned(sr2) rol 1);
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end if;
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end process;
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muxI: process(chip_gen_symbol, sr1)
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begin
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IF (chip_gen_symbol(2 downto 0) = symbols(0)(2 downto 0)) then
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muxIout <= sr1(0);
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elsif (chip_gen_symbol(2 downto 0) = symbols(1)(2 downto 0)) then
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muxIout <= sr1(2);
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elsif (chip_gen_symbol(2 downto 0) = symbols(2)(2 downto 0)) then
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muxIout <= sr1(4);
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elsif (chip_gen_symbol(2 downto 0) = symbols(3)(2 downto 0)) then
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muxIout <= sr1(6);
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elsif (chip_gen_symbol(2 downto 0) = symbols(4)(2 downto 0)) then
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muxIout <= sr1(8);
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elsif (chip_gen_symbol(2 downto 0) = symbols(5)(2 downto 0)) then
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muxIout <= sr1(10);
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elsif (chip_gen_symbol(2 downto 0) = symbols(6)(2 downto 0)) then
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muxIout <= sr1(12);
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elsif (chip_gen_symbol(2 downto 0) = symbols(7)(2 downto 0)) then
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muxIout <= sr1(14);
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end if;
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end process;
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muxQ: process(chip_gen_symbol, sr2)
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begin
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IF (chip_gen_symbol(2 downto 0) = symbols(0)(2 downto 0)) then
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muxQout <= sr2(0) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(1)(2 downto 0)) then
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muxQout <= sr2(2) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(2)(2 downto 0)) then
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muxQout <= sr2(4) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(3)(2 downto 0)) then
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muxQout <= sr2(6) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(4)(2 downto 0)) then
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muxQout <= sr2(8) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(5)(2 downto 0)) then
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muxQout <= sr2(10) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(6)(2 downto 0)) then
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muxQout <= sr2(12) xor chip_gen_symbol(3);
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elsif (chip_gen_symbol(2 downto 0) = symbols(7)(2 downto 0)) then
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muxQout <= sr2(14) xor chip_gen_symbol(3);
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end if;
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end process;
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chip_gen_iOut <= muxIout;
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chip_gen_qOut <= muxQout;
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end Behavioral;
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