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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_decoder.v] - Blame information for rev 23

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1 10 markom
////////////////////////////////////////////////////////////////////// ////                                                              ////
2 2 simont
////  8051 core decoder                                           ////
3
////                                                              ////
4
////  This file is part of the 8051 cores project                 ////
5
////  http://www.opencores.org/cores/8051/                        ////
6
////                                                              ////
7
////  Description                                                 ////
8
////   Main 8051 core module. decodes instruction and creates     ////
9
////   control sigals.                                            ////
10
////                                                              ////
11
////  To Do:                                                      ////
12 8 markom
////   optimize state machine, especially IDS ASS and AS3         ////
13 2 simont
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Simon Teran, simont@opencores.org                     ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// ver: 1
45
//
46
 
47
// synopsys translate_off
48
`include "oc8051_timescale.v"
49
// synopsys translate_on
50
 
51
`include "oc8051_defines.v"
52
 
53
 
54
 
55
module oc8051_decoder (clk, rst, op_in, eq, ram_rd_sel, ram_wr_sel, bit_addr,
56
wr, src_sel1, src_sel2, src_sel3, alu_op, psw_set, cy_sel, imm_sel, pc_wr,
57
pc_sel, comp_sel, rom_addr_sel, ext_addr_sel, wad2, rd, write_x, reti,
58
rmw);
59
//
60
// clk          (in)  clock
61
// rst          (in)  reset
62
// op_in        (in)  operation code [oc8051_op_select.op1]
63
// eq           (in)  compare result [oc8051_comp.eq]
64
// ram_rd_sel   (out) select, whitch address will be send to ram for read [oc8051_ram_rd_sel.sel, oc8051_sp.ram_rd_sel]
65
// ram_wr_sel   (out) select, whitch address will be send to ram for write [oc8051_ram_wr_sel.sel -r, oc8051_sp.ram_wr_sel -r]
66
// wr           (out) write - if 1 then we will write to ram [oc8051_ram_top.wr -r, oc8051_acc.wr -r, oc8051_b_register.wr -r, oc8051_sp.wr-r, oc8051_dptr.wr -r, oc8051_psw.wr -r, oc8051_indi_addr.wr -r, oc8051_ports.wr -r]
67
// src_sel1     (out) select alu source 1 [oc8051_alu_src1_sel.sel -r]
68
// src_sel2     (out) select alu source 2 [oc8051_alu_src2_sel.sel -r]
69
// src_sel3     (out) select alu source 3 [oc8051_alu_src3_sel.sel -r]
70
// alu_op       (out) alu operation [oc8051_alu.op_code -r]
71
// psw_set      (out) will we remember cy, ac, ov from alu [oc8051_psw.set -r]
72
// cy_sel       (out) carry in alu select [oc8051_cy_select.cy_sel -r]
73
// comp_sel     (out) compare source select [oc8051_comp.sel]
74
// bit_addr     (out) if instruction is bit addresable [oc8051_ram_top.bit_addr -r, oc8051_acc.wr_bit -r, oc8051_b_register.wr_bit-r, oc8051_sp.wr_bit -r, oc8051_dptr.wr_bit -r, oc8051_psw.wr_bit -r, oc8051_indi_addr.wr_bit -r, oc8051_ports.wr_bit -r]
75
// wad2         (out) write acc from destination 2 [oc8051_acc.wad2 -r]
76
// imm_sel      (out) immediate select [oc8051_immediate_sel.sel -r]
77
// pc_wr        (out) pc write [oc8051_pc.wr]
78
// pc_sel       (out) pc select [oc8051_pc.pc_wr_sel]
79
// rom_addr_sel (out) rom address select (alu destination or pc) [oc8051_rom_addr_sel.select]
80
// ext_addr_sel (out) external address select (dptr or Ri) [oc8051_ext_addr_sel.select]
81
// rd           (out) read from rom [oc8051_pc.rd, oc8051_op_select.rd]
82
// write_x      (out) write to external rom [pin]
83
// reti         (out) return from interrupt [pin]
84
// rmw          (out) read modify write feature [oc8051_ports.rmw]
85
//
86
 
87
input clk, rst, eq;
88
input [7:0] op_in;
89
 
90
output wr, reti, write_x, bit_addr, src_sel3, rom_addr_sel, ext_addr_sel,
91
pc_wr, wad2, rmw;
92 17 simont
output [1:0] ram_rd_sel, src_sel1, src_sel2, psw_set, cy_sel, pc_sel, comp_sel;
93
output [2:0] ram_wr_sel, imm_sel;
94 2 simont
output [3:0] alu_op;
95
output rd;
96
 
97
reg reti, write_x, rmw;
98
reg wr,  bit_addr, src_sel3, rom_addr_sel, ext_addr_sel, pc_wr, wad2;
99 9 markom
reg [1:0] comp_sel, psw_set, ram_rd_sel, src_sel1, src_sel2, pc_sel, cy_sel;
100 2 simont
reg [3:0] alu_op;
101 9 markom
reg [2:0] ram_wr_sel, imm_sel;
102 2 simont
 
103
//
104
// state        if 2'b00 then normal execution, sle instructin that need more than one clock
105
// op           instruction buffer
106
reg [1:0] state;
107
reg [7:0] op;
108
 
109
//
110
// if state = 2'b00 then read nex instruction
111
assign rd = !state[0] & !state[1];
112
 
113
//
114
// main block
115
// case of instruction set control signals
116 5 markom
always @(op_in or eq or state or op)
117 2 simont
begin
118
    case (state)
119
      2'b01: begin
120
    casex (op)
121
      `OC8051_ACALL :begin
122
          ram_rd_sel = `OC8051_RRS_DC;
123
          ram_wr_sel = `OC8051_RWS_SP;
124
          src_sel1 = `OC8051_ASS_IMM;
125
          src_sel2 = `OC8051_ASS_DC;
126
          alu_op = `OC8051_ALU_NOP;
127
          imm_sel = `OC8051_IDS_PCH;
128
          wr = 1'b1;
129
          psw_set = `OC8051_PS_NOT;
130
          cy_sel = `OC8051_CY_0;
131
          pc_wr = `OC8051_PCW_N;
132
          pc_sel = `OC8051_PIS_DC;
133
          comp_sel = `OC8051_CSS_DC;
134
          src_sel3 = `OC8051_AS3_DC;
135
          comp_sel = `OC8051_CSS_DC;
136
          rmw = `OC8051_RMW_N;
137
          bit_addr = 1'b0;
138
          wad2 = `OC8051_WAD_N;
139
          rom_addr_sel = `OC8051_RAS_PC;
140
          ext_addr_sel = `OC8051_EAS_DC;
141
 
142
        end
143
      `OC8051_AJMP : begin
144
          ram_rd_sel = `OC8051_RRS_DC;
145
          ram_wr_sel = `OC8051_RWS_DC;
146
          src_sel1 = `OC8051_ASS_DC;
147
          src_sel2 = `OC8051_ASS_DC;
148
          alu_op = `OC8051_ALU_NOP;
149
          imm_sel = `OC8051_IDS_DC;
150
          wr = 1'b0;
151
          psw_set = `OC8051_PS_NOT;
152
          cy_sel = `OC8051_CY_0;
153
          pc_wr = `OC8051_PCW_N;
154
          pc_sel = `OC8051_PIS_DC;
155
          comp_sel = `OC8051_CSS_DC;
156
          src_sel3 = `OC8051_AS3_DC;
157
          comp_sel = `OC8051_CSS_DC;
158
          rmw = `OC8051_RMW_N;
159
          bit_addr = 1'b0;
160
          wad2 = `OC8051_WAD_N;
161
          rom_addr_sel = `OC8051_RAS_PC;
162
          ext_addr_sel = `OC8051_EAS_DC;
163
 
164
        end
165
      `OC8051_LCALL :begin
166
          ram_rd_sel = `OC8051_RRS_DC;
167
          ram_wr_sel = `OC8051_RWS_SP;
168
          src_sel1 = `OC8051_ASS_IMM;
169
          src_sel2 = `OC8051_ASS_DC;
170
          alu_op = `OC8051_ALU_NOP;
171
          imm_sel = `OC8051_IDS_PCH;
172
          wr = 1'b1;
173
          psw_set = `OC8051_PS_NOT;
174
          cy_sel = `OC8051_CY_0;
175
          pc_wr = `OC8051_PCW_N;
176
          pc_sel = `OC8051_PIS_DC;
177
          comp_sel = `OC8051_CSS_DC;
178
          src_sel3 = `OC8051_AS3_DC;
179
          comp_sel = `OC8051_CSS_DC;
180
          rmw = `OC8051_RMW_N;
181
          bit_addr = 1'b0;
182
          wad2 = `OC8051_WAD_N;
183
          rom_addr_sel = `OC8051_RAS_PC;
184
          ext_addr_sel = `OC8051_EAS_DC;
185
 
186
        end
187
      `OC8051_MOVC_DP :begin
188
          ram_rd_sel = `OC8051_RRS_DC;
189
          ram_wr_sel = `OC8051_RWS_ACC;
190
          src_sel1 = `OC8051_ASS_IMM;
191
          src_sel2 = `OC8051_ASS_DC;
192
          alu_op = `OC8051_ALU_NOP;
193
          wr = 1'b1;
194
          psw_set = `OC8051_PS_NOT;
195
          cy_sel = `OC8051_CY_0;
196
          pc_wr = `OC8051_PCW_N;
197
          pc_sel = `OC8051_PIS_DC;
198
          imm_sel = `OC8051_IDS_OP1;
199
          src_sel3 = `OC8051_AS3_DP;
200
          comp_sel = `OC8051_CSS_DC;
201
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
202
          wad2 = `OC8051_WAD_N;
203
          rom_addr_sel = `OC8051_RAS_PC;
204
          ext_addr_sel = `OC8051_EAS_DC;
205
 
206
        end
207
      `OC8051_MOVC_PC :begin
208
          ram_rd_sel = `OC8051_RRS_DC;
209
          ram_wr_sel = `OC8051_RWS_ACC;
210
          src_sel1 = `OC8051_ASS_IMM;
211
          src_sel2 = `OC8051_ASS_DC;
212
          alu_op = `OC8051_ALU_NOP;
213
          wr = 1'b1;
214
          psw_set = `OC8051_PS_NOT;
215
          cy_sel = `OC8051_CY_0;
216
          pc_wr = `OC8051_PCW_N;
217
          pc_sel = `OC8051_PIS_DC;
218
          imm_sel = `OC8051_IDS_OP1;
219
          src_sel3 = `OC8051_AS3_PC;
220
          comp_sel = `OC8051_CSS_DC;
221
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
222
          wad2 = `OC8051_WAD_N;
223
          rom_addr_sel = `OC8051_RAS_PC;
224
          ext_addr_sel = `OC8051_EAS_DC;
225
        end
226 20 markom
      `OC8051_DIV : begin
227
          ram_rd_sel = `OC8051_RRS_D;
228
          ram_wr_sel = `OC8051_RWS_B;
229
          src_sel1 = `OC8051_ASS_ACC;
230
          src_sel2 = `OC8051_ASS_RAM;
231
          alu_op = `OC8051_ALU_DIV;
232
          wr = 1'b1;
233
          psw_set = `OC8051_PS_OV;
234
          cy_sel = `OC8051_CY_0;
235
          pc_wr = `OC8051_PCW_N;
236
          pc_sel = `OC8051_PIS_DC;
237
          imm_sel = `OC8051_IDS_DC;
238
          src_sel3 = `OC8051_AS3_DC;
239
          comp_sel = `OC8051_CSS_DC;
240
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
241
          wad2 = `OC8051_WAD_Y;
242
          rom_addr_sel = `OC8051_RAS_PC;
243
          ext_addr_sel = `OC8051_EAS_DC;
244
        end
245
      `OC8051_MUL : begin
246
          ram_rd_sel = `OC8051_RRS_D;
247
          ram_wr_sel = `OC8051_RWS_B;
248
          src_sel1 = `OC8051_ASS_ACC;
249
          src_sel2 = `OC8051_ASS_RAM;
250
          alu_op = `OC8051_ALU_MUL;
251
          wr = 1'b1;
252
          psw_set = `OC8051_PS_OV;
253
          cy_sel = `OC8051_CY_0;
254
          pc_wr = `OC8051_PCW_N;
255
          pc_sel = `OC8051_PIS_DC;
256
          imm_sel = `OC8051_IDS_DC;
257
          src_sel3 = `OC8051_AS3_DC;
258
          comp_sel = `OC8051_CSS_DC;
259
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
260
          wad2 = `OC8051_WAD_Y;
261
          rom_addr_sel = `OC8051_RAS_PC;
262
          ext_addr_sel = `OC8051_EAS_DC;
263
        end
264 2 simont
      default begin
265
          ram_rd_sel = `OC8051_RRS_DC;
266
          ram_wr_sel = `OC8051_RWS_DC;
267
          src_sel1 = `OC8051_ASS_DC;
268
          src_sel2 = `OC8051_ASS_DC;
269
          alu_op = `OC8051_ALU_NOP;
270
          wr = 1'b0;
271
          psw_set = `OC8051_PS_NOT;
272
          cy_sel = `OC8051_CY_0;
273
          pc_wr = `OC8051_PCW_N;
274
          pc_sel = `OC8051_PIS_DC;
275
          imm_sel = `OC8051_IDS_DC;
276
          src_sel3 = `OC8051_AS3_DC;
277
          comp_sel = `OC8051_CSS_DC;
278
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
279
          wad2 = `OC8051_WAD_N;
280
          rom_addr_sel = `OC8051_RAS_PC;
281
          ext_addr_sel = `OC8051_EAS_DC;
282
 
283
      end
284
    endcase
285
    end
286
    2'b10:
287
    casex (op)
288
      `OC8051_CJNE_R : begin
289
          ram_rd_sel = `OC8051_RRS_DC;
290
          ram_wr_sel = `OC8051_RWS_DC;
291
          src_sel1 = `OC8051_ASS_DC;
292
          src_sel2 = `OC8051_ASS_DC;
293
          alu_op = `OC8051_ALU_NOP;
294
          wr = 1'b0;
295
          psw_set = `OC8051_PS_NOT;
296
          cy_sel = `OC8051_CY_0;
297
          pc_wr = !eq;
298
          pc_sel = `OC8051_PIS_ALU;
299
          imm_sel = `OC8051_IDS_DC;
300
          src_sel3 = `OC8051_AS3_DC;
301
          comp_sel = `OC8051_CSS_DES;
302
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
303
          wad2 = `OC8051_WAD_N;
304
          rom_addr_sel = `OC8051_RAS_PC;
305
          ext_addr_sel = `OC8051_EAS_DC;
306
 
307
        end
308
      `OC8051_CJNE_I : begin
309
          ram_rd_sel = `OC8051_RRS_DC;
310
          ram_wr_sel = `OC8051_RWS_DC;
311
          src_sel1 = `OC8051_ASS_DC;
312
          src_sel2 = `OC8051_ASS_DC;
313
          alu_op = `OC8051_ALU_NOP;
314
          wr = 1'b0;
315
          psw_set = `OC8051_PS_NOT;
316
          cy_sel = `OC8051_CY_0;
317
          pc_wr = !eq;
318
          pc_sel = `OC8051_PIS_ALU;
319
          imm_sel = `OC8051_IDS_DC;
320
          src_sel3 = `OC8051_AS3_DC;
321
          comp_sel = `OC8051_CSS_DES;
322
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
323
          wad2 = `OC8051_WAD_N;
324
          rom_addr_sel = `OC8051_RAS_PC;
325
          ext_addr_sel = `OC8051_EAS_DC;
326
 
327
        end
328
      `OC8051_CJNE_D : begin
329
          ram_rd_sel = `OC8051_RRS_DC;
330
          ram_wr_sel = `OC8051_RWS_DC;
331
          src_sel1 = `OC8051_ASS_DC;
332
          src_sel2 = `OC8051_ASS_DC;
333
          alu_op = `OC8051_ALU_NOP;
334
          wr = 1'b0;
335
          psw_set = `OC8051_PS_NOT;
336
          cy_sel = `OC8051_CY_0;
337
          pc_wr = !eq;
338
          pc_sel = `OC8051_PIS_ALU;
339
          imm_sel = `OC8051_IDS_DC;
340
          src_sel3 = `OC8051_AS3_DC;
341
          comp_sel = `OC8051_CSS_DES;
342
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
343
          wad2 = `OC8051_WAD_N;
344
          rom_addr_sel = `OC8051_RAS_PC;
345
          ext_addr_sel = `OC8051_EAS_DC;
346
 
347
        end
348
      `OC8051_CJNE_C : begin
349
          ram_rd_sel = `OC8051_RRS_DC;
350
          ram_wr_sel = `OC8051_RWS_DC;
351
          src_sel1 = `OC8051_ASS_DC;
352
          src_sel2 = `OC8051_ASS_DC;
353
          alu_op = `OC8051_ALU_NOP;
354
          wr = 1'b0;
355
          psw_set = `OC8051_PS_NOT;
356
          cy_sel = `OC8051_CY_0;
357
          pc_wr = !eq;
358
          pc_sel = `OC8051_PIS_ALU;
359
          imm_sel = `OC8051_IDS_DC;
360
          src_sel3 = `OC8051_AS3_DC;
361
          comp_sel = `OC8051_CSS_DES;
362
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
363
          wad2 = `OC8051_WAD_N;
364
          rom_addr_sel = `OC8051_RAS_PC;
365
          ext_addr_sel = `OC8051_EAS_DC;
366
 
367
        end
368
      `OC8051_DJNZ_R : begin
369
          ram_rd_sel = `OC8051_RRS_DC;
370
          ram_wr_sel = `OC8051_RWS_DC;
371
          src_sel1 = `OC8051_ASS_DC;
372
          src_sel2 = `OC8051_ASS_DC;
373
          alu_op = `OC8051_ALU_NOP;
374
          wr = 1'b0;
375
          psw_set = `OC8051_PS_NOT;
376
          cy_sel = `OC8051_CY_0;
377
          pc_wr = !eq;
378
          pc_sel = `OC8051_PIS_ALU;
379
          imm_sel = `OC8051_IDS_DC;
380
          src_sel3 = `OC8051_AS3_DC;
381
          comp_sel = `OC8051_CSS_DES;
382
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
383
          wad2 = `OC8051_WAD_N;
384
          rom_addr_sel = `OC8051_RAS_PC;
385
          ext_addr_sel = `OC8051_EAS_DC;
386
 
387
        end
388
      `OC8051_DJNZ_D : begin
389
          ram_rd_sel = `OC8051_RRS_DC;
390
          ram_wr_sel = `OC8051_RWS_DC;
391
          src_sel1 = `OC8051_ASS_DC;
392
          src_sel2 = `OC8051_ASS_DC;
393
          alu_op = `OC8051_ALU_NOP;
394
          wr = 1'b0;
395
          psw_set = `OC8051_PS_NOT;
396
          cy_sel = `OC8051_CY_0;
397
          pc_wr = !eq;
398
          pc_sel = `OC8051_PIS_ALU;
399
          imm_sel = `OC8051_IDS_DC;
400
          src_sel3 = `OC8051_AS3_DC;
401
          comp_sel = `OC8051_CSS_DES;
402
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
403
          wad2 = `OC8051_WAD_N;
404
          rom_addr_sel = `OC8051_RAS_PC;
405
          ext_addr_sel = `OC8051_EAS_DC;
406
 
407
        end
408
      `OC8051_JB : begin
409
          ram_rd_sel = `OC8051_RRS_DC;
410
          ram_wr_sel = `OC8051_RWS_DC;
411
          src_sel1 = `OC8051_ASS_DC;
412
          src_sel2 = `OC8051_ASS_DC;
413
          alu_op = `OC8051_ALU_NOP;
414
          wr = 1'b0;
415
          psw_set = `OC8051_PS_NOT;
416
          cy_sel = `OC8051_CY_0;
417
          pc_wr = eq;
418
          pc_sel = `OC8051_PIS_ALU;
419
          imm_sel = `OC8051_IDS_DC;
420
          src_sel3 = `OC8051_AS3_DC;
421
          comp_sel = `OC8051_CSS_BIT;
422
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
423
          wad2 = `OC8051_WAD_N;
424
          rom_addr_sel = `OC8051_RAS_PC;
425
          ext_addr_sel = `OC8051_EAS_DC;
426
 
427
        end
428
      `OC8051_JBC : begin
429
          ram_rd_sel = `OC8051_RRS_DC;
430
          ram_wr_sel = `OC8051_RWS_D;
431
          src_sel1 = `OC8051_ASS_DC;
432
          src_sel2 = `OC8051_ASS_DC;
433
          alu_op = `OC8051_ALU_NOP;
434
          wr = 1'b1;
435
          psw_set = `OC8051_PS_NOT;
436
          cy_sel = `OC8051_CY_0;
437
          pc_wr = eq;
438
          pc_sel = `OC8051_PIS_ALU;
439
          imm_sel = `OC8051_IDS_DC;
440
          src_sel3 = `OC8051_AS3_DC;
441
          comp_sel = `OC8051_CSS_BIT;
442
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
443
          wad2 = `OC8051_WAD_N;
444
          rom_addr_sel = `OC8051_RAS_PC;
445
          ext_addr_sel = `OC8051_EAS_DC;
446
 
447
        end
448
      `OC8051_JC : begin
449
          ram_rd_sel = `OC8051_RRS_DC;
450
          ram_wr_sel = `OC8051_RWS_DC;
451
          src_sel1 = `OC8051_ASS_DC;
452
          src_sel2 = `OC8051_ASS_DC;
453
          alu_op = `OC8051_ALU_NOP;
454
          wr = 1'b0;
455
          psw_set = `OC8051_PS_NOT;
456
          cy_sel = `OC8051_CY_0;
457
          pc_wr = eq;
458
          pc_sel = `OC8051_PIS_ALU;
459
          imm_sel = `OC8051_IDS_DC;
460
          src_sel3 = `OC8051_AS3_DC;
461
          comp_sel = `OC8051_CSS_CY;
462
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
463
          wad2 = `OC8051_WAD_N;
464
          rom_addr_sel = `OC8051_RAS_PC;
465
          ext_addr_sel = `OC8051_EAS_DC;
466
 
467
        end
468
      `OC8051_JMP : begin
469
          ram_rd_sel = `OC8051_RRS_DC;
470
          ram_wr_sel = `OC8051_RWS_DC;
471
          src_sel1 = `OC8051_ASS_DC;
472
          src_sel2 = `OC8051_ASS_DC;
473
          alu_op = `OC8051_ALU_NOP;
474
          wr = 1'b0;
475
          psw_set = `OC8051_PS_NOT;
476
          cy_sel = `OC8051_CY_0;
477
          pc_wr = `OC8051_PCW_Y;
478
          pc_sel = `OC8051_PIS_ALU;
479
          imm_sel = `OC8051_IDS_DC;
480
          src_sel3 = `OC8051_AS3_DC;
481
          comp_sel = `OC8051_CSS_BIT;
482
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
483
          wad2 = `OC8051_WAD_N;
484
          rom_addr_sel = `OC8051_RAS_PC;
485
          ext_addr_sel = `OC8051_EAS_DC;
486
 
487
        end
488
      `OC8051_JNB : begin
489
          ram_rd_sel = `OC8051_RRS_DC;
490
          ram_wr_sel = `OC8051_RWS_DC;
491
          src_sel1 = `OC8051_ASS_DC;
492
          src_sel2 = `OC8051_ASS_DC;
493
          alu_op = `OC8051_ALU_NOP;
494
          wr = 1'b0;
495
          psw_set = `OC8051_PS_NOT;
496
          cy_sel = `OC8051_CY_0;
497
          pc_wr = !eq;
498
          pc_sel = `OC8051_PIS_ALU;
499
          imm_sel = `OC8051_IDS_DC;
500
          src_sel3 = `OC8051_AS3_DC;
501
          comp_sel = `OC8051_CSS_BIT;
502
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
503
          wad2 = `OC8051_WAD_N;
504
          rom_addr_sel = `OC8051_RAS_PC;
505
          ext_addr_sel = `OC8051_EAS_DC;
506
 
507
        end
508
      `OC8051_JNC : begin
509
          ram_rd_sel = `OC8051_RRS_DC;
510
          ram_wr_sel = `OC8051_RWS_DC;
511
          src_sel1 = `OC8051_ASS_DC;
512
          src_sel2 = `OC8051_ASS_DC;
513
          alu_op = `OC8051_ALU_NOP;
514
          wr = 1'b0;
515
          psw_set = `OC8051_PS_NOT;
516
          cy_sel = `OC8051_CY_0;
517
          pc_wr = !eq;
518
          pc_sel = `OC8051_PIS_ALU;
519
          imm_sel = `OC8051_IDS_DC;
520
          src_sel3 = `OC8051_AS3_DC;
521
          comp_sel = `OC8051_CSS_CY;
522
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
523
          wad2 = `OC8051_WAD_N;
524
          rom_addr_sel = `OC8051_RAS_PC;
525
          ext_addr_sel = `OC8051_EAS_DC;
526
 
527
        end
528
      `OC8051_JNZ : begin
529
          ram_rd_sel = `OC8051_RRS_DC;
530
          ram_wr_sel = `OC8051_RWS_DC;
531
          src_sel1 = `OC8051_ASS_DC;
532
          src_sel2 = `OC8051_ASS_DC;
533
          alu_op = `OC8051_ALU_NOP;
534
          wr = 1'b0;
535
          psw_set = `OC8051_PS_NOT;
536
          cy_sel = `OC8051_CY_0;
537
          pc_wr = !eq;
538
          pc_sel = `OC8051_PIS_ALU;
539
          imm_sel = `OC8051_IDS_DC;
540
          src_sel3 = `OC8051_AS3_DC;
541
          comp_sel = `OC8051_CSS_AZ;
542
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
543
          wad2 = `OC8051_WAD_N;
544
          rom_addr_sel = `OC8051_RAS_PC;
545
          ext_addr_sel = `OC8051_EAS_DC;
546
 
547
        end
548
      `OC8051_JZ : begin
549
          ram_rd_sel = `OC8051_RRS_DC;
550
          ram_wr_sel = `OC8051_RWS_DC;
551
          src_sel1 = `OC8051_ASS_DC;
552
          src_sel2 = `OC8051_ASS_DC;
553
          alu_op = `OC8051_ALU_NOP;
554
          wr = 1'b0;
555
          psw_set = `OC8051_PS_NOT;
556
          cy_sel = `OC8051_CY_0;
557
          pc_wr = eq;
558
          pc_sel = `OC8051_PIS_ALU;
559
          imm_sel = `OC8051_IDS_DC;
560
          src_sel3 = `OC8051_AS3_DC;
561
          comp_sel = `OC8051_CSS_AZ;
562
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
563
          wad2 = `OC8051_WAD_N;
564
          rom_addr_sel = `OC8051_RAS_PC;
565
          ext_addr_sel = `OC8051_EAS_DC;
566
 
567
        end
568
      `OC8051_MOVC_DP :begin
569
          ram_rd_sel = `OC8051_RRS_DC;
570
          ram_wr_sel = `OC8051_RWS_DC;
571
          src_sel1 = `OC8051_ASS_DC;
572
          src_sel2 = `OC8051_ASS_DC;
573
          alu_op = `OC8051_ALU_NOP;
574
          wr = 1'b0;
575
          psw_set = `OC8051_PS_NOT;
576
          cy_sel = `OC8051_CY_0;
577
          pc_wr = `OC8051_PCW_N;
578
          pc_sel = `OC8051_PIS_DC;
579
          imm_sel = `OC8051_IDS_DC;
580
          src_sel3 = `OC8051_AS3_DP;
581
          comp_sel = `OC8051_CSS_DC;
582
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
583
          wad2 = `OC8051_WAD_N;
584
          rom_addr_sel = `OC8051_RAS_DES;
585
          ext_addr_sel = `OC8051_EAS_DC;
586
 
587
        end
588
      `OC8051_MOVC_PC :begin
589
          ram_rd_sel = `OC8051_RRS_DC;
590
          ram_wr_sel = `OC8051_RWS_DC;
591
          src_sel1 = `OC8051_ASS_DC;
592
          src_sel2 = `OC8051_ASS_DC;
593
          alu_op = `OC8051_ALU_NOP;
594
          wr = 1'b0;
595
          psw_set = `OC8051_PS_NOT;
596
          cy_sel = `OC8051_CY_0;
597
          pc_wr = `OC8051_PCW_N;
598
          pc_sel = `OC8051_PIS_DC;
599
          imm_sel = `OC8051_IDS_DC;
600
          src_sel3 = `OC8051_AS3_PC;
601
          comp_sel = `OC8051_CSS_DC;
602
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
603
          wad2 = `OC8051_WAD_N;
604
          rom_addr_sel = `OC8051_RAS_DES;
605
          ext_addr_sel = `OC8051_EAS_DC;
606
        end
607
      `OC8051_SJMP : begin
608
          ram_rd_sel = `OC8051_RRS_DC;
609
          ram_wr_sel = `OC8051_RWS_DC;
610
          src_sel1 = `OC8051_ASS_DC;
611
          src_sel2 = `OC8051_ASS_DC;
612
          alu_op = `OC8051_ALU_NOP;
613
          wr = 1'b0;
614
          psw_set = `OC8051_PS_NOT;
615
          cy_sel = `OC8051_CY_0;
616
          pc_wr = `OC8051_PCW_Y;
617
          pc_sel = `OC8051_PIS_ALU;
618
          imm_sel = `OC8051_IDS_DC;
619
          src_sel3 = `OC8051_AS3_DC;
620
          comp_sel = `OC8051_CSS_DC;
621
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
622
          wad2 = `OC8051_WAD_N;
623
          rom_addr_sel = `OC8051_RAS_PC;
624
          ext_addr_sel = `OC8051_EAS_DC;
625
        end
626 20 markom
      `OC8051_DIV : begin
627
          ram_rd_sel = `OC8051_RRS_D;
628
          ram_wr_sel = `OC8051_RWS_B;
629
          src_sel1 = `OC8051_ASS_ACC;
630
          src_sel2 = `OC8051_ASS_RAM;
631
          alu_op = `OC8051_ALU_DIV;
632 23 simont
          wr = 1'b0;
633 20 markom
          psw_set = `OC8051_PS_OV;
634
          cy_sel = `OC8051_CY_0;
635
          pc_wr = `OC8051_PCW_N;
636
          pc_sel = `OC8051_PIS_DC;
637
          imm_sel = `OC8051_IDS_DC;
638
          src_sel3 = `OC8051_AS3_DC;
639
          comp_sel = `OC8051_CSS_DC;
640
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
641 23 simont
          wad2 = `OC8051_WAD_N;
642 20 markom
          rom_addr_sel = `OC8051_RAS_PC;
643
          ext_addr_sel = `OC8051_EAS_DC;
644
        end
645
      `OC8051_MUL : begin
646
          ram_rd_sel = `OC8051_RRS_D;
647
          ram_wr_sel = `OC8051_RWS_B;
648
          src_sel1 = `OC8051_ASS_ACC;
649
          src_sel2 = `OC8051_ASS_RAM;
650
          alu_op = `OC8051_ALU_MUL;
651 23 simont
          wr = 1'b0;
652 20 markom
          psw_set = `OC8051_PS_OV;
653
          cy_sel = `OC8051_CY_0;
654
          pc_wr = `OC8051_PCW_N;
655
          pc_sel = `OC8051_PIS_DC;
656
          imm_sel = `OC8051_IDS_DC;
657
          src_sel3 = `OC8051_AS3_DC;
658
          comp_sel = `OC8051_CSS_DC;
659
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
660 23 simont
          wad2 = `OC8051_WAD_N;
661 20 markom
          rom_addr_sel = `OC8051_RAS_PC;
662
          ext_addr_sel = `OC8051_EAS_DC;
663
        end
664 2 simont
      default begin
665
          ram_rd_sel = `OC8051_RRS_DC;
666
          ram_wr_sel = `OC8051_RWS_DC;
667
          src_sel1 = `OC8051_ASS_DC;
668
          src_sel2 = `OC8051_ASS_DC;
669
          alu_op = `OC8051_ALU_NOP;
670
          wr = 1'b0;
671
          psw_set = `OC8051_PS_NOT;
672
          cy_sel = `OC8051_CY_0;
673
          pc_wr = `OC8051_PCW_N;
674
          pc_sel = `OC8051_PIS_DC;
675
          imm_sel = `OC8051_IDS_DC;
676
          src_sel3 = `OC8051_AS3_DC;
677
          comp_sel = `OC8051_CSS_DC;
678
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
679
          wad2 = `OC8051_WAD_N;
680
          rom_addr_sel = `OC8051_RAS_PC;
681
          ext_addr_sel = `OC8051_EAS_DC;
682
      end
683
    endcase
684
 
685
    2'b11:
686
    casex (op)
687
      `OC8051_CJNE_R : begin
688
          ram_rd_sel = `OC8051_RRS_DC;
689
          ram_wr_sel = `OC8051_RWS_DC;
690
          src_sel1 = `OC8051_ASS_IMM;
691
          src_sel2 = `OC8051_ASS_IMM;
692
          alu_op = `OC8051_ALU_PCS;
693
          wr = 1'b0;
694
          psw_set = `OC8051_PS_NOT;
695
          cy_sel = `OC8051_CY_0;
696
          pc_wr = `OC8051_PCW_N;
697
          pc_sel = `OC8051_PIS_DC;
698
          imm_sel = `OC8051_IDS_OP3_PCL;
699
          src_sel3 = `OC8051_AS3_PC;
700
          comp_sel = `OC8051_CSS_DC;
701
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
702
          wad2 = `OC8051_WAD_N;
703
          rom_addr_sel = `OC8051_RAS_PC;
704
          ext_addr_sel = `OC8051_EAS_DC;
705
        end
706
      `OC8051_CJNE_I : begin
707
          ram_rd_sel = `OC8051_RRS_DC;
708
          ram_wr_sel = `OC8051_RWS_DC;
709
          src_sel1 = `OC8051_ASS_IMM;
710
          src_sel2 = `OC8051_ASS_IMM;
711
          alu_op = `OC8051_ALU_PCS;
712
          wr = 1'b0;
713
          psw_set = `OC8051_PS_NOT;
714
          cy_sel = `OC8051_CY_0;
715
          pc_wr = `OC8051_PCW_N;
716
          pc_sel = `OC8051_PIS_DC;
717
          imm_sel = `OC8051_IDS_OP3_PCL;
718
          src_sel3 = `OC8051_AS3_PC;
719
          comp_sel = `OC8051_CSS_DC;
720
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
721
          wad2 = `OC8051_WAD_N;
722
          rom_addr_sel = `OC8051_RAS_PC;
723
          ext_addr_sel = `OC8051_EAS_DC;
724
        end
725
      `OC8051_CJNE_D : begin
726
          ram_rd_sel = `OC8051_RRS_DC;
727
          ram_wr_sel = `OC8051_RWS_DC;
728
          src_sel1 = `OC8051_ASS_IMM;
729
          src_sel2 = `OC8051_ASS_IMM;
730
          alu_op = `OC8051_ALU_PCS;
731
          wr = 1'b0;
732
          psw_set = `OC8051_PS_NOT;
733
          cy_sel = `OC8051_CY_0;
734
          pc_wr = `OC8051_PCW_N;
735
          pc_sel = `OC8051_PIS_DC;
736
          imm_sel = `OC8051_IDS_OP3_PCL;
737
          src_sel3 = `OC8051_AS3_PC;
738
          comp_sel = `OC8051_CSS_DC;
739
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
740
          wad2 = `OC8051_WAD_N;
741
          rom_addr_sel = `OC8051_RAS_PC;
742
          ext_addr_sel = `OC8051_EAS_DC;
743
        end
744
      `OC8051_CJNE_C : begin
745
          ram_rd_sel = `OC8051_RRS_DC;
746
          ram_wr_sel = `OC8051_RWS_DC;
747
          src_sel1 = `OC8051_ASS_IMM;
748
          src_sel2 = `OC8051_ASS_IMM;
749
          alu_op = `OC8051_ALU_PCS;
750
          wr = 1'b0;
751
          psw_set = `OC8051_PS_NOT;
752
          cy_sel = `OC8051_CY_0;
753
          pc_wr = `OC8051_PCW_N;
754
          pc_sel = `OC8051_PIS_DC;
755
          imm_sel = `OC8051_IDS_OP3_PCL;
756
          src_sel3 = `OC8051_AS3_PC;
757
          comp_sel = `OC8051_CSS_DC;
758
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
759
          wad2 = `OC8051_WAD_N;
760
          rom_addr_sel = `OC8051_RAS_PC;
761
          ext_addr_sel = `OC8051_EAS_DC;
762
        end
763
      `OC8051_DJNZ_R : begin
764
          ram_rd_sel = `OC8051_RRS_DC;
765
          ram_wr_sel = `OC8051_RWS_DC;
766
          src_sel1 = `OC8051_ASS_IMM;
767
          src_sel2 = `OC8051_ASS_IMM;
768
          alu_op = `OC8051_ALU_PCS;
769
          wr = 1'b0;
770
          psw_set = `OC8051_PS_NOT;
771
          cy_sel = `OC8051_CY_0;
772
          pc_wr = `OC8051_PCW_N;
773
          pc_sel = `OC8051_PIS_DC;
774
          imm_sel = `OC8051_IDS_OP2_PCL;
775
          src_sel3 = `OC8051_AS3_PC;
776
          comp_sel = `OC8051_CSS_DC;
777
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
778
          wad2 = `OC8051_WAD_N;
779
          rom_addr_sel = `OC8051_RAS_PC;
780
          ext_addr_sel = `OC8051_EAS_DC;
781
        end
782
      `OC8051_DJNZ_D : begin
783
          ram_rd_sel = `OC8051_RRS_DC;
784
          ram_wr_sel = `OC8051_RWS_DC;
785
          src_sel1 = `OC8051_ASS_IMM;
786
          src_sel2 = `OC8051_ASS_IMM;
787
          alu_op = `OC8051_ALU_PCS;
788
          wr = 1'b0;
789
          psw_set = `OC8051_PS_NOT;
790
          cy_sel = `OC8051_CY_0;
791
          pc_wr = `OC8051_PCW_N;
792
          pc_sel = `OC8051_PIS_DC;
793
          imm_sel = `OC8051_IDS_OP3_PCL;
794
          src_sel3 = `OC8051_AS3_PC;
795
          comp_sel = `OC8051_CSS_DC;
796
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
797
          wad2 = `OC8051_WAD_N;
798
          rom_addr_sel = `OC8051_RAS_PC;
799
          ext_addr_sel = `OC8051_EAS_DC;
800
        end
801
      `OC8051_RET : begin
802
          ram_rd_sel = `OC8051_RRS_SP;
803
          ram_wr_sel = `OC8051_RWS_DC;
804
          src_sel1 = `OC8051_ASS_RAM;
805
          src_sel2 = `OC8051_ASS_DC;
806
          alu_op = `OC8051_ALU_NOP;
807
          wr = 1'b0;
808
          psw_set = `OC8051_PS_NOT;
809
          cy_sel = `OC8051_CY_0;
810
          pc_wr = `OC8051_PCW_Y;
811
          pc_sel = `OC8051_PIS_SP;
812
          imm_sel = `OC8051_IDS_DC;
813
          src_sel3 = `OC8051_AS3_DC;
814
          comp_sel = `OC8051_CSS_DC;
815
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
816
          wad2 = `OC8051_WAD_N;
817
          rom_addr_sel = `OC8051_RAS_PC;
818
          ext_addr_sel = `OC8051_EAS_DC;
819
        end
820
      `OC8051_RETI : begin
821
          ram_rd_sel = `OC8051_RRS_SP;
822
          ram_wr_sel = `OC8051_RWS_DC;
823
          src_sel1 = `OC8051_ASS_RAM;
824
          src_sel2 = `OC8051_ASS_DC;
825
          alu_op = `OC8051_ALU_NOP;
826
          wr = 1'b0;
827
          psw_set = `OC8051_PS_NOT;
828
          cy_sel = `OC8051_CY_0;
829
          pc_wr = `OC8051_PCW_Y;
830
          pc_sel = `OC8051_PIS_SP;
831
          imm_sel = `OC8051_IDS_DC;
832
          src_sel3 = `OC8051_AS3_DC;
833
          comp_sel = `OC8051_CSS_DC;
834
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
835
          wad2 = `OC8051_WAD_N;
836
          rom_addr_sel = `OC8051_RAS_PC;
837
          ext_addr_sel = `OC8051_EAS_DC;
838
        end
839 20 markom
      `OC8051_DIV : begin
840
          ram_rd_sel = `OC8051_RRS_D;
841
          ram_wr_sel = `OC8051_RWS_B;
842
          src_sel1 = `OC8051_ASS_ACC;
843
          src_sel2 = `OC8051_ASS_RAM;
844
          alu_op = `OC8051_ALU_DIV;
845 23 simont
          wr = 1'b0;
846 20 markom
          psw_set = `OC8051_PS_OV;
847
          cy_sel = `OC8051_CY_0;
848
          pc_wr = `OC8051_PCW_N;
849
          pc_sel = `OC8051_PIS_DC;
850
          imm_sel = `OC8051_IDS_DC;
851
          src_sel3 = `OC8051_AS3_DC;
852
          comp_sel = `OC8051_CSS_DC;
853
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
854 23 simont
          wad2 = `OC8051_WAD_N;
855 20 markom
          rom_addr_sel = `OC8051_RAS_PC;
856
          ext_addr_sel = `OC8051_EAS_DC;
857
        end
858
      `OC8051_MUL : begin
859
          ram_rd_sel = `OC8051_RRS_D;
860
          ram_wr_sel = `OC8051_RWS_B;
861
          src_sel1 = `OC8051_ASS_ACC;
862
          src_sel2 = `OC8051_ASS_RAM;
863
          alu_op = `OC8051_ALU_MUL;
864 23 simont
          wr = 1'b0;
865 20 markom
          psw_set = `OC8051_PS_OV;
866
          cy_sel = `OC8051_CY_0;
867
          pc_wr = `OC8051_PCW_N;
868
          pc_sel = `OC8051_PIS_DC;
869
          imm_sel = `OC8051_IDS_DC;
870
          src_sel3 = `OC8051_AS3_DC;
871
          comp_sel = `OC8051_CSS_DC;
872
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
873 23 simont
          wad2 = `OC8051_WAD_N;
874 20 markom
          rom_addr_sel = `OC8051_RAS_PC;
875
          ext_addr_sel = `OC8051_EAS_DC;
876
        end
877 23 simont
     default begin
878 2 simont
          ram_rd_sel = `OC8051_RRS_DC;
879
          ram_wr_sel = `OC8051_RWS_DC;
880
          src_sel1 = `OC8051_ASS_DC;
881
          src_sel2 = `OC8051_ASS_DC;
882
          alu_op = `OC8051_ALU_NOP;
883
          wr = 1'b0;
884
          psw_set = `OC8051_PS_NOT;
885
          cy_sel = `OC8051_CY_0;
886
          pc_wr = `OC8051_PCW_N;
887
          pc_sel = `OC8051_PIS_DC;
888
          imm_sel = `OC8051_IDS_DC;
889
          src_sel3 = `OC8051_AS3_DC;
890
          comp_sel = `OC8051_CSS_DC;
891
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
892
          wad2 = `OC8051_WAD_N;
893
          rom_addr_sel = `OC8051_RAS_PC;
894
          ext_addr_sel = `OC8051_EAS_DC;
895
      end
896
    endcase
897
    default: begin
898
    casex (op_in)
899
      `OC8051_ACALL :begin
900
          ram_rd_sel = `OC8051_RRS_DC;
901
          ram_wr_sel = `OC8051_RWS_SP;
902
          src_sel1 = `OC8051_ASS_IMM;
903
          src_sel2 = `OC8051_ASS_DC;
904
          alu_op = `OC8051_ALU_NOP;
905
          imm_sel = `OC8051_IDS_PCL;
906
          wr = 1'b1;
907
          psw_set = `OC8051_PS_NOT;
908
          cy_sel = `OC8051_CY_0;
909
          pc_wr = `OC8051_PCW_Y;
910
          pc_sel = `OC8051_PIS_I11;
911
          src_sel3 = `OC8051_AS3_DC;
912
          comp_sel = `OC8051_CSS_DC;
913
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
914
          wad2 = `OC8051_WAD_N;
915
          rom_addr_sel = `OC8051_RAS_PC;
916
          ext_addr_sel = `OC8051_EAS_DC;
917
        end
918
      `OC8051_AJMP : begin
919
          ram_rd_sel = `OC8051_RRS_DC;
920
          ram_wr_sel = `OC8051_RWS_DC;
921
          src_sel1 = `OC8051_ASS_DC;
922
          src_sel2 = `OC8051_ASS_DC;
923
          alu_op = `OC8051_ALU_NOP;
924
          imm_sel = `OC8051_IDS_DC;
925
          wr = 1'b0;
926
          psw_set = `OC8051_PS_NOT;
927
          cy_sel = `OC8051_CY_0;
928
          pc_wr = `OC8051_PCW_Y;
929
          pc_sel = `OC8051_PIS_I11;
930
          src_sel3 = `OC8051_AS3_DC;
931
          comp_sel = `OC8051_CSS_DC;
932
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
933
          wad2 = `OC8051_WAD_N;
934
          rom_addr_sel = `OC8051_RAS_PC;
935
          ext_addr_sel = `OC8051_EAS_DC;
936
        end
937
      `OC8051_ADD_R : begin
938
          ram_rd_sel = `OC8051_RRS_RN;
939
          ram_wr_sel = `OC8051_RWS_ACC;
940
          src_sel1 = `OC8051_ASS_ACC;
941
          src_sel2 = `OC8051_ASS_RAM;
942
          alu_op = `OC8051_ALU_ADD;
943
          wr = 1'b1;
944
          psw_set = `OC8051_PS_AC;
945
          cy_sel = `OC8051_CY_0;
946
          pc_wr = `OC8051_PCW_N;
947
          pc_sel = `OC8051_PIS_DC;
948
          imm_sel = `OC8051_IDS_DC;
949
          src_sel3 = `OC8051_AS3_DC;
950
          comp_sel = `OC8051_CSS_DC;
951
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
952
          wad2 = `OC8051_WAD_N;
953
          rom_addr_sel = `OC8051_RAS_PC;
954
          ext_addr_sel = `OC8051_EAS_DC;
955
        end
956
      `OC8051_ADDC_R : begin
957
          ram_rd_sel = `OC8051_RRS_RN;
958
          ram_wr_sel = `OC8051_RWS_ACC;
959
          src_sel1 = `OC8051_ASS_ACC;
960
          src_sel2 = `OC8051_ASS_RAM;
961
          alu_op = `OC8051_ALU_ADD;
962
          wr = 1'b1;
963
          psw_set = `OC8051_PS_AC;
964
          cy_sel = `OC8051_CY_PSW;
965
          pc_wr = `OC8051_PCW_N;
966
          pc_sel = `OC8051_PIS_DC;
967
          imm_sel = `OC8051_IDS_DC;
968
          src_sel3 = `OC8051_AS3_DC;
969
          comp_sel = `OC8051_CSS_DC;
970
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
971
          wad2 = `OC8051_WAD_N;
972
          rom_addr_sel = `OC8051_RAS_PC;
973
          ext_addr_sel = `OC8051_EAS_DC;
974
        end
975
      `OC8051_ANL_R : begin
976
          ram_rd_sel = `OC8051_RRS_RN;
977
          ram_wr_sel = `OC8051_RWS_ACC;
978
          src_sel1 = `OC8051_ASS_ACC;
979
          src_sel2 = `OC8051_ASS_RAM;
980
          alu_op = `OC8051_ALU_AND;
981
          wr = 1'b1;
982
          psw_set = `OC8051_PS_NOT;
983
          cy_sel = `OC8051_CY_0;
984
          pc_wr = `OC8051_PCW_N;
985
          pc_sel = `OC8051_PIS_DC;
986
          imm_sel = `OC8051_IDS_DC;
987
          src_sel3 = `OC8051_AS3_DC;
988
          comp_sel = `OC8051_CSS_DC;
989
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
990
          wad2 = `OC8051_WAD_N;
991
          rom_addr_sel = `OC8051_RAS_PC;
992
          ext_addr_sel = `OC8051_EAS_DC;
993
        end
994
      `OC8051_CJNE_R : begin
995
          ram_rd_sel = `OC8051_RRS_RN;
996
          ram_wr_sel = `OC8051_RWS_DC;
997
          src_sel1 = `OC8051_ASS_RAM;
998
          src_sel2 = `OC8051_ASS_IMM;
999
          alu_op = `OC8051_ALU_SUB;
1000
          wr = 1'b0;
1001
          psw_set = `OC8051_PS_CY;
1002
          cy_sel = `OC8051_CY_0;
1003
          pc_wr = `OC8051_PCW_N;
1004
          pc_sel = `OC8051_PIS_DC;
1005
          imm_sel = `OC8051_IDS_OP2;
1006
          src_sel3 = `OC8051_AS3_DC;
1007
          comp_sel = `OC8051_CSS_DC;
1008
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1009
          wad2 = `OC8051_WAD_N;
1010
          rom_addr_sel = `OC8051_RAS_PC;
1011
          ext_addr_sel = `OC8051_EAS_DC;
1012
        end
1013
      `OC8051_DEC_R : begin
1014
          ram_rd_sel = `OC8051_RRS_RN;
1015
          ram_wr_sel = `OC8051_RWS_RN;
1016
          src_sel1 = `OC8051_ASS_RAM;
1017
          src_sel2 = `OC8051_ASS_ZERO;
1018
          alu_op = `OC8051_ALU_SUB;
1019
          wr = 1'b1;
1020
          psw_set = `OC8051_PS_NOT;
1021
          cy_sel = `OC8051_CY_1;
1022
          pc_wr = `OC8051_PCW_N;
1023
          pc_sel = `OC8051_PIS_DC;
1024
          imm_sel = `OC8051_IDS_DC;
1025
          src_sel3 = `OC8051_AS3_DC;
1026
          comp_sel = `OC8051_CSS_DC;
1027
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1028
          wad2 = `OC8051_WAD_N;
1029
          rom_addr_sel = `OC8051_RAS_PC;
1030
          ext_addr_sel = `OC8051_EAS_DC;
1031
        end
1032
      `OC8051_DJNZ_R : begin
1033
          ram_rd_sel = `OC8051_RRS_RN;
1034
          ram_wr_sel = `OC8051_RWS_RN;
1035
          src_sel1 = `OC8051_ASS_RAM;
1036
          src_sel2 = `OC8051_ASS_ZERO;
1037
          alu_op = `OC8051_ALU_SUB;
1038
          wr = 1'b1;
1039
          psw_set = `OC8051_PS_NOT;
1040
          cy_sel = `OC8051_CY_1;
1041
          pc_wr = `OC8051_PCW_N;
1042
          pc_sel = `OC8051_PIS_DC;
1043
          imm_sel = `OC8051_IDS_DC;
1044
          src_sel3 = `OC8051_AS3_DC;
1045
          comp_sel = `OC8051_CSS_DC;
1046
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1047
          wad2 = `OC8051_WAD_N;
1048
          rom_addr_sel = `OC8051_RAS_PC;
1049
          ext_addr_sel = `OC8051_EAS_DC;
1050
        end
1051
      `OC8051_INC_R : begin
1052
          ram_rd_sel = `OC8051_RRS_RN;
1053
          ram_wr_sel = `OC8051_RWS_RN;
1054
          src_sel1 = `OC8051_ASS_RAM;
1055
          src_sel2 = `OC8051_ASS_ZERO;
1056
          alu_op = `OC8051_ALU_ADD;
1057
          wr = 1'b1;
1058
          psw_set = `OC8051_PS_NOT;
1059
          cy_sel = `OC8051_CY_1;
1060
          pc_wr = `OC8051_PCW_N;
1061
          pc_sel = `OC8051_PIS_DC;
1062
          imm_sel = `OC8051_IDS_DC;
1063
          src_sel3 = `OC8051_AS3_DC;
1064
          comp_sel = `OC8051_CSS_DC;
1065
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1066
          wad2 = `OC8051_WAD_N;
1067
          rom_addr_sel = `OC8051_RAS_PC;
1068
          ext_addr_sel = `OC8051_EAS_DC;
1069
        end
1070
      `OC8051_MOV_R : begin
1071
          ram_rd_sel = `OC8051_RRS_RN;
1072
          ram_wr_sel = `OC8051_RWS_ACC;
1073
          src_sel1 = `OC8051_ASS_RAM;
1074
          src_sel2 = `OC8051_ASS_DC;
1075
          alu_op = `OC8051_ALU_NOP;
1076
          wr = 1'b1;
1077
          psw_set = `OC8051_PS_NOT;
1078
          cy_sel = `OC8051_CY_0;
1079
          pc_wr = `OC8051_PCW_N;
1080
          pc_sel = `OC8051_PIS_DC;
1081
          imm_sel = `OC8051_IDS_DC;
1082
          src_sel3 = `OC8051_AS3_DC;
1083
          comp_sel = `OC8051_CSS_DC;
1084
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1085
          wad2 = `OC8051_WAD_N;
1086
          rom_addr_sel = `OC8051_RAS_PC;
1087
          ext_addr_sel = `OC8051_EAS_DC;
1088
        end
1089
 
1090
      `OC8051_MOV_AR : begin
1091
          ram_rd_sel = `OC8051_RRS_DC;
1092
          ram_wr_sel = `OC8051_RWS_RN;
1093
          src_sel1 = `OC8051_ASS_ACC;
1094
          src_sel2 = `OC8051_ASS_DC;
1095
          alu_op = `OC8051_ALU_NOP;
1096
          wr = 1'b1;
1097
          psw_set = `OC8051_PS_NOT;
1098
          cy_sel = `OC8051_CY_0;
1099
          pc_wr = `OC8051_PCW_N;
1100
          pc_sel = `OC8051_PIS_DC;
1101
          imm_sel = `OC8051_IDS_DC;
1102
          src_sel3 = `OC8051_AS3_DC;
1103
          comp_sel = `OC8051_CSS_DC;
1104
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1105
          wad2 = `OC8051_WAD_N;
1106
          rom_addr_sel = `OC8051_RAS_PC;
1107
          ext_addr_sel = `OC8051_EAS_DC;
1108
        end
1109
      `OC8051_MOV_DR : begin
1110
          ram_rd_sel = `OC8051_RRS_D;
1111
          ram_wr_sel = `OC8051_RWS_RN;
1112
          src_sel1 = `OC8051_ASS_RAM;
1113
          src_sel2 = `OC8051_ASS_DC;
1114
          alu_op = `OC8051_ALU_NOP;
1115
          wr = 1'b1;
1116
          psw_set = `OC8051_PS_NOT;
1117
          cy_sel = `OC8051_CY_0;
1118
          pc_wr = `OC8051_PCW_N;
1119
          pc_sel = `OC8051_PIS_DC;
1120
          imm_sel = `OC8051_IDS_DC;
1121
          src_sel3 = `OC8051_AS3_DC;
1122
          comp_sel = `OC8051_CSS_DC;
1123
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1124
          wad2 = `OC8051_WAD_N;
1125
          rom_addr_sel = `OC8051_RAS_PC;
1126
          ext_addr_sel = `OC8051_EAS_DC;
1127
        end
1128
      `OC8051_MOV_CR : begin
1129
          ram_rd_sel = `OC8051_RRS_DC;
1130
          ram_wr_sel = `OC8051_RWS_RN;
1131
          src_sel1 = `OC8051_ASS_IMM;
1132
          src_sel2 = `OC8051_ASS_DC;
1133
          alu_op = `OC8051_ALU_NOP;
1134
          wr = 1'b1;
1135
          psw_set = `OC8051_PS_NOT;
1136
          cy_sel = `OC8051_CY_0;
1137
          pc_wr = `OC8051_PCW_N;
1138
          pc_sel = `OC8051_PIS_DC;
1139
          imm_sel = `OC8051_IDS_OP2;
1140
          src_sel3 = `OC8051_AS3_DC;
1141
          comp_sel = `OC8051_CSS_DC;
1142
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1143
          wad2 = `OC8051_WAD_N;
1144
          rom_addr_sel = `OC8051_RAS_PC;
1145
          ext_addr_sel = `OC8051_EAS_DC;
1146
        end
1147
      `OC8051_MOV_RD : begin
1148
          ram_rd_sel = `OC8051_RRS_RN;
1149
          ram_wr_sel = `OC8051_RWS_D;
1150
          src_sel1 = `OC8051_ASS_RAM;
1151
          src_sel2 = `OC8051_ASS_DC;
1152
          alu_op = `OC8051_ALU_NOP;
1153
          wr = 1'b1;
1154
          psw_set = `OC8051_PS_NOT;
1155
          cy_sel = `OC8051_CY_0;
1156
          pc_wr = `OC8051_PCW_N;
1157
          pc_sel = `OC8051_PIS_DC;
1158
          imm_sel = `OC8051_IDS_DC;
1159
          src_sel3 = `OC8051_AS3_DC;
1160
          comp_sel = `OC8051_CSS_DC;
1161
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1162
          wad2 = `OC8051_WAD_N;
1163
          rom_addr_sel = `OC8051_RAS_PC;
1164
          ext_addr_sel = `OC8051_EAS_DC;
1165
        end
1166
      `OC8051_ORL_R : begin
1167
          ram_rd_sel = `OC8051_RRS_RN;
1168
          ram_wr_sel = `OC8051_RWS_ACC;
1169
          src_sel1 = `OC8051_ASS_RAM;
1170
          src_sel2 = `OC8051_ASS_ACC;
1171
          alu_op = `OC8051_ALU_OR;
1172
          wr = 1'b1;
1173
          psw_set = `OC8051_PS_NOT;
1174
          cy_sel = `OC8051_CY_0;
1175
          pc_wr = `OC8051_PCW_N;
1176
          pc_sel = `OC8051_PIS_DC;
1177
          imm_sel = `OC8051_IDS_DC;
1178
          src_sel3 = `OC8051_AS3_DC;
1179
          comp_sel = `OC8051_CSS_DC;
1180
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1181
          wad2 = `OC8051_WAD_N;
1182
          rom_addr_sel = `OC8051_RAS_PC;
1183
          ext_addr_sel = `OC8051_EAS_DC;
1184
        end
1185
      `OC8051_SUBB_R : begin
1186
          ram_rd_sel = `OC8051_RRS_RN;
1187
          ram_wr_sel = `OC8051_RWS_ACC;
1188
          src_sel1 = `OC8051_ASS_ACC;
1189
          src_sel2 = `OC8051_ASS_RAM;
1190
          alu_op = `OC8051_ALU_SUB;
1191
          wr = 1'b1;
1192
          psw_set = `OC8051_PS_AC;
1193
          cy_sel = `OC8051_CY_PSW;
1194
          pc_wr = `OC8051_PCW_N;
1195
          pc_sel = `OC8051_PIS_DC;
1196
          imm_sel = `OC8051_IDS_DC;
1197
          src_sel3 = `OC8051_AS3_DC;
1198
          comp_sel = `OC8051_CSS_DC;
1199
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1200
          wad2 = `OC8051_WAD_N;
1201
          rom_addr_sel = `OC8051_RAS_PC;
1202
          ext_addr_sel = `OC8051_EAS_DC;
1203
        end
1204
      `OC8051_XCH_R : begin
1205
          ram_rd_sel = `OC8051_RRS_RN;
1206
          ram_wr_sel = `OC8051_RWS_RN;
1207
          src_sel1 = `OC8051_ASS_RAM;
1208
          src_sel2 = `OC8051_ASS_ACC;
1209
          alu_op = `OC8051_ALU_XCH;
1210
          wr = 1'b1;
1211
          psw_set = `OC8051_PS_NOT;
1212
          cy_sel = `OC8051_CY_1;
1213
          pc_wr = `OC8051_PCW_N;
1214
          pc_sel = `OC8051_PIS_DC;
1215
          imm_sel = `OC8051_IDS_DC;
1216
          src_sel3 = `OC8051_AS3_DC;
1217
          comp_sel = `OC8051_CSS_DC;
1218
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1219
          wad2 = `OC8051_WAD_Y;
1220
          rom_addr_sel = `OC8051_RAS_PC;
1221
          ext_addr_sel = `OC8051_EAS_DC;
1222
        end
1223
      `OC8051_XRL_R : begin
1224
          ram_rd_sel = `OC8051_RRS_RN;
1225
          ram_wr_sel = `OC8051_RWS_ACC;
1226
          src_sel1 = `OC8051_ASS_RAM;
1227
          src_sel2 = `OC8051_ASS_ACC;
1228
          alu_op = `OC8051_ALU_XOR;
1229
          wr = 1'b1;
1230
          psw_set = `OC8051_PS_NOT;
1231
          cy_sel = `OC8051_CY_0;
1232
          pc_wr = `OC8051_PCW_N;
1233
          pc_sel = `OC8051_PIS_DC;
1234
          imm_sel = `OC8051_IDS_DC;
1235
          src_sel3 = `OC8051_AS3_DC;
1236
          comp_sel = `OC8051_CSS_DC;
1237
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1238
          wad2 = `OC8051_WAD_N;
1239
          rom_addr_sel = `OC8051_RAS_PC;
1240
          ext_addr_sel = `OC8051_EAS_DC;
1241
        end
1242
 
1243
//op_code [7:1]
1244
      `OC8051_ADD_I : begin
1245
          ram_rd_sel = `OC8051_RRS_I;
1246
          ram_wr_sel = `OC8051_RWS_ACC;
1247
          src_sel1 = `OC8051_ASS_ACC;
1248
          src_sel2 = `OC8051_ASS_RAM;
1249
          alu_op = `OC8051_ALU_ADD;
1250
          wr = 1'b1;
1251
          psw_set = `OC8051_PS_AC;
1252
          cy_sel = `OC8051_CY_0;
1253
          pc_wr = `OC8051_PCW_N;
1254
          pc_sel = `OC8051_PIS_DC;
1255
          imm_sel = `OC8051_IDS_DC;
1256
          src_sel3 = `OC8051_AS3_DC;
1257
          comp_sel = `OC8051_CSS_DC;
1258
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1259
          wad2 = `OC8051_WAD_N;
1260
          rom_addr_sel = `OC8051_RAS_PC;
1261
          ext_addr_sel = `OC8051_EAS_DC;
1262
        end
1263
      `OC8051_ADDC_I : begin
1264
          ram_rd_sel = `OC8051_RRS_I;
1265
          ram_wr_sel = `OC8051_RWS_ACC;
1266
          src_sel1 = `OC8051_ASS_ACC;
1267
          src_sel2 = `OC8051_ASS_RAM;
1268
          alu_op = `OC8051_ALU_ADD;
1269
          wr = 1'b1;
1270
          psw_set = `OC8051_PS_AC;
1271
          cy_sel = `OC8051_CY_PSW;
1272
          pc_wr = `OC8051_PCW_N;
1273
          pc_sel = `OC8051_PIS_DC;
1274
          imm_sel = `OC8051_IDS_DC;
1275
          src_sel3 = `OC8051_AS3_DC;
1276
          comp_sel = `OC8051_CSS_DC;
1277
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1278
          wad2 = `OC8051_WAD_N;
1279
          rom_addr_sel = `OC8051_RAS_PC;
1280
          ext_addr_sel = `OC8051_EAS_DC;
1281
        end
1282
      `OC8051_ANL_I : begin
1283
          ram_rd_sel = `OC8051_RRS_I;
1284
          ram_wr_sel = `OC8051_RWS_ACC;
1285
          src_sel1 = `OC8051_ASS_ACC;
1286
          src_sel2 = `OC8051_ASS_RAM;
1287
          alu_op = `OC8051_ALU_AND;
1288
          wr = 1'b1;
1289
          psw_set = `OC8051_PS_NOT;
1290
          cy_sel = `OC8051_CY_0;
1291
          pc_wr = `OC8051_PCW_N;
1292
          pc_sel = `OC8051_PIS_DC;
1293
          imm_sel = `OC8051_IDS_DC;
1294
          src_sel3 = `OC8051_AS3_DC;
1295
          comp_sel = `OC8051_CSS_DC;
1296
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1297
          wad2 = `OC8051_WAD_N;
1298
          rom_addr_sel = `OC8051_RAS_PC;
1299
          ext_addr_sel = `OC8051_EAS_DC;
1300
        end
1301
      `OC8051_CJNE_I : begin
1302
          ram_rd_sel = `OC8051_RRS_I;
1303
          ram_wr_sel = `OC8051_RWS_DC;
1304
          src_sel1 = `OC8051_ASS_RAM;
1305
          src_sel2 = `OC8051_ASS_IMM;
1306
          alu_op = `OC8051_ALU_SUB;
1307
          wr = 1'b0;
1308
          psw_set = `OC8051_PS_CY;
1309
          cy_sel = `OC8051_CY_0;
1310
          pc_wr = `OC8051_PCW_N;
1311
          pc_sel = `OC8051_PIS_DC;
1312
          imm_sel = `OC8051_IDS_OP2;
1313
          src_sel3 = `OC8051_AS3_DC;
1314
          comp_sel = `OC8051_CSS_DC;
1315
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1316
          wad2 = `OC8051_WAD_N;
1317
          rom_addr_sel = `OC8051_RAS_PC;
1318
          ext_addr_sel = `OC8051_EAS_DC;
1319
        end
1320
      `OC8051_DEC_I : begin
1321
          ram_rd_sel = `OC8051_RRS_I;
1322
          ram_wr_sel = `OC8051_RWS_I;
1323
          src_sel1 = `OC8051_ASS_RAM;
1324
          src_sel2 = `OC8051_ASS_ZERO;
1325
          alu_op = `OC8051_ALU_SUB;
1326
          wr = 1'b1;
1327
          psw_set = `OC8051_PS_NOT;
1328
          cy_sel = `OC8051_CY_1;
1329
          pc_wr = `OC8051_PCW_N;
1330
          pc_sel = `OC8051_PIS_DC;
1331
          imm_sel = `OC8051_IDS_DC;
1332
          src_sel3 = `OC8051_AS3_DC;
1333
          comp_sel = `OC8051_CSS_DC;
1334
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1335
          wad2 = `OC8051_WAD_N;
1336
          rom_addr_sel = `OC8051_RAS_PC;
1337
          ext_addr_sel = `OC8051_EAS_DC;
1338
        end
1339
      `OC8051_INC_I : begin
1340
          ram_rd_sel = `OC8051_RRS_I;
1341
          ram_wr_sel = `OC8051_RWS_I;
1342
          src_sel1 = `OC8051_ASS_RAM;
1343
          src_sel2 = `OC8051_ASS_ZERO;
1344
          alu_op = `OC8051_ALU_ADD;
1345
          wr = 1'b1;
1346
          psw_set = `OC8051_PS_NOT;
1347
          cy_sel = `OC8051_CY_1;
1348
          pc_wr = `OC8051_PCW_N;
1349
          pc_sel = `OC8051_PIS_DC;
1350
          imm_sel = `OC8051_IDS_DC;
1351
          src_sel3 = `OC8051_AS3_DC;
1352
          comp_sel = `OC8051_CSS_DC;
1353
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1354
          wad2 = `OC8051_WAD_N;
1355
          rom_addr_sel = `OC8051_RAS_PC;
1356
          ext_addr_sel = `OC8051_EAS_DC;
1357
        end
1358
      `OC8051_MOV_I : begin
1359
          ram_rd_sel = `OC8051_RRS_I;
1360
          ram_wr_sel = `OC8051_RWS_ACC;
1361
          src_sel1 = `OC8051_ASS_RAM;
1362
          src_sel2 = `OC8051_ASS_DC;
1363
          alu_op = `OC8051_ALU_NOP;
1364
          wr = 1'b1;
1365
          psw_set = `OC8051_PS_NOT;
1366
          cy_sel = `OC8051_CY_0;
1367
          pc_wr = `OC8051_PCW_N;
1368
          pc_sel = `OC8051_PIS_DC;
1369
          imm_sel = `OC8051_IDS_DC;
1370
          src_sel3 = `OC8051_AS3_DC;
1371
          comp_sel = `OC8051_CSS_DC;
1372
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1373
          wad2 = `OC8051_WAD_N;
1374
          rom_addr_sel = `OC8051_RAS_PC;
1375
          ext_addr_sel = `OC8051_EAS_DC;
1376
        end
1377
      `OC8051_MOV_ID : begin
1378
          ram_rd_sel = `OC8051_RRS_I;
1379
          ram_wr_sel = `OC8051_RWS_D;
1380
          src_sel1 = `OC8051_ASS_RAM;
1381
          src_sel2 = `OC8051_ASS_DC;
1382
          alu_op = `OC8051_ALU_NOP;
1383
          wr = 1'b1;
1384
          psw_set = `OC8051_PS_NOT;
1385
          cy_sel = `OC8051_CY_0;
1386
          pc_wr = `OC8051_PCW_N;
1387
          pc_sel = `OC8051_PIS_DC;
1388
          imm_sel = `OC8051_IDS_DC;
1389
          src_sel3 = `OC8051_AS3_DC;
1390
          comp_sel = `OC8051_CSS_DC;
1391
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1392
          wad2 = `OC8051_WAD_N;
1393
          rom_addr_sel = `OC8051_RAS_PC;
1394
          ext_addr_sel = `OC8051_EAS_DC;
1395
        end
1396
      `OC8051_MOV_AI : begin
1397
          ram_rd_sel = `OC8051_RRS_DC;
1398
          ram_wr_sel = `OC8051_RWS_I;
1399
          src_sel1 = `OC8051_ASS_ACC;
1400
          src_sel2 = `OC8051_ASS_DC;
1401
          alu_op = `OC8051_ALU_NOP;
1402
          wr = 1'b1;
1403
          psw_set = `OC8051_PS_NOT;
1404
          cy_sel = `OC8051_CY_0;
1405
          pc_wr = `OC8051_PCW_N;
1406
          pc_sel = `OC8051_PIS_DC;
1407
          imm_sel = `OC8051_IDS_DC;
1408
          src_sel3 = `OC8051_AS3_DC;
1409
          comp_sel = `OC8051_CSS_DC;
1410
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1411
          wad2 = `OC8051_WAD_N;
1412
          rom_addr_sel = `OC8051_RAS_PC;
1413
          ext_addr_sel = `OC8051_EAS_DC;
1414
        end
1415
      `OC8051_MOV_DI : begin
1416
          ram_rd_sel = `OC8051_RRS_D;
1417
          ram_wr_sel = `OC8051_RWS_I;
1418
          src_sel1 = `OC8051_ASS_RAM;
1419
          src_sel2 = `OC8051_ASS_DC;
1420
          alu_op = `OC8051_ALU_NOP;
1421
          wr = 1'b1;
1422
          psw_set = `OC8051_PS_NOT;
1423
          cy_sel = `OC8051_CY_0;
1424
          pc_wr = `OC8051_PCW_N;
1425
          pc_sel = `OC8051_PIS_DC;
1426
          imm_sel = `OC8051_IDS_DC;
1427
          src_sel3 = `OC8051_AS3_DC;
1428
          comp_sel = `OC8051_CSS_DC;
1429
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1430
          wad2 = `OC8051_WAD_N;
1431
          rom_addr_sel = `OC8051_RAS_PC;
1432
          ext_addr_sel = `OC8051_EAS_DC;
1433
        end
1434
      `OC8051_MOV_CI : begin
1435
          ram_rd_sel = `OC8051_RRS_DC;
1436
          ram_wr_sel = `OC8051_RWS_I;
1437
          src_sel1 = `OC8051_ASS_IMM;
1438
          src_sel2 = `OC8051_ASS_DC;
1439
          alu_op = `OC8051_ALU_NOP;
1440
          wr = 1'b1;
1441
          psw_set = `OC8051_PS_NOT;
1442
          cy_sel = `OC8051_CY_0;
1443
          pc_wr = `OC8051_PCW_N;
1444
          pc_sel = `OC8051_PIS_DC;
1445
          imm_sel = `OC8051_IDS_OP2;
1446
          src_sel3 = `OC8051_AS3_DC;
1447
          comp_sel = `OC8051_CSS_DC;
1448
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1449
          wad2 = `OC8051_WAD_N;
1450
          rom_addr_sel = `OC8051_RAS_PC;
1451
          ext_addr_sel = `OC8051_EAS_DC;
1452
        end
1453
      `OC8051_MOVX_IA : begin
1454
          ram_rd_sel = `OC8051_RRS_DC;
1455
          ram_wr_sel = `OC8051_RWS_ACC;
1456
          src_sel1 = `OC8051_ASS_XRAM;
1457
          src_sel2 = `OC8051_ASS_DC;
1458
          alu_op = `OC8051_ALU_NOP;
1459
          wr = 1'b1;
1460
          psw_set = `OC8051_PS_NOT;
1461
          cy_sel = `OC8051_CY_0;
1462
          pc_wr = `OC8051_PCW_N;
1463
          pc_sel = `OC8051_PIS_DC;
1464
          imm_sel = `OC8051_IDS_OP2;
1465
          src_sel3 = `OC8051_AS3_DC;
1466
          comp_sel = `OC8051_CSS_DC;
1467
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1468
          wad2 = `OC8051_WAD_N;
1469
          rom_addr_sel = `OC8051_RAS_PC;
1470
          ext_addr_sel = `OC8051_EAS_RI;
1471
        end
1472
      `OC8051_MOVX_AI :begin
1473
          ram_rd_sel = `OC8051_RRS_DC;
1474
          ram_wr_sel = `OC8051_RWS_ACC;
1475
          src_sel1 = `OC8051_ASS_DC;
1476
          src_sel2 = `OC8051_ASS_DC;
1477
          alu_op = `OC8051_ALU_NOP;
1478
          wr = 1'b0;
1479
          psw_set = `OC8051_PS_NOT;
1480
          cy_sel = `OC8051_CY_0;
1481
          pc_wr = `OC8051_PCW_N;
1482
          pc_sel = `OC8051_PIS_DC;
1483
          imm_sel = `OC8051_IDS_OP2;
1484
          src_sel3 = `OC8051_AS3_DC;
1485
          comp_sel = `OC8051_CSS_DC;
1486
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1487
          wad2 = `OC8051_WAD_N;
1488
          rom_addr_sel = `OC8051_RAS_PC;
1489
          ext_addr_sel = `OC8051_EAS_RI;
1490
        end
1491
      `OC8051_ORL_I : begin
1492
          ram_rd_sel = `OC8051_RRS_I;
1493
          ram_wr_sel = `OC8051_RWS_ACC;
1494
          src_sel1 = `OC8051_ASS_RAM;
1495
          src_sel2 = `OC8051_ASS_ACC;
1496
          alu_op = `OC8051_ALU_OR;
1497
          wr = 1'b1;
1498
          psw_set = `OC8051_PS_NOT;
1499
          cy_sel = `OC8051_CY_0;
1500
          pc_wr = `OC8051_PCW_N;
1501
          pc_sel = `OC8051_PIS_DC;
1502
          imm_sel = `OC8051_IDS_DC;
1503
          src_sel3 = `OC8051_AS3_DC;
1504
          comp_sel = `OC8051_CSS_DC;
1505
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1506
          wad2 = `OC8051_WAD_N;
1507
          rom_addr_sel = `OC8051_RAS_PC;
1508
          ext_addr_sel = `OC8051_EAS_DC;
1509
        end
1510
      `OC8051_SUBB_I : begin
1511
          ram_rd_sel = `OC8051_RRS_I;
1512
          ram_wr_sel = `OC8051_RWS_ACC;
1513
          src_sel1 = `OC8051_ASS_ACC;
1514
          src_sel2 = `OC8051_ASS_RAM;
1515
          alu_op = `OC8051_ALU_SUB;
1516
          wr = 1'b1;
1517
          psw_set = `OC8051_PS_AC;
1518
          cy_sel = `OC8051_CY_PSW;
1519
          pc_wr = `OC8051_PCW_N;
1520
          pc_sel = `OC8051_PIS_DC;
1521
          imm_sel = `OC8051_IDS_DC;
1522
          src_sel3 = `OC8051_AS3_DC;
1523
          comp_sel = `OC8051_CSS_DC;
1524
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1525
          wad2 = `OC8051_WAD_N;
1526
          rom_addr_sel = `OC8051_RAS_PC;
1527
          ext_addr_sel = `OC8051_EAS_DC;
1528
        end
1529
      `OC8051_XCH_I : begin
1530
          ram_rd_sel = `OC8051_RRS_I;
1531
          ram_wr_sel = `OC8051_RWS_I;
1532
          src_sel1 = `OC8051_ASS_RAM;
1533
          src_sel2 = `OC8051_ASS_ACC;
1534
          alu_op = `OC8051_ALU_XCH;
1535
          wr = 1'b1;
1536
          psw_set = `OC8051_PS_NOT;
1537
          cy_sel = `OC8051_CY_1;
1538
          pc_wr = `OC8051_PCW_N;
1539
          pc_sel = `OC8051_PIS_DC;
1540
          imm_sel = `OC8051_IDS_DC;
1541
          src_sel3 = `OC8051_AS3_DC;
1542
          comp_sel = `OC8051_CSS_DC;
1543
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1544
          wad2 = `OC8051_WAD_Y;
1545
          rom_addr_sel = `OC8051_RAS_PC;
1546
          ext_addr_sel = `OC8051_EAS_DC;
1547
        end
1548
      `OC8051_XCHD :begin
1549
          ram_rd_sel = `OC8051_RRS_I;
1550
          ram_wr_sel = `OC8051_RWS_I;
1551
          src_sel1 = `OC8051_ASS_RAM;
1552
          src_sel2 = `OC8051_ASS_ACC;
1553
          alu_op = `OC8051_ALU_XCH;
1554
          wr = 1'b1;
1555
          psw_set = `OC8051_PS_NOT;
1556
          cy_sel = `OC8051_CY_0;
1557
          pc_wr = `OC8051_PCW_N;
1558
          pc_sel = `OC8051_PIS_DC;
1559
          imm_sel = `OC8051_IDS_DC;
1560
          src_sel3 = `OC8051_AS3_DC;
1561
          comp_sel = `OC8051_CSS_DC;
1562
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1563
          wad2 = `OC8051_WAD_Y;
1564
          rom_addr_sel = `OC8051_RAS_PC;
1565
          ext_addr_sel = `OC8051_EAS_DC;
1566
        end
1567
      `OC8051_XRL_I : begin
1568
          ram_rd_sel = `OC8051_RRS_I;
1569
          ram_wr_sel = `OC8051_RWS_ACC;
1570
          src_sel1 = `OC8051_ASS_RAM;
1571
          src_sel2 = `OC8051_ASS_ACC;
1572
          alu_op = `OC8051_ALU_XOR;
1573
          wr = 1'b1;
1574
          psw_set = `OC8051_PS_NOT;
1575
          cy_sel = `OC8051_CY_0;
1576
          pc_wr = `OC8051_PCW_N;
1577
          pc_sel = `OC8051_PIS_DC;
1578
          imm_sel = `OC8051_IDS_DC;
1579
          src_sel3 = `OC8051_AS3_DC;
1580
          comp_sel = `OC8051_CSS_DC;
1581
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1582
          wad2 = `OC8051_WAD_N;
1583
          rom_addr_sel = `OC8051_RAS_PC;
1584
          ext_addr_sel = `OC8051_EAS_DC;
1585
        end
1586
 
1587
//op_code [7:0]
1588
      `OC8051_ADD_D : begin
1589
          ram_rd_sel = `OC8051_RRS_D;
1590
          ram_wr_sel = `OC8051_RWS_ACC;
1591
          src_sel1 = `OC8051_ASS_ACC;
1592
          src_sel2 = `OC8051_ASS_RAM;
1593
          alu_op = `OC8051_ALU_ADD;
1594
          wr = 1'b1;
1595
          psw_set = `OC8051_PS_AC;
1596
          cy_sel = `OC8051_CY_0;
1597
          pc_wr = `OC8051_PCW_N;
1598
          pc_sel = `OC8051_PIS_DC;
1599
          imm_sel = `OC8051_IDS_DC;
1600
          src_sel3 = `OC8051_AS3_DC;
1601
          comp_sel = `OC8051_CSS_DC;
1602
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1603
          wad2 = `OC8051_WAD_N;
1604
          rom_addr_sel = `OC8051_RAS_PC;
1605
          ext_addr_sel = `OC8051_EAS_DC;
1606
        end
1607
      `OC8051_ADD_C : begin
1608
          ram_rd_sel = `OC8051_RRS_DC;
1609
          ram_wr_sel = `OC8051_RWS_ACC;
1610
          src_sel1 = `OC8051_ASS_IMM;
1611
          src_sel2 = `OC8051_ASS_ACC;
1612
          alu_op = `OC8051_ALU_ADD;
1613
          wr = 1'b1;
1614
          psw_set = `OC8051_PS_AC;
1615
          cy_sel = `OC8051_CY_0;
1616
          pc_wr = `OC8051_PCW_N;
1617
          pc_sel = `OC8051_PIS_DC;
1618
          imm_sel = `OC8051_IDS_OP2;
1619
          src_sel3 = `OC8051_AS3_DC;
1620
          comp_sel = `OC8051_CSS_DC;
1621
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1622
          wad2 = `OC8051_WAD_N;
1623
          rom_addr_sel = `OC8051_RAS_PC;
1624
          ext_addr_sel = `OC8051_EAS_DC;
1625
        end
1626
      `OC8051_ADDC_D : begin
1627
          ram_rd_sel = `OC8051_RRS_D;
1628
          ram_wr_sel = `OC8051_RWS_ACC;
1629
          src_sel1 = `OC8051_ASS_ACC;
1630
          src_sel2 = `OC8051_ASS_RAM;
1631
          alu_op = `OC8051_ALU_ADD;
1632
          wr = 1'b1;
1633
          psw_set = `OC8051_PS_AC;
1634
          cy_sel = `OC8051_CY_PSW;
1635
          pc_wr = `OC8051_PCW_N;
1636
          pc_sel = `OC8051_PIS_DC;
1637
          imm_sel = `OC8051_IDS_DC;
1638
          src_sel3 = `OC8051_AS3_DC;
1639
          comp_sel = `OC8051_CSS_DC;
1640
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1641
          wad2 = `OC8051_WAD_N;
1642
          rom_addr_sel = `OC8051_RAS_PC;
1643
          ext_addr_sel = `OC8051_EAS_DC;
1644
        end
1645
      `OC8051_ADDC_C : begin
1646
          ram_rd_sel = `OC8051_RRS_DC;
1647
          ram_wr_sel = `OC8051_RWS_ACC;
1648
          src_sel1 = `OC8051_ASS_IMM;
1649
          src_sel2 = `OC8051_ASS_ACC;
1650
          alu_op = `OC8051_ALU_ADD;
1651
          wr = 1'b1;
1652
          psw_set = `OC8051_PS_AC;
1653
          cy_sel = `OC8051_CY_PSW;
1654
          pc_wr = `OC8051_PCW_N;
1655
          pc_sel = `OC8051_PIS_DC;
1656
          imm_sel = `OC8051_IDS_OP2;
1657
          src_sel3 = `OC8051_AS3_DC;
1658
          comp_sel = `OC8051_CSS_DC;
1659
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1660
          wad2 = `OC8051_WAD_N;
1661
          rom_addr_sel = `OC8051_RAS_PC;
1662
          ext_addr_sel = `OC8051_EAS_DC;
1663
        end
1664
      `OC8051_ANL_D : begin
1665
          ram_rd_sel = `OC8051_RRS_D;
1666
          ram_wr_sel = `OC8051_RWS_ACC;
1667
          src_sel1 = `OC8051_ASS_ACC;
1668
          src_sel2 = `OC8051_ASS_RAM;
1669
          alu_op = `OC8051_ALU_AND;
1670
          wr = 1'b1;
1671
          psw_set = `OC8051_PS_NOT;
1672
          cy_sel = `OC8051_CY_0;
1673
          pc_wr = `OC8051_PCW_N;
1674
          pc_sel = `OC8051_PIS_DC;
1675
          imm_sel = `OC8051_IDS_DC;
1676
          src_sel3 = `OC8051_AS3_DC;
1677
          comp_sel = `OC8051_CSS_DC;
1678
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1679
          wad2 = `OC8051_WAD_N;
1680
          rom_addr_sel = `OC8051_RAS_PC;
1681
          ext_addr_sel = `OC8051_EAS_DC;
1682
        end
1683
      `OC8051_ANL_C : begin
1684
          ram_rd_sel = `OC8051_RRS_DC;
1685
          ram_wr_sel = `OC8051_RWS_ACC;
1686
          src_sel1 = `OC8051_ASS_IMM;
1687
          src_sel2 = `OC8051_ASS_ACC;
1688
          alu_op = `OC8051_ALU_AND;
1689
          wr = 1'b1;
1690
          psw_set = `OC8051_PS_NOT;
1691
          cy_sel = `OC8051_CY_0;
1692
          pc_wr = `OC8051_PCW_N;
1693
          pc_sel = `OC8051_PIS_DC;
1694
          imm_sel = `OC8051_IDS_OP2;
1695
          src_sel3 = `OC8051_AS3_DC;
1696
          comp_sel = `OC8051_CSS_DC;
1697
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1698
          wad2 = `OC8051_WAD_N;
1699
          rom_addr_sel = `OC8051_RAS_PC;
1700
          ext_addr_sel = `OC8051_EAS_DC;
1701
        end
1702
      `OC8051_ANL_DD : begin
1703
          ram_rd_sel = `OC8051_RRS_D;
1704
          ram_wr_sel = `OC8051_RWS_D;
1705
          src_sel1 = `OC8051_ASS_ACC;
1706
          src_sel2 = `OC8051_ASS_RAM;
1707
          alu_op = `OC8051_ALU_AND;
1708
          wr = 1'b1;
1709
          psw_set = `OC8051_PS_NOT;
1710
          cy_sel = `OC8051_CY_0;
1711
          pc_wr = `OC8051_PCW_N;
1712
          pc_sel = `OC8051_PIS_DC;
1713
          imm_sel = `OC8051_IDS_DC;
1714
          src_sel3 = `OC8051_AS3_DC;
1715
          comp_sel = `OC8051_CSS_DC;
1716
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1717
          wad2 = `OC8051_WAD_N;
1718
          rom_addr_sel = `OC8051_RAS_PC;
1719
          ext_addr_sel = `OC8051_EAS_DC;
1720
        end
1721
      `OC8051_ANL_DC : begin
1722
          ram_rd_sel = `OC8051_RRS_D;
1723
          ram_wr_sel = `OC8051_RWS_D;
1724
          src_sel1 = `OC8051_ASS_IMM;
1725
          src_sel2 = `OC8051_ASS_RAM;
1726
          alu_op = `OC8051_ALU_AND;
1727
          wr = 1'b1;
1728
          psw_set = `OC8051_PS_NOT;
1729
          cy_sel = `OC8051_CY_0;
1730
          pc_wr = `OC8051_PCW_N;
1731
          pc_sel = `OC8051_PIS_DC;
1732
          imm_sel = `OC8051_IDS_OP3;
1733
          src_sel3 = `OC8051_AS3_DC;
1734
          comp_sel = `OC8051_CSS_DC;
1735
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1736
          wad2 = `OC8051_WAD_N;
1737
          rom_addr_sel = `OC8051_RAS_PC;
1738
          ext_addr_sel = `OC8051_EAS_DC;
1739
        end
1740
      `OC8051_ANL_B : begin
1741
          ram_rd_sel = `OC8051_RRS_D;
1742
          ram_wr_sel = `OC8051_RWS_DC;
1743
          src_sel1 = `OC8051_ASS_DC;
1744
          src_sel2 = `OC8051_ASS_DC;
1745
          alu_op = `OC8051_ALU_AND;
1746
          wr = 1'b0;
1747
          psw_set = `OC8051_PS_CY;
1748
          cy_sel = `OC8051_CY_PSW;
1749
          pc_wr = `OC8051_PCW_N;
1750
          pc_sel = `OC8051_PIS_DC;
1751
          imm_sel = `OC8051_IDS_DC;
1752
          src_sel3 = `OC8051_AS3_DC;
1753
          comp_sel = `OC8051_CSS_DC;
1754
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1755
          wad2 = `OC8051_WAD_N;
1756
          rom_addr_sel = `OC8051_RAS_PC;
1757
          ext_addr_sel = `OC8051_EAS_DC;
1758
        end
1759
      `OC8051_ANL_NB : begin
1760
          ram_rd_sel = `OC8051_RRS_D;
1761
          ram_wr_sel = `OC8051_RWS_DC;
1762
          src_sel1 = `OC8051_ASS_DC;
1763
          src_sel2 = `OC8051_ASS_DC;
1764
          alu_op = `OC8051_ALU_RR;
1765
          wr = 1'b0;
1766
          psw_set = `OC8051_PS_CY;
1767
          cy_sel = `OC8051_CY_PSW;
1768
          pc_wr = `OC8051_PCW_N;
1769
          pc_sel = `OC8051_PIS_DC;
1770
          imm_sel = `OC8051_IDS_DC;
1771
          src_sel3 = `OC8051_AS3_DC;
1772
          comp_sel = `OC8051_CSS_DC;
1773
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1774
          wad2 = `OC8051_WAD_N;
1775
          rom_addr_sel = `OC8051_RAS_PC;
1776
          ext_addr_sel = `OC8051_EAS_DC;
1777
        end
1778
      `OC8051_CJNE_D : begin
1779
          ram_rd_sel = `OC8051_RRS_D;
1780
          ram_wr_sel = `OC8051_RWS_DC;
1781
          src_sel1 = `OC8051_ASS_ACC;
1782
          src_sel2 = `OC8051_ASS_RAM;
1783
          alu_op = `OC8051_ALU_SUB;
1784
          wr = 1'b0;
1785
          psw_set = `OC8051_PS_CY;
1786
          cy_sel = `OC8051_CY_0;
1787
          pc_wr = `OC8051_PCW_N;
1788
          pc_sel = `OC8051_PIS_DC;
1789
          imm_sel = `OC8051_IDS_DC;
1790
          src_sel3 = `OC8051_AS3_DC;
1791
          comp_sel = `OC8051_CSS_DC;
1792
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1793
          wad2 = `OC8051_WAD_N;
1794
          rom_addr_sel = `OC8051_RAS_PC;
1795
          ext_addr_sel = `OC8051_EAS_DC;
1796
        end
1797
      `OC8051_CJNE_C : begin
1798
          ram_rd_sel = `OC8051_RRS_DC;
1799
          ram_wr_sel = `OC8051_RWS_DC;
1800
          src_sel1 = `OC8051_ASS_ACC;
1801
          src_sel2 = `OC8051_ASS_IMM;
1802
          alu_op = `OC8051_ALU_SUB;
1803
          wr = 1'b0;
1804
          psw_set = `OC8051_PS_CY;
1805
          cy_sel = `OC8051_CY_0;
1806
          pc_wr = `OC8051_PCW_N;
1807
          pc_sel = `OC8051_PIS_DC;
1808
          imm_sel = `OC8051_IDS_OP2;
1809
          src_sel3 = `OC8051_AS3_DC;
1810
          comp_sel = `OC8051_CSS_DC;
1811
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1812
          wad2 = `OC8051_WAD_N;
1813
          rom_addr_sel = `OC8051_RAS_PC;
1814
          ext_addr_sel = `OC8051_EAS_DC;
1815
        end
1816
      `OC8051_CLR_A : begin
1817
          ram_rd_sel = `OC8051_RRS_DC;
1818
          ram_wr_sel = `OC8051_RWS_ACC;
1819
          src_sel1 = `OC8051_ASS_ACC;
1820
          src_sel2 = `OC8051_ASS_ACC;
1821
          alu_op = `OC8051_ALU_SUB;
1822
          wr = 1'b1;
1823
          psw_set = `OC8051_PS_NOT;
1824
          cy_sel = `OC8051_CY_0;
1825
          pc_wr = `OC8051_PCW_N;
1826
          pc_sel = `OC8051_PIS_DC;
1827
          imm_sel = `OC8051_IDS_DC;
1828
          src_sel3 = `OC8051_AS3_PC;
1829
          comp_sel = `OC8051_CSS_DC;
1830
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1831
          wad2 = `OC8051_WAD_N;
1832
          rom_addr_sel = `OC8051_RAS_PC;
1833
          ext_addr_sel = `OC8051_EAS_DC;
1834
        end
1835
      `OC8051_CLR_C : begin
1836
          ram_rd_sel = `OC8051_RRS_DC;
1837
          ram_wr_sel = `OC8051_RWS_DC;
1838
          src_sel1 = `OC8051_ASS_DC;
1839
          src_sel2 = `OC8051_ASS_DC;
1840
          alu_op = `OC8051_ALU_NOP;
1841
          wr = 1'b0;
1842
          psw_set = `OC8051_PS_CY;
1843
          cy_sel = `OC8051_CY_0;
1844
          pc_wr = `OC8051_PCW_N;
1845
          pc_sel = `OC8051_PIS_DC;
1846
          imm_sel = `OC8051_IDS_DC;
1847
          src_sel3 = `OC8051_AS3_PC;
1848
          comp_sel = `OC8051_CSS_DC;
1849
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1850
          wad2 = `OC8051_WAD_N;
1851
          rom_addr_sel = `OC8051_RAS_PC;
1852
          ext_addr_sel = `OC8051_EAS_DC;
1853
        end
1854
      `OC8051_CLR_B : begin
1855
          ram_rd_sel = `OC8051_RRS_D;
1856
          ram_wr_sel = `OC8051_RWS_D;
1857
          src_sel1 = `OC8051_ASS_DC;
1858
          src_sel2 = `OC8051_ASS_DC;
1859
          alu_op = `OC8051_ALU_NOP;
1860
          wr = 1'b1;
1861
          psw_set = `OC8051_PS_NOT;
1862
          cy_sel = `OC8051_CY_0;
1863
          pc_wr = `OC8051_PCW_N;
1864
          pc_sel = `OC8051_PIS_DC;
1865
          imm_sel = `OC8051_IDS_DC;
1866
          src_sel3 = `OC8051_AS3_PC;
1867
          comp_sel = `OC8051_CSS_DC;
1868
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1869
          wad2 = `OC8051_WAD_N;
1870
          rom_addr_sel = `OC8051_RAS_PC;
1871
          ext_addr_sel = `OC8051_EAS_DC;
1872
        end
1873
      `OC8051_CPL_A : begin
1874
          ram_rd_sel = `OC8051_RRS_DC;
1875
          ram_wr_sel = `OC8051_RWS_ACC;
1876
          src_sel1 = `OC8051_ASS_ACC;
1877
          src_sel2 = `OC8051_ASS_DC;
1878
          alu_op = `OC8051_ALU_NOT;
1879
          wr = 1'b1;
1880
          psw_set = `OC8051_PS_NOT;
1881
          cy_sel = `OC8051_CY_0;
1882
          pc_wr = `OC8051_PCW_N;
1883
          pc_sel = `OC8051_PIS_DC;
1884
          imm_sel = `OC8051_IDS_OP3;   ///****
1885
          src_sel3 = `OC8051_AS3_DC;
1886
          comp_sel = `OC8051_CSS_DC;
1887
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1888
          wad2 = `OC8051_WAD_N;
1889
          rom_addr_sel = `OC8051_RAS_PC;
1890
          ext_addr_sel = `OC8051_EAS_DC;
1891
        end
1892
      `OC8051_CPL_C : begin
1893
          ram_rd_sel = `OC8051_RRS_DC;
1894
          ram_wr_sel = `OC8051_RWS_DC;
1895
          src_sel1 = `OC8051_ASS_DC;
1896
          src_sel2 = `OC8051_ASS_DC;
1897
          alu_op = `OC8051_ALU_NOT;
1898
          wr = 1'b0;
1899
          psw_set = `OC8051_PS_CY;
1900
          cy_sel = `OC8051_CY_PSW;
1901
          pc_wr = `OC8051_PCW_N;
1902
          pc_sel = `OC8051_PIS_DC;
1903
          imm_sel = `OC8051_IDS_OP3;  ///*****
1904
          src_sel3 = `OC8051_AS3_DC;
1905
          comp_sel = `OC8051_CSS_DC;
1906
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1907
          wad2 = `OC8051_WAD_N;
1908
          rom_addr_sel = `OC8051_RAS_PC;
1909
          ext_addr_sel = `OC8051_EAS_DC;
1910
        end
1911
      `OC8051_CPL_B : begin
1912
          ram_rd_sel = `OC8051_RRS_D;
1913
          ram_wr_sel = `OC8051_RWS_D;
1914
          src_sel1 = `OC8051_ASS_DC;
1915
          src_sel2 = `OC8051_ASS_DC;
1916
          alu_op = `OC8051_ALU_NOT;
1917
          wr = 1'b1;
1918
          psw_set = `OC8051_PS_NOT;
1919
          cy_sel = `OC8051_CY_RAM;
1920
          pc_wr = `OC8051_PCW_N;
1921
          pc_sel = `OC8051_PIS_DC;
1922
          imm_sel = `OC8051_IDS_OP3;  ///***
1923
          src_sel3 = `OC8051_AS3_DC;
1924
          comp_sel = `OC8051_CSS_DC;
1925
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
1926
          wad2 = `OC8051_WAD_N;
1927
          rom_addr_sel = `OC8051_RAS_PC;
1928
          ext_addr_sel = `OC8051_EAS_DC;
1929
        end
1930
      `OC8051_DA : begin
1931
          ram_rd_sel = `OC8051_RRS_DC;
1932
          ram_wr_sel = `OC8051_RWS_ACC;
1933
          src_sel1 = `OC8051_ASS_ACC;
1934
          src_sel2 = `OC8051_ASS_DC;
1935
          alu_op = `OC8051_ALU_DA;
1936
          wr = 1'b1;
1937
          psw_set = `OC8051_PS_CY;
1938
          cy_sel = `OC8051_CY_PSW;
1939
          pc_wr = `OC8051_PCW_N;
1940
          pc_sel = `OC8051_PIS_DC;
1941
          imm_sel = `OC8051_IDS_DC;
1942
          src_sel3 = `OC8051_AS3_DC;
1943
          comp_sel = `OC8051_CSS_DC;
1944
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
1945
          wad2 = `OC8051_WAD_N;
1946
          rom_addr_sel = `OC8051_RAS_PC;
1947
          ext_addr_sel = `OC8051_EAS_DC;
1948
        end
1949
      `OC8051_DEC_A : begin
1950
          ram_rd_sel = `OC8051_RRS_DC;
1951
          ram_wr_sel = `OC8051_RWS_ACC;
1952
          src_sel1 = `OC8051_ASS_ACC;
1953
          src_sel2 = `OC8051_ASS_ZERO;
1954
          alu_op = `OC8051_ALU_SUB;
1955
          wr = 1'b1;
1956
          psw_set = `OC8051_PS_NOT;
1957
          cy_sel = `OC8051_CY_1;
1958
          pc_wr = `OC8051_PCW_N;
1959
          pc_sel = `OC8051_PIS_DC;
1960
          imm_sel = `OC8051_IDS_DC;
1961
          src_sel3 = `OC8051_AS3_DC;
1962
          comp_sel = `OC8051_CSS_DC;
1963
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1964
          wad2 = `OC8051_WAD_N;
1965
          rom_addr_sel = `OC8051_RAS_PC;
1966
          ext_addr_sel = `OC8051_EAS_DC;
1967
        end
1968
      `OC8051_DEC_D : begin
1969
          ram_rd_sel = `OC8051_RRS_D;
1970
          ram_wr_sel = `OC8051_RWS_D;
1971
          src_sel1 = `OC8051_ASS_RAM;
1972
          src_sel2 = `OC8051_ASS_ZERO;
1973
          alu_op = `OC8051_ALU_SUB;
1974
          wr = 1'b1;
1975
          psw_set = `OC8051_PS_NOT;
1976
          cy_sel = `OC8051_CY_1;
1977
          pc_wr = `OC8051_PCW_N;
1978
          pc_sel = `OC8051_PIS_DC;
1979
          imm_sel = `OC8051_IDS_DC;
1980
          src_sel3 = `OC8051_AS3_DC;
1981
          comp_sel = `OC8051_CSS_DC;
1982
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
1983
          wad2 = `OC8051_WAD_N;
1984
          rom_addr_sel = `OC8051_RAS_PC;
1985
          ext_addr_sel = `OC8051_EAS_DC;
1986
        end
1987
      `OC8051_DIV : begin
1988
          ram_rd_sel = `OC8051_RRS_D;
1989
          ram_wr_sel = `OC8051_RWS_B;
1990
          src_sel1 = `OC8051_ASS_ACC;
1991
          src_sel2 = `OC8051_ASS_RAM;
1992
          alu_op = `OC8051_ALU_DIV;
1993 20 markom
          wr = 1'b0;
1994 2 simont
          psw_set = `OC8051_PS_OV;
1995
          cy_sel = `OC8051_CY_0;
1996
          pc_wr = `OC8051_PCW_N;
1997
          pc_sel = `OC8051_PIS_DC;
1998
          imm_sel = `OC8051_IDS_DC;
1999
          src_sel3 = `OC8051_AS3_DC;
2000
          comp_sel = `OC8051_CSS_DC;
2001
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2002 20 markom
          wad2 = `OC8051_WAD_N;
2003 2 simont
          rom_addr_sel = `OC8051_RAS_PC;
2004
          ext_addr_sel = `OC8051_EAS_DC;
2005
        end
2006
      `OC8051_DJNZ_D : begin
2007
          ram_rd_sel = `OC8051_RRS_D;
2008
          ram_wr_sel = `OC8051_RWS_D;
2009
          src_sel1 = `OC8051_ASS_RAM;
2010
          src_sel2 = `OC8051_ASS_ZERO;
2011
          alu_op = `OC8051_ALU_SUB;
2012
          wr = 1'b1;
2013
          psw_set = `OC8051_PS_NOT;
2014
          cy_sel = `OC8051_CY_1;
2015
          pc_wr = `OC8051_PCW_N;
2016
          pc_sel = `OC8051_PIS_DC;
2017
          imm_sel = `OC8051_IDS_DC;
2018
          src_sel3 = `OC8051_AS3_DC;
2019
          comp_sel = `OC8051_CSS_DC;
2020
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2021
          wad2 = `OC8051_WAD_N;
2022
          rom_addr_sel = `OC8051_RAS_PC;
2023
          ext_addr_sel = `OC8051_EAS_DC;
2024
        end
2025
      `OC8051_INC_A : begin
2026
          ram_rd_sel = `OC8051_RRS_DC;
2027
          ram_wr_sel = `OC8051_RWS_ACC;
2028
          src_sel1 = `OC8051_ASS_ACC;
2029
          src_sel2 = `OC8051_ASS_ZERO;
2030
          alu_op = `OC8051_ALU_ADD;
2031
          wr = 1'b1;
2032
          psw_set = `OC8051_PS_NOT;
2033
          cy_sel = `OC8051_CY_1;
2034
          pc_wr = `OC8051_PCW_N;
2035
          pc_sel = `OC8051_PIS_DC;
2036
          imm_sel = `OC8051_IDS_DC;
2037
          src_sel3 = `OC8051_AS3_DC;
2038
          comp_sel = `OC8051_CSS_DC;
2039
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2040
          wad2 = `OC8051_WAD_N;
2041
          rom_addr_sel = `OC8051_RAS_PC;
2042
          ext_addr_sel = `OC8051_EAS_DC;
2043
        end
2044
      `OC8051_INC_D : begin
2045
          ram_rd_sel = `OC8051_RRS_D;
2046
          ram_wr_sel = `OC8051_RWS_D;
2047
          src_sel1 = `OC8051_ASS_RAM;
2048
          src_sel2 = `OC8051_ASS_ZERO;
2049
          alu_op = `OC8051_ALU_ADD;
2050
          wr = 1'b1;
2051
          psw_set = `OC8051_PS_NOT;
2052
          cy_sel = `OC8051_CY_1;
2053
          pc_wr = `OC8051_PCW_N;
2054
          pc_sel = `OC8051_PIS_DC;
2055
          imm_sel = `OC8051_IDS_DC;
2056
          src_sel3 = `OC8051_AS3_DC;
2057
          comp_sel = `OC8051_CSS_DC;
2058
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2059
          wad2 = `OC8051_WAD_N;
2060
          rom_addr_sel = `OC8051_RAS_PC;
2061
          ext_addr_sel = `OC8051_EAS_DC;
2062
        end
2063
      `OC8051_INC_DP : begin
2064
          ram_rd_sel = `OC8051_RRS_D;
2065
          ram_wr_sel = `OC8051_RWS_DPTR;
2066
          src_sel1 = `OC8051_ASS_RAM;
2067
          src_sel2 = `OC8051_ASS_ZERO;
2068
          alu_op = `OC8051_ALU_ADD;
2069
          wr = 1'b1;
2070
          psw_set = `OC8051_PS_NOT;
2071
          cy_sel = `OC8051_CY_1;
2072
          pc_wr = `OC8051_PCW_N;
2073
          pc_sel = `OC8051_PIS_DC;
2074
          imm_sel = `OC8051_IDS_DC;
2075
          src_sel3 = `OC8051_AS3_DP;
2076
          comp_sel = `OC8051_CSS_DC;
2077
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2078
          wad2 = `OC8051_WAD_N;
2079
          rom_addr_sel = `OC8051_RAS_PC;
2080
          ext_addr_sel = `OC8051_EAS_DC;
2081
        end
2082
      `OC8051_JB : begin
2083
          ram_rd_sel = `OC8051_RRS_D;
2084
          ram_wr_sel = `OC8051_RWS_DC;
2085
          src_sel1 = `OC8051_ASS_IMM;
2086
          src_sel2 = `OC8051_ASS_IMM;
2087
          alu_op = `OC8051_ALU_PCS;
2088
          wr = 1'b0;
2089
          psw_set = `OC8051_PS_NOT;
2090
          cy_sel = `OC8051_CY_0;
2091
          pc_wr = `OC8051_PCW_N;
2092
          pc_sel = `OC8051_PIS_DC;
2093
          imm_sel = `OC8051_IDS_OP3_PCL;
2094
          src_sel3 = `OC8051_AS3_PC;
2095
          comp_sel = `OC8051_CSS_BIT;
2096
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2097
          wad2 = `OC8051_WAD_N;
2098
          rom_addr_sel = `OC8051_RAS_PC;
2099
          ext_addr_sel = `OC8051_EAS_DC;
2100
        end
2101
      `OC8051_JBC :begin
2102
          ram_rd_sel = `OC8051_RRS_D;
2103
          ram_wr_sel = `OC8051_RWS_DC;
2104
          src_sel1 = `OC8051_ASS_IMM;
2105
          src_sel2 = `OC8051_ASS_IMM;
2106
          alu_op = `OC8051_ALU_PCS;
2107
          wr = 1'b0;
2108
          psw_set = `OC8051_PS_NOT;
2109
          cy_sel = `OC8051_CY_0;
2110
          pc_wr = `OC8051_PCW_N;
2111
          pc_sel = `OC8051_PIS_DC;
2112
          imm_sel = `OC8051_IDS_OP3_PCL;
2113
          src_sel3 = `OC8051_AS3_PC;
2114
          comp_sel = `OC8051_CSS_BIT;
2115
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2116
          wad2 = `OC8051_WAD_N;
2117
          rom_addr_sel = `OC8051_RAS_PC;
2118
          ext_addr_sel = `OC8051_EAS_DC;
2119
        end
2120
      `OC8051_JC : begin
2121
          ram_rd_sel = `OC8051_RRS_DC;
2122
          ram_wr_sel = `OC8051_RWS_DC;
2123
          src_sel1 = `OC8051_ASS_IMM;
2124
          src_sel2 = `OC8051_ASS_IMM;
2125
          alu_op = `OC8051_ALU_PCS;
2126
          wr = 1'b0;
2127
          psw_set = `OC8051_PS_NOT;
2128
          cy_sel = `OC8051_CY_0;
2129
          pc_wr = `OC8051_PCW_N;
2130
          pc_sel = `OC8051_PIS_DC;
2131
          imm_sel = `OC8051_IDS_OP2_PCL;
2132
          src_sel3 = `OC8051_AS3_PC;
2133
          comp_sel = `OC8051_CSS_CY;
2134
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2135
          wad2 = `OC8051_WAD_N;
2136
          rom_addr_sel = `OC8051_RAS_PC;
2137
          ext_addr_sel = `OC8051_EAS_DC;
2138
        end
2139
      `OC8051_JMP : begin
2140
          ram_rd_sel = `OC8051_RRS_D;
2141
          ram_wr_sel = `OC8051_RWS_DC;
2142
          src_sel1 = `OC8051_ASS_ACC;
2143
          src_sel2 = `OC8051_ASS_RAM;
2144
          alu_op = `OC8051_ALU_ADD;
2145
          wr = 1'b0;
2146
          psw_set = `OC8051_PS_NOT;
2147
          cy_sel = `OC8051_CY_0;
2148
          pc_wr = `OC8051_PCW_N;
2149
          pc_sel = `OC8051_PIS_DC;
2150
          imm_sel = `OC8051_IDS_DC;
2151
          src_sel3 = `OC8051_AS3_DP;
2152
          comp_sel = `OC8051_CSS_BIT;
2153
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2154
          wad2 = `OC8051_WAD_N;
2155
          rom_addr_sel = `OC8051_RAS_PC;
2156
          ext_addr_sel = `OC8051_EAS_DC;
2157
        end
2158
      `OC8051_JNB : begin
2159
          ram_rd_sel = `OC8051_RRS_D;
2160
          ram_wr_sel = `OC8051_RWS_DC;
2161
          src_sel1 = `OC8051_ASS_IMM;
2162
          src_sel2 = `OC8051_ASS_IMM;
2163
          alu_op = `OC8051_ALU_PCS;
2164
          wr = 1'b0;
2165
          psw_set = `OC8051_PS_NOT;
2166
          cy_sel = `OC8051_CY_0;
2167
          pc_wr = `OC8051_PCW_N;
2168
          pc_sel = `OC8051_PIS_DC;
2169
          imm_sel = `OC8051_IDS_OP3_PCL;
2170
          src_sel3 = `OC8051_AS3_PC;
2171
          comp_sel = `OC8051_CSS_BIT;
2172
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2173
          wad2 = `OC8051_WAD_N;
2174
          rom_addr_sel = `OC8051_RAS_PC;
2175
          ext_addr_sel = `OC8051_EAS_DC;
2176
        end
2177
      `OC8051_JNC : begin
2178
          ram_rd_sel = `OC8051_RRS_DC;
2179
          ram_wr_sel = `OC8051_RWS_DC;
2180
          src_sel1 = `OC8051_ASS_IMM;
2181
          src_sel2 = `OC8051_ASS_IMM;
2182
          alu_op = `OC8051_ALU_PCS;
2183
          wr = 1'b0;
2184
          psw_set = `OC8051_PS_NOT;
2185
          cy_sel = `OC8051_CY_0;
2186
          pc_wr = `OC8051_PCW_N;
2187
          pc_sel = `OC8051_PIS_DC;
2188
          imm_sel = `OC8051_IDS_OP2_PCL;
2189
          src_sel3 = `OC8051_AS3_PC;
2190
          comp_sel = `OC8051_CSS_CY;
2191
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2192
          wad2 = `OC8051_WAD_N;
2193
          rom_addr_sel = `OC8051_RAS_PC;
2194
          ext_addr_sel = `OC8051_EAS_DC;
2195
        end
2196
      `OC8051_JNZ :begin
2197
          ram_rd_sel = `OC8051_RRS_DC;
2198
          ram_wr_sel = `OC8051_RWS_DC;
2199
          src_sel1 = `OC8051_ASS_IMM;
2200
          src_sel2 = `OC8051_ASS_IMM;
2201
          alu_op = `OC8051_ALU_PCS;
2202
          wr = 1'b0;
2203
          psw_set = `OC8051_PS_NOT;
2204
          cy_sel = `OC8051_CY_0;
2205
          pc_wr = `OC8051_PCW_N;
2206
          pc_sel = `OC8051_PIS_DC;
2207
          imm_sel = `OC8051_IDS_OP2_PCL;
2208
          src_sel3 = `OC8051_AS3_PC;
2209
          comp_sel = `OC8051_CSS_AZ;
2210
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2211
          wad2 = `OC8051_WAD_N;
2212
          rom_addr_sel = `OC8051_RAS_PC;
2213
          ext_addr_sel = `OC8051_EAS_DC;
2214
        end
2215
      `OC8051_JZ : begin
2216
          ram_rd_sel = `OC8051_RRS_DC;
2217
          ram_wr_sel = `OC8051_RWS_DC;
2218
          src_sel1 = `OC8051_ASS_IMM;
2219
          src_sel2 = `OC8051_ASS_IMM;
2220
          alu_op = `OC8051_ALU_PCS;
2221
          wr = 1'b0;
2222
          psw_set = `OC8051_PS_NOT;
2223
          cy_sel = `OC8051_CY_0;
2224
          pc_wr = `OC8051_PCW_N;
2225
          pc_sel = `OC8051_PIS_DC;
2226
          imm_sel = `OC8051_IDS_OP2_PCL;
2227
          src_sel3 = `OC8051_AS3_PC;
2228
          comp_sel = `OC8051_CSS_AZ;
2229
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2230
          wad2 = `OC8051_WAD_N;
2231
          rom_addr_sel = `OC8051_RAS_PC;
2232
          ext_addr_sel = `OC8051_EAS_DC;
2233
        end
2234
      `OC8051_LCALL :begin
2235
          ram_rd_sel = `OC8051_RRS_DC;
2236
          ram_wr_sel = `OC8051_RWS_SP;
2237
          src_sel1 = `OC8051_ASS_IMM;
2238
          src_sel2 = `OC8051_ASS_DC;
2239
          alu_op = `OC8051_ALU_NOP;
2240
          imm_sel = `OC8051_IDS_PCL;
2241
          wr = 1'b1;
2242
          psw_set = `OC8051_PS_NOT;
2243
          cy_sel = `OC8051_CY_0;
2244
          pc_wr = `OC8051_PCW_Y;
2245
          pc_sel = `OC8051_PIS_I16;
2246
          src_sel3 = `OC8051_AS3_DC;
2247
          comp_sel = `OC8051_CSS_DC;
2248
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2249
          wad2 = `OC8051_WAD_N;
2250
          rom_addr_sel = `OC8051_RAS_PC;
2251
          ext_addr_sel = `OC8051_EAS_DC;
2252
        end
2253
      `OC8051_LJMP : begin
2254
          ram_rd_sel = `OC8051_RRS_DC;
2255
          ram_wr_sel = `OC8051_RWS_DC;
2256
          src_sel1 = `OC8051_ASS_DC;
2257
          src_sel2 = `OC8051_ASS_DC;
2258
          alu_op = `OC8051_ALU_NOP;
2259
          imm_sel = `OC8051_IDS_DC;
2260
          wr = 1'b0;
2261
          psw_set = `OC8051_PS_NOT;
2262
          cy_sel = `OC8051_CY_0;
2263
          pc_wr = `OC8051_PCW_Y;
2264
          pc_sel = `OC8051_PIS_I16;
2265
          src_sel3 = `OC8051_AS3_DC;
2266
          comp_sel = `OC8051_CSS_DC;
2267
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2268
          wad2 = `OC8051_WAD_N;
2269
          rom_addr_sel = `OC8051_RAS_PC;
2270
          ext_addr_sel = `OC8051_EAS_DC;
2271
        end
2272
      `OC8051_MOV_D : begin
2273
          ram_rd_sel = `OC8051_RRS_D;
2274
          ram_wr_sel = `OC8051_RWS_ACC;
2275
          src_sel1 = `OC8051_ASS_RAM;
2276
          src_sel2 = `OC8051_ASS_DC;
2277
          alu_op = `OC8051_ALU_NOP;
2278
          wr = 1'b1;
2279
          psw_set = `OC8051_PS_NOT;
2280
          cy_sel = `OC8051_CY_0;
2281
          pc_wr = `OC8051_PCW_N;
2282
          pc_sel = `OC8051_PIS_DC;
2283
          imm_sel = `OC8051_IDS_DC;
2284
          src_sel3 = `OC8051_AS3_DC;
2285
          comp_sel = `OC8051_CSS_DC;
2286
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2287
          wad2 = `OC8051_WAD_N;
2288
          rom_addr_sel = `OC8051_RAS_PC;
2289
          ext_addr_sel = `OC8051_EAS_DC;
2290
        end
2291
      `OC8051_MOV_C : begin
2292
          ram_rd_sel = `OC8051_RRS_DC;
2293
          ram_wr_sel = `OC8051_RWS_ACC;
2294
          src_sel1 = `OC8051_ASS_IMM;
2295
          src_sel2 = `OC8051_ASS_DC;
2296
          alu_op = `OC8051_ALU_NOP;
2297
          wr = 1'b1;
2298
          psw_set = `OC8051_PS_NOT;
2299
          cy_sel = `OC8051_CY_0;
2300
          pc_wr = `OC8051_PCW_N;
2301
          pc_sel = `OC8051_PIS_DC;
2302
          imm_sel = `OC8051_IDS_OP2;
2303
          src_sel3 = `OC8051_AS3_DC;
2304
          comp_sel = `OC8051_CSS_DC;
2305
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2306
          wad2 = `OC8051_WAD_N;
2307
          rom_addr_sel = `OC8051_RAS_PC;
2308
          ext_addr_sel = `OC8051_EAS_DC;
2309
        end
2310
 
2311
      `OC8051_MOV_DA : begin
2312
          ram_rd_sel = `OC8051_RRS_DC;
2313
          ram_wr_sel = `OC8051_RWS_D;
2314
          src_sel1 = `OC8051_ASS_ACC;
2315
          src_sel2 = `OC8051_ASS_DC;
2316
          alu_op = `OC8051_ALU_NOP;
2317
          wr = 1'b1;
2318
          psw_set = `OC8051_PS_NOT;
2319
          cy_sel = `OC8051_CY_0;
2320
          pc_wr = `OC8051_PCW_N;
2321
          pc_sel = `OC8051_PIS_DC;
2322
          imm_sel = `OC8051_IDS_DC;
2323
          src_sel3 = `OC8051_AS3_DC;
2324
          comp_sel = `OC8051_CSS_DC;
2325
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2326
          wad2 = `OC8051_WAD_N;
2327
          rom_addr_sel = `OC8051_RAS_PC;
2328
          ext_addr_sel = `OC8051_EAS_DC;
2329
        end
2330
      `OC8051_MOV_DD : begin
2331
          ram_rd_sel = `OC8051_RRS_D;
2332
          ram_wr_sel = `OC8051_RWS_D3;
2333
          src_sel1 = `OC8051_ASS_RAM;
2334
          src_sel2 = `OC8051_ASS_DC;
2335
          alu_op = `OC8051_ALU_NOP;
2336
          wr = 1'b1;
2337
          psw_set = `OC8051_PS_NOT;
2338
          cy_sel = `OC8051_CY_0;
2339
          pc_wr = `OC8051_PCW_N;
2340
          pc_sel = `OC8051_PIS_DC;
2341
          imm_sel = `OC8051_IDS_OP2;
2342
          src_sel3 = `OC8051_AS3_DC;
2343
          comp_sel = `OC8051_CSS_DC;
2344
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2345
          wad2 = `OC8051_WAD_N;
2346
          rom_addr_sel = `OC8051_RAS_PC;
2347
          ext_addr_sel = `OC8051_EAS_DC;
2348
        end
2349
      `OC8051_MOV_CD : begin
2350
          ram_rd_sel = `OC8051_RRS_DC;
2351
          ram_wr_sel = `OC8051_RWS_D;
2352
          src_sel1 = `OC8051_ASS_IMM;
2353
          src_sel2 = `OC8051_ASS_DC;
2354
          alu_op = `OC8051_ALU_NOP;
2355
          wr = 1'b1;
2356
          psw_set = `OC8051_PS_NOT;
2357
          cy_sel = `OC8051_CY_0;
2358
          pc_wr = `OC8051_PCW_N;
2359
          pc_sel = `OC8051_PIS_DC;
2360
          imm_sel = `OC8051_IDS_OP3;
2361
          src_sel3 = `OC8051_AS3_DC;
2362
          comp_sel = `OC8051_CSS_DC;
2363
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2364
          wad2 = `OC8051_WAD_N;
2365
          rom_addr_sel = `OC8051_RAS_PC;
2366
          ext_addr_sel = `OC8051_EAS_DC;
2367
        end
2368
      `OC8051_MOV_BC : begin
2369
          ram_rd_sel = `OC8051_RRS_D;
2370
          ram_wr_sel = `OC8051_RWS_DC;
2371
          src_sel1 = `OC8051_ASS_DC;
2372
          src_sel2 = `OC8051_ASS_DC;
2373
          alu_op = `OC8051_ALU_NOP;
2374
          wr = 1'b0;
2375
          psw_set = `OC8051_PS_CY;
2376
          cy_sel = `OC8051_CY_RAM;
2377
          pc_wr = `OC8051_PCW_N;
2378
          pc_sel = `OC8051_PIS_DC;
2379
          imm_sel = `OC8051_IDS_DC;
2380
          src_sel3 = `OC8051_AS3_DC;
2381
          comp_sel = `OC8051_CSS_DC;
2382
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2383
          wad2 = `OC8051_WAD_N;
2384
          rom_addr_sel = `OC8051_RAS_PC;
2385
          ext_addr_sel = `OC8051_EAS_DC;
2386
        end
2387
      `OC8051_MOV_CB : begin
2388
          ram_rd_sel = `OC8051_RRS_D;
2389
          ram_wr_sel = `OC8051_RWS_D;
2390
          src_sel1 = `OC8051_ASS_DC;
2391
          src_sel2 = `OC8051_ASS_DC;
2392
          alu_op = `OC8051_ALU_NOP;
2393
          wr = 1'b1;
2394
          psw_set = `OC8051_PS_NOT;
2395
          cy_sel = `OC8051_CY_PSW;
2396
          pc_wr = `OC8051_PCW_N;
2397
          pc_sel = `OC8051_PIS_DC;
2398
          imm_sel = `OC8051_IDS_OP3;
2399
          src_sel3 = `OC8051_AS3_DC;
2400
          comp_sel = `OC8051_CSS_DC;
2401
          rmw = `OC8051_RMW_N;        bit_addr = 1'b1;
2402
          wad2 = `OC8051_WAD_N;
2403
          rom_addr_sel = `OC8051_RAS_PC;
2404
          ext_addr_sel = `OC8051_EAS_DC;
2405
        end
2406
      `OC8051_MOV_DP : begin  ///***
2407
          ram_rd_sel = `OC8051_RRS_DC;
2408
          ram_wr_sel = `OC8051_RWS_DPTR;
2409
          src_sel1 = `OC8051_ASS_IMM;
2410
          src_sel2 = `OC8051_ASS_IMM;
2411
          alu_op = `OC8051_ALU_NOP;
2412
          wr = 1'b1;
2413
          psw_set = `OC8051_PS_NOT;
2414
          cy_sel = `OC8051_CY_0;
2415
          pc_wr = `OC8051_PCW_N;
2416
          pc_sel = `OC8051_PIS_DC;
2417
          imm_sel = `OC8051_IDS_OP3_OP2;
2418
          src_sel3 = `OC8051_AS3_DC;
2419
          comp_sel = `OC8051_CSS_DC;
2420
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2421
          wad2 = `OC8051_WAD_N;
2422
          rom_addr_sel = `OC8051_RAS_PC;
2423
          ext_addr_sel = `OC8051_EAS_DC;
2424
        end
2425
      `OC8051_MOVC_DP :begin
2426
          ram_rd_sel = `OC8051_RRS_D;
2427
          ram_wr_sel = `OC8051_RWS_DC;
2428
          src_sel1 = `OC8051_ASS_ACC;
2429
          src_sel2 = `OC8051_ASS_RAM;
2430
          alu_op = `OC8051_ALU_ADD;
2431
          wr = 1'b0;
2432
          psw_set = `OC8051_PS_NOT;
2433
          cy_sel = `OC8051_CY_0;
2434
          pc_wr = `OC8051_PCW_N;
2435
          pc_sel = `OC8051_PIS_DC;
2436
          imm_sel = `OC8051_IDS_DC;
2437
          src_sel3 = `OC8051_AS3_DP;
2438
          comp_sel = `OC8051_CSS_DC;
2439
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2440
          wad2 = `OC8051_WAD_N;
2441
          rom_addr_sel = `OC8051_RAS_PC;
2442
          ext_addr_sel = `OC8051_EAS_DC;
2443
        end
2444
      `OC8051_MOVC_PC : begin
2445
          ram_rd_sel = `OC8051_RRS_DC;
2446
          ram_wr_sel = `OC8051_RWS_DC;
2447 8 markom
          src_sel1 = `OC8051_ASS_IMM;
2448
          src_sel2 = `OC8051_ASS_ACC;
2449 2 simont
          alu_op = `OC8051_ALU_ADD;
2450
          wr = 1'b0;
2451
          psw_set = `OC8051_PS_NOT;
2452
          cy_sel = `OC8051_CY_0;
2453
          pc_wr = `OC8051_PCW_N;
2454
          pc_sel = `OC8051_PIS_DC;
2455
          imm_sel = `OC8051_IDS_PCL;
2456
          src_sel3 = `OC8051_AS3_PC;
2457
          comp_sel = `OC8051_CSS_DC;
2458
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2459
          wad2 = `OC8051_WAD_N;
2460
          rom_addr_sel = `OC8051_RAS_PC;
2461
          ext_addr_sel = `OC8051_EAS_DC;
2462
        end
2463
      `OC8051_MOVX_PA : begin
2464
          ram_rd_sel = `OC8051_RRS_DC;
2465
          ram_wr_sel = `OC8051_RWS_ACC;
2466
          src_sel1 = `OC8051_ASS_XRAM;
2467
          src_sel2 = `OC8051_ASS_DC;
2468
          alu_op = `OC8051_ALU_NOP;
2469
          wr = 1'b1;
2470
          psw_set = `OC8051_PS_NOT;
2471
          cy_sel = `OC8051_CY_0;
2472
          pc_wr = `OC8051_PCW_N;
2473
          pc_sel = `OC8051_PIS_DC;
2474
          imm_sel = `OC8051_IDS_OP2;
2475
          src_sel3 = `OC8051_AS3_DC;
2476
          comp_sel = `OC8051_CSS_DC;
2477
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2478
          wad2 = `OC8051_WAD_N;
2479
          rom_addr_sel = `OC8051_RAS_PC;
2480
          ext_addr_sel = `OC8051_EAS_DPTR;
2481
        end
2482
      `OC8051_MOVX_AP : begin
2483
          ram_rd_sel = `OC8051_RRS_DC;
2484
          ram_wr_sel = `OC8051_RWS_DC;
2485
          src_sel1 = `OC8051_ASS_XRAM;
2486
          src_sel2 = `OC8051_ASS_DC;
2487
          alu_op = `OC8051_ALU_NOP;
2488
          wr = 1'b0;
2489
          psw_set = `OC8051_PS_NOT;
2490
          cy_sel = `OC8051_CY_0;
2491
          pc_wr = `OC8051_PCW_N;
2492
          pc_sel = `OC8051_PIS_DC;
2493
          imm_sel = `OC8051_IDS_DC;
2494
          src_sel3 = `OC8051_AS3_DC;
2495
          comp_sel = `OC8051_CSS_DC;
2496
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2497
          wad2 = `OC8051_WAD_N;
2498
          rom_addr_sel = `OC8051_RAS_PC;
2499
          ext_addr_sel = `OC8051_EAS_DPTR;
2500
        end
2501
      `OC8051_MUL : begin
2502
          ram_rd_sel = `OC8051_RRS_D;
2503
          ram_wr_sel = `OC8051_RWS_B;
2504
          src_sel1 = `OC8051_ASS_ACC;
2505
          src_sel2 = `OC8051_ASS_RAM;
2506
          alu_op = `OC8051_ALU_MUL;
2507 20 markom
          wr = 1'b0;
2508 2 simont
          psw_set = `OC8051_PS_OV;
2509
          cy_sel = `OC8051_CY_0;
2510
          pc_wr = `OC8051_PCW_N;
2511
          pc_sel = `OC8051_PIS_DC;
2512
          imm_sel = `OC8051_IDS_DC;
2513
          src_sel3 = `OC8051_AS3_DC;
2514
          comp_sel = `OC8051_CSS_DC;
2515
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2516 20 markom
          wad2 = `OC8051_WAD_N;
2517 2 simont
          rom_addr_sel = `OC8051_RAS_PC;
2518
          ext_addr_sel = `OC8051_EAS_DC;
2519
        end
2520
      `OC8051_ORL_D : begin
2521
          ram_rd_sel = `OC8051_RRS_D;
2522
          ram_wr_sel = `OC8051_RWS_ACC;
2523
          src_sel1 = `OC8051_ASS_RAM;
2524
          src_sel2 = `OC8051_ASS_ACC;
2525
          alu_op = `OC8051_ALU_OR;
2526
          wr = 1'b1;
2527
          psw_set = `OC8051_PS_NOT;
2528
          cy_sel = `OC8051_CY_0;
2529
          pc_wr = `OC8051_PCW_N;
2530
          pc_sel = `OC8051_PIS_DC;
2531
          imm_sel = `OC8051_IDS_DC;
2532
          src_sel3 = `OC8051_AS3_DC;
2533
          comp_sel = `OC8051_CSS_DC;
2534
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2535
          wad2 = `OC8051_WAD_N;
2536
          rom_addr_sel = `OC8051_RAS_PC;
2537
          ext_addr_sel = `OC8051_EAS_DC;
2538
        end
2539
      `OC8051_ORL_C : begin
2540
          ram_rd_sel = `OC8051_RRS_DC;
2541
          ram_wr_sel = `OC8051_RWS_ACC;
2542
          src_sel1 = `OC8051_ASS_IMM;
2543
          src_sel2 = `OC8051_ASS_ACC;
2544
          alu_op = `OC8051_ALU_OR;
2545
          wr = 1'b1;
2546
          psw_set = `OC8051_PS_NOT;
2547
          cy_sel = `OC8051_CY_0;
2548
          pc_wr = `OC8051_PCW_N;
2549
          pc_sel = `OC8051_PIS_DC;
2550
          imm_sel = `OC8051_IDS_OP2;
2551
          src_sel3 = `OC8051_AS3_DC;
2552
          comp_sel = `OC8051_CSS_DC;
2553
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2554
          wad2 = `OC8051_WAD_N;
2555
          rom_addr_sel = `OC8051_RAS_PC;
2556
          ext_addr_sel = `OC8051_EAS_DC;
2557
        end
2558
      `OC8051_ORL_AD : begin
2559
          ram_rd_sel = `OC8051_RRS_D;
2560
          ram_wr_sel = `OC8051_RWS_D;
2561
          src_sel1 = `OC8051_ASS_RAM;
2562
          src_sel2 = `OC8051_ASS_ACC;
2563
          alu_op = `OC8051_ALU_OR;
2564
          wr = 1'b1;
2565
          psw_set = `OC8051_PS_NOT;
2566
          cy_sel = `OC8051_CY_0;
2567
          pc_wr = `OC8051_PCW_N;
2568
          pc_sel = `OC8051_PIS_DC;
2569
          imm_sel = `OC8051_IDS_DC;
2570
          src_sel3 = `OC8051_AS3_DC;
2571
          comp_sel = `OC8051_CSS_DC;
2572
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2573
          wad2 = `OC8051_WAD_N;
2574
          rom_addr_sel = `OC8051_RAS_PC;
2575
          ext_addr_sel = `OC8051_EAS_DC;
2576
        end
2577
      `OC8051_ORL_CD : begin
2578
          ram_rd_sel = `OC8051_RRS_D;
2579
          ram_wr_sel = `OC8051_RWS_D;
2580
          src_sel1 = `OC8051_ASS_IMM;
2581
          src_sel2 = `OC8051_ASS_RAM;
2582
          alu_op = `OC8051_ALU_OR;
2583
          wr = 1'b1;
2584
          psw_set = `OC8051_PS_NOT;
2585
          cy_sel = `OC8051_CY_0;
2586
          pc_wr = `OC8051_PCW_N;
2587
          pc_sel = `OC8051_PIS_DC;
2588
          imm_sel = `OC8051_IDS_OP3;
2589
          src_sel3 = `OC8051_AS3_DC;
2590
          comp_sel = `OC8051_CSS_DC;
2591
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2592
          wad2 = `OC8051_WAD_N;
2593
          rom_addr_sel = `OC8051_RAS_PC;
2594
          ext_addr_sel = `OC8051_EAS_DC;
2595
        end
2596
      `OC8051_ORL_B : begin
2597
          ram_rd_sel = `OC8051_RRS_D;
2598
          ram_wr_sel = `OC8051_RWS_DC;
2599
          src_sel1 = `OC8051_ASS_DC;
2600
          src_sel2 = `OC8051_ASS_DC;
2601
          alu_op = `OC8051_ALU_OR;
2602
          wr = 1'b0;
2603
          psw_set = `OC8051_PS_CY;
2604
          cy_sel = `OC8051_CY_PSW;
2605
          pc_wr = `OC8051_PCW_N;
2606
          pc_sel = `OC8051_PIS_DC;
2607
          imm_sel = `OC8051_IDS_DC;
2608
          src_sel3 = `OC8051_AS3_DC;
2609
          comp_sel = `OC8051_CSS_DC;
2610
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2611
          wad2 = `OC8051_WAD_N;
2612
          rom_addr_sel = `OC8051_RAS_PC;
2613
          ext_addr_sel = `OC8051_EAS_DC;
2614
        end
2615
      `OC8051_ORL_NB : begin
2616
          ram_rd_sel = `OC8051_RRS_D;
2617
          ram_wr_sel = `OC8051_RWS_DC;
2618
          src_sel1 = `OC8051_ASS_DC;
2619
          src_sel2 = `OC8051_ASS_DC;
2620
          alu_op = `OC8051_ALU_RL;
2621
          wr = 1'b0;
2622
          psw_set = `OC8051_PS_CY;
2623
          cy_sel = `OC8051_CY_PSW;
2624
          pc_wr = `OC8051_PCW_N;
2625
          pc_sel = `OC8051_PIS_DC;
2626
          imm_sel = `OC8051_IDS_DC;
2627
          src_sel3 = `OC8051_AS3_DC;
2628
          comp_sel = `OC8051_CSS_DC;
2629
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2630
          wad2 = `OC8051_WAD_N;
2631
          rom_addr_sel = `OC8051_RAS_PC;
2632
          ext_addr_sel = `OC8051_EAS_DC;
2633
        end
2634
      `OC8051_POP : begin
2635
          ram_rd_sel = `OC8051_RRS_SP;
2636
          ram_wr_sel = `OC8051_RWS_D;
2637
          src_sel1 = `OC8051_ASS_RAM;
2638
          src_sel2 = `OC8051_ASS_DC;
2639
          alu_op = `OC8051_ALU_NOP;
2640
          wr = 1'b1;
2641
          psw_set = `OC8051_PS_NOT;
2642
          cy_sel = `OC8051_CY_0;
2643
          pc_wr = `OC8051_PCW_N;
2644
          pc_sel = `OC8051_PIS_DC;
2645
          imm_sel = `OC8051_IDS_DC;
2646
          src_sel3 = `OC8051_AS3_DC;
2647
          comp_sel = `OC8051_CSS_DC;
2648
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2649
          wad2 = `OC8051_WAD_N;
2650
          rom_addr_sel = `OC8051_RAS_PC;
2651
          ext_addr_sel = `OC8051_EAS_DC;
2652
        end
2653
      `OC8051_PUSH : begin
2654
          ram_rd_sel = `OC8051_RRS_D;
2655
          ram_wr_sel = `OC8051_RWS_SP;
2656
          src_sel1 = `OC8051_ASS_RAM;
2657
          src_sel2 = `OC8051_ASS_DC;
2658
          alu_op = `OC8051_ALU_NOP;
2659
          wr = 1'b1;
2660
          psw_set = `OC8051_PS_NOT;
2661
          cy_sel = `OC8051_CY_0;
2662
          pc_wr = `OC8051_PCW_N;
2663
          pc_sel = `OC8051_PIS_DC;
2664
          imm_sel = `OC8051_IDS_DC;
2665
          src_sel3 = `OC8051_AS3_DC;
2666
          comp_sel = `OC8051_CSS_DC;
2667
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2668
          wad2 = `OC8051_WAD_N;
2669
          rom_addr_sel = `OC8051_RAS_PC;
2670
          ext_addr_sel = `OC8051_EAS_DC;
2671
        end
2672
      `OC8051_RET : begin
2673
          ram_rd_sel = `OC8051_RRS_SP;
2674
          ram_wr_sel = `OC8051_RWS_DC;
2675
          src_sel1 = `OC8051_ASS_RAM;
2676
          src_sel2 = `OC8051_ASS_DC;
2677
          alu_op = `OC8051_ALU_NOP;
2678
          wr = 1'b0;
2679
          psw_set = `OC8051_PS_NOT;
2680
          cy_sel = `OC8051_CY_0;
2681
          pc_wr = `OC8051_PCW_N;
2682
          pc_sel = `OC8051_PIS_DC;
2683
          imm_sel = `OC8051_IDS_DC;
2684
          src_sel3 = `OC8051_AS3_DC;
2685
          comp_sel = `OC8051_CSS_DC;
2686
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2687
          wad2 = `OC8051_WAD_N;
2688
          rom_addr_sel = `OC8051_RAS_PC;
2689
          ext_addr_sel = `OC8051_EAS_DC;
2690
        end
2691
      `OC8051_RETI : begin
2692
          ram_rd_sel = `OC8051_RRS_SP;
2693
          ram_wr_sel = `OC8051_RWS_DC;
2694
          src_sel1 = `OC8051_ASS_RAM;
2695
          src_sel2 = `OC8051_ASS_DC;
2696
          alu_op = `OC8051_ALU_NOP;
2697
          wr = 1'b0;
2698
          psw_set = `OC8051_PS_NOT;
2699
          cy_sel = `OC8051_CY_0;
2700
          pc_wr = `OC8051_PCW_N;
2701
          pc_sel = `OC8051_PIS_DC;
2702
          imm_sel = `OC8051_IDS_DC;
2703
          src_sel3 = `OC8051_AS3_DC;
2704
          comp_sel = `OC8051_CSS_DC;
2705
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2706
          wad2 = `OC8051_WAD_N;
2707
          rom_addr_sel = `OC8051_RAS_PC;
2708
          ext_addr_sel = `OC8051_EAS_DC;
2709
        end
2710
      `OC8051_RL : begin
2711
          ram_rd_sel = `OC8051_RRS_DC;
2712
          ram_wr_sel = `OC8051_RWS_ACC;
2713
          src_sel1 = `OC8051_ASS_ACC;
2714
          src_sel2 = `OC8051_ASS_DC;
2715
          alu_op = `OC8051_ALU_RL;
2716
          wr = 1'b1;
2717
          psw_set = `OC8051_PS_NOT;
2718
          cy_sel = `OC8051_CY_0;
2719
          pc_wr = `OC8051_PCW_N;
2720
          pc_sel = `OC8051_PIS_DC;
2721
          imm_sel = `OC8051_IDS_DC;
2722
          src_sel3 = `OC8051_AS3_DC;
2723
          comp_sel = `OC8051_CSS_DC;
2724
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2725
          wad2 = `OC8051_WAD_N;
2726
          rom_addr_sel = `OC8051_RAS_PC;
2727
          ext_addr_sel = `OC8051_EAS_DC;
2728
        end
2729
      `OC8051_RLC : begin
2730
          ram_rd_sel = `OC8051_RRS_DC;
2731
          ram_wr_sel = `OC8051_RWS_ACC;
2732
          src_sel1 = `OC8051_ASS_ACC;
2733
          src_sel2 = `OC8051_ASS_DC;
2734
          alu_op = `OC8051_ALU_RLC;
2735
          wr = 1'b1;
2736
          psw_set = `OC8051_PS_CY;
2737
          cy_sel = `OC8051_CY_PSW;
2738
          pc_wr = `OC8051_PCW_N;
2739
          pc_sel = `OC8051_PIS_DC;
2740
          imm_sel = `OC8051_IDS_DC;
2741
          src_sel3 = `OC8051_AS3_DC;
2742
          comp_sel = `OC8051_CSS_DC;
2743
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2744
          wad2 = `OC8051_WAD_N;
2745
          rom_addr_sel = `OC8051_RAS_PC;
2746
          ext_addr_sel = `OC8051_EAS_DC;
2747
        end
2748
      `OC8051_RR : begin
2749
          ram_rd_sel = `OC8051_RRS_DC;
2750
          ram_wr_sel = `OC8051_RWS_ACC;
2751
          src_sel1 = `OC8051_ASS_ACC;
2752
          src_sel2 = `OC8051_ASS_DC;
2753
          alu_op = `OC8051_ALU_RR;
2754
          wr = 1'b1;
2755
          psw_set = `OC8051_PS_NOT;
2756
          cy_sel = `OC8051_CY_0;
2757
          pc_wr = `OC8051_PCW_N;
2758
          pc_sel = `OC8051_PIS_DC;
2759
          imm_sel = `OC8051_IDS_DC;
2760
          src_sel3 = `OC8051_AS3_DC;
2761
          comp_sel = `OC8051_CSS_DC;
2762
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2763
          wad2 = `OC8051_WAD_N;
2764
          rom_addr_sel = `OC8051_RAS_PC;
2765
          ext_addr_sel = `OC8051_EAS_DC;
2766
        end
2767
      `OC8051_RRC : begin
2768
          ram_rd_sel = `OC8051_RRS_DC;
2769
          ram_wr_sel = `OC8051_RWS_ACC;
2770
          src_sel1 = `OC8051_ASS_ACC;
2771
          src_sel2 = `OC8051_ASS_DC;
2772
          alu_op = `OC8051_ALU_RRC;
2773
          wr = 1'b1;
2774
          psw_set = `OC8051_PS_CY;
2775
          cy_sel = `OC8051_CY_PSW;
2776
          pc_wr = `OC8051_PCW_N;
2777
          pc_sel = `OC8051_PIS_DC;
2778
          imm_sel = `OC8051_IDS_DC;
2779
          src_sel3 = `OC8051_AS3_DC;
2780
          comp_sel = `OC8051_CSS_DC;
2781
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2782
          wad2 = `OC8051_WAD_N;
2783
          rom_addr_sel = `OC8051_RAS_PC;
2784
          ext_addr_sel = `OC8051_EAS_DC;
2785
        end
2786
      `OC8051_SETB_C : begin
2787
          ram_rd_sel = `OC8051_RRS_DC;
2788
          ram_wr_sel = `OC8051_RWS_DC;
2789
          src_sel1 = `OC8051_ASS_DC;
2790
          src_sel2 = `OC8051_ASS_DC;
2791
          alu_op = `OC8051_ALU_NOP;
2792
          wr = 1'b0;
2793
          psw_set = `OC8051_PS_CY;
2794
          cy_sel = `OC8051_CY_1;
2795
          pc_wr = `OC8051_PCW_N;
2796
          pc_sel = `OC8051_PIS_DC;
2797
          imm_sel = `OC8051_IDS_DC;
2798
          src_sel3 = `OC8051_AS3_PC;
2799
          comp_sel = `OC8051_CSS_DC;
2800
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2801
          wad2 = `OC8051_WAD_N;
2802
          rom_addr_sel = `OC8051_RAS_PC;
2803
          ext_addr_sel = `OC8051_EAS_DC;
2804
        end
2805
      `OC8051_SETB_B : begin
2806
          ram_rd_sel = `OC8051_RRS_D;
2807
          ram_wr_sel = `OC8051_RWS_D;
2808
          src_sel1 = `OC8051_ASS_DC;
2809
          src_sel2 = `OC8051_ASS_DC;
2810
          alu_op = `OC8051_ALU_NOP;
2811
          wr = 1'b1;
2812
          psw_set = `OC8051_PS_NOT;
2813
          cy_sel = `OC8051_CY_1;
2814
          pc_wr = `OC8051_PCW_N;
2815
          pc_sel = `OC8051_PIS_DC;
2816
          imm_sel = `OC8051_IDS_DC;
2817
          src_sel3 = `OC8051_AS3_PC;
2818
          comp_sel = `OC8051_CSS_DC;
2819
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b1;
2820
          wad2 = `OC8051_WAD_N;
2821
          rom_addr_sel = `OC8051_RAS_PC;
2822
          ext_addr_sel = `OC8051_EAS_DC;
2823
        end
2824
      `OC8051_SJMP : begin
2825
          ram_rd_sel = `OC8051_RRS_DC;
2826
          ram_wr_sel = `OC8051_RWS_DC;
2827
          src_sel1 = `OC8051_ASS_IMM;
2828
          src_sel2 = `OC8051_ASS_IMM;
2829
          alu_op = `OC8051_ALU_PCS;
2830
          wr = 1'b0;
2831
          psw_set = `OC8051_PS_NOT;
2832
          cy_sel = `OC8051_CY_0;
2833
          pc_wr = `OC8051_PCW_N;
2834
          pc_sel = `OC8051_PIS_DC;
2835
          imm_sel = `OC8051_IDS_OP2_PCL;
2836
          src_sel3 = `OC8051_AS3_PC;
2837
          comp_sel = `OC8051_CSS_DC;
2838
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2839
          wad2 = `OC8051_WAD_N;
2840
          rom_addr_sel = `OC8051_RAS_PC;
2841
          ext_addr_sel = `OC8051_EAS_DC;
2842
        end
2843
      `OC8051_SUBB_D : begin
2844
          ram_rd_sel = `OC8051_RRS_D;
2845
          ram_wr_sel = `OC8051_RWS_ACC;
2846
          src_sel1 = `OC8051_ASS_ACC;
2847
          src_sel2 = `OC8051_ASS_RAM;
2848
          alu_op = `OC8051_ALU_SUB;
2849
          wr = 1'b1;
2850
          psw_set = `OC8051_PS_AC;
2851
          cy_sel = `OC8051_CY_PSW;
2852
          pc_wr = `OC8051_PCW_N;
2853
          pc_sel = `OC8051_PIS_DC;
2854
          imm_sel = `OC8051_IDS_DC;
2855
          src_sel3 = `OC8051_AS3_DC;
2856
          comp_sel = `OC8051_CSS_DC;
2857
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2858
          wad2 = `OC8051_WAD_N;
2859
          rom_addr_sel = `OC8051_RAS_PC;
2860
          ext_addr_sel = `OC8051_EAS_DC;
2861
        end
2862
      `OC8051_SUBB_C : begin
2863
          ram_rd_sel = `OC8051_RRS_DC;
2864
          ram_wr_sel = `OC8051_RWS_ACC;
2865
          src_sel1 = `OC8051_ASS_ACC;
2866
          src_sel2 = `OC8051_ASS_IMM;
2867
          alu_op = `OC8051_ALU_SUB;
2868
          wr = 1'b1;
2869
          psw_set = `OC8051_PS_AC;
2870
          cy_sel = `OC8051_CY_PSW;
2871
          pc_wr = `OC8051_PCW_N;
2872
          pc_sel = `OC8051_PIS_DC;
2873
          imm_sel = `OC8051_IDS_OP2;
2874
          src_sel3 = `OC8051_AS3_DC;
2875
          comp_sel = `OC8051_CSS_DC;
2876
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2877
          wad2 = `OC8051_WAD_N;
2878
          rom_addr_sel = `OC8051_RAS_PC;
2879
          ext_addr_sel = `OC8051_EAS_DC;
2880
        end
2881
      `OC8051_SWAP : begin
2882
          ram_rd_sel = `OC8051_RRS_DC;
2883
          ram_wr_sel = `OC8051_RWS_DC;
2884
          src_sel1 = `OC8051_ASS_ACC;
2885
          src_sel2 = `OC8051_ASS_DC;
2886
          alu_op = `OC8051_ALU_RLC;
2887
          wr = 1'b0;
2888
          psw_set = `OC8051_PS_NOT;
2889
          cy_sel = `OC8051_CY_0;
2890
          pc_wr = `OC8051_PCW_N;
2891
          pc_sel = `OC8051_PIS_DC;
2892
          imm_sel = `OC8051_IDS_DC;
2893
          src_sel3 = `OC8051_AS3_DC;
2894
          comp_sel = `OC8051_CSS_DC;
2895
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2896
          wad2 = `OC8051_WAD_Y;
2897
          rom_addr_sel = `OC8051_RAS_PC;
2898
          ext_addr_sel = `OC8051_EAS_DC;
2899
        end
2900
      `OC8051_XCH_D : begin
2901
          ram_rd_sel = `OC8051_RRS_D;
2902
          ram_wr_sel = `OC8051_RWS_D;
2903
          src_sel1 = `OC8051_ASS_RAM;
2904
          src_sel2 = `OC8051_ASS_ACC;
2905
          alu_op = `OC8051_ALU_XCH;
2906
          wr = 1'b1;
2907
          psw_set = `OC8051_PS_NOT;
2908
          cy_sel = `OC8051_CY_1;
2909
          pc_wr = `OC8051_PCW_N;
2910
          pc_sel = `OC8051_PIS_DC;
2911
          imm_sel = `OC8051_IDS_DC;
2912
          src_sel3 = `OC8051_AS3_DC;
2913
          comp_sel = `OC8051_CSS_DC;
2914
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
2915
          wad2 = `OC8051_WAD_Y;
2916
          rom_addr_sel = `OC8051_RAS_PC;
2917
          ext_addr_sel = `OC8051_EAS_DC;
2918
        end
2919
      `OC8051_XRL_D : begin
2920
          ram_rd_sel = `OC8051_RRS_D;
2921
          ram_wr_sel = `OC8051_RWS_ACC;
2922
          src_sel1 = `OC8051_ASS_RAM;
2923
          src_sel2 = `OC8051_ASS_ACC;
2924
          alu_op = `OC8051_ALU_XOR;
2925
          wr = 1'b1;
2926
          psw_set = `OC8051_PS_NOT;
2927
          cy_sel = `OC8051_CY_0;
2928
          pc_wr = `OC8051_PCW_N;
2929
          pc_sel = `OC8051_PIS_DC;
2930
          imm_sel = `OC8051_IDS_DC;
2931
          src_sel3 = `OC8051_AS3_DC;
2932
          comp_sel = `OC8051_CSS_DC;
2933
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2934
          wad2 = `OC8051_WAD_N;
2935
          rom_addr_sel = `OC8051_RAS_PC;
2936
          ext_addr_sel = `OC8051_EAS_DC;
2937
        end
2938
      `OC8051_XRL_C : begin
2939
          ram_rd_sel = `OC8051_RRS_DC;
2940
          ram_wr_sel = `OC8051_RWS_ACC;
2941
          src_sel1 = `OC8051_ASS_IMM;
2942
          src_sel2 = `OC8051_ASS_ACC;
2943
          alu_op = `OC8051_ALU_XOR;
2944
          wr = 1'b1;
2945
          psw_set = `OC8051_PS_NOT;
2946
          cy_sel = `OC8051_CY_0;
2947
          pc_wr = `OC8051_PCW_N;
2948
          pc_sel = `OC8051_PIS_DC;
2949
          imm_sel = `OC8051_IDS_OP2;
2950
          src_sel3 = `OC8051_AS3_DC;
2951
          comp_sel = `OC8051_CSS_DC;
2952
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2953
          wad2 = `OC8051_WAD_N;
2954
          rom_addr_sel = `OC8051_RAS_PC;
2955
          ext_addr_sel = `OC8051_EAS_DC;
2956
        end
2957
      `OC8051_XRL_AD : begin
2958
          ram_rd_sel = `OC8051_RRS_D;
2959
          ram_wr_sel = `OC8051_RWS_D;
2960
          src_sel1 = `OC8051_ASS_RAM;
2961
          src_sel2 = `OC8051_ASS_ACC;
2962
          alu_op = `OC8051_ALU_XOR;
2963
          wr = 1'b1;
2964
          psw_set = `OC8051_PS_NOT;
2965
          cy_sel = `OC8051_CY_0;
2966
          pc_wr = `OC8051_PCW_N;
2967
          pc_sel = `OC8051_PIS_DC;
2968
          imm_sel = `OC8051_IDS_DC;
2969
          src_sel3 = `OC8051_AS3_DC;
2970
          comp_sel = `OC8051_CSS_DC;
2971
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2972
          wad2 = `OC8051_WAD_N;
2973
          rom_addr_sel = `OC8051_RAS_PC;
2974
          ext_addr_sel = `OC8051_EAS_DC;
2975
        end
2976
      `OC8051_XRL_CD : begin
2977
          ram_rd_sel = `OC8051_RRS_D;
2978
          ram_wr_sel = `OC8051_RWS_D;
2979
          src_sel1 = `OC8051_ASS_IMM;
2980
          src_sel2 = `OC8051_ASS_RAM;
2981
          alu_op = `OC8051_ALU_XOR;
2982
          wr = 1'b1;
2983
          psw_set = `OC8051_PS_NOT;
2984
          cy_sel = `OC8051_CY_0;
2985
          pc_wr = `OC8051_PCW_N;
2986
          pc_sel = `OC8051_PIS_DC;
2987
          imm_sel = `OC8051_IDS_OP3;
2988
          src_sel3 = `OC8051_AS3_DC;
2989
          comp_sel = `OC8051_CSS_DC;
2990
          rmw = `OC8051_RMW_Y;        bit_addr = 1'b0;
2991
          wad2 = `OC8051_WAD_N;
2992
          rom_addr_sel = `OC8051_RAS_PC;
2993
          ext_addr_sel = `OC8051_EAS_DC;
2994
        end
2995
      default: begin
2996
          ram_rd_sel = `OC8051_RRS_DC;
2997
          ram_wr_sel = `OC8051_RWS_DC;
2998
          src_sel1 = `OC8051_ASS_DC;
2999
          src_sel2 = `OC8051_ASS_DC;
3000
          alu_op = `OC8051_ALU_NOP;
3001
          imm_sel = `OC8051_IDS_DC;
3002
          wr = 1'b0;
3003
          psw_set = `OC8051_PS_NOT;
3004
          cy_sel = `OC8051_CY_0;
3005
          pc_wr = `OC8051_PCW_N;
3006
          pc_sel = `OC8051_PIS_DC;
3007
          src_sel3 = `OC8051_AS3_DC;
3008
          comp_sel = `OC8051_CSS_DC;
3009
          rmw = `OC8051_RMW_N;        bit_addr = 1'b0;
3010
          wad2 = `OC8051_WAD_N;
3011
          rom_addr_sel = `OC8051_RAS_PC;
3012
          ext_addr_sel = `OC8051_EAS_DC;
3013
       end
3014
 
3015
    endcase
3016
    end
3017
    endcase
3018
end
3019
 
3020
//
3021
// remember current instruction
3022 4 markom
always @(posedge clk or posedge rst)
3023
  if (rst) op <= #1 2'b00;
3024
  else if (state==2'b00) op <= #1 op_in;
3025 2 simont
 
3026
//
3027
// in case of instructions that needs more than one clock set state
3028
always @(posedge clk or posedge rst)
3029
begin
3030
  if (rst)
3031 17 simont
    state <= #1 2'b01;
3032 2 simont
  else begin
3033
    case (state)
3034
      2'b10: state <= #1 2'b01;
3035
      2'b11: state <= #1 2'b10;
3036
      2'b00:
3037
        casex (op_in)
3038
          `OC8051_ACALL :state <= #1 2'b01;
3039
          `OC8051_AJMP : state <= #1 2'b01;
3040
          `OC8051_CJNE_R :state <= #1 2'b11;
3041
          `OC8051_CJNE_I :state <= #1 2'b11;
3042
          `OC8051_CJNE_D : state <= #1 2'b11;
3043
          `OC8051_CJNE_C : state <= #1 2'b11;
3044
          `OC8051_LJMP : state <= #1 2'b01;
3045
          `OC8051_DJNZ_R :state <= #1 2'b11;
3046
          `OC8051_DJNZ_D :state <= #1 2'b11;
3047
          `OC8051_LCALL :state <= #1 2'b01;
3048
          `OC8051_MOVC_DP :state <= #1 2'b10;
3049
          `OC8051_MOVC_PC :state <= #1 2'b10;
3050
          `OC8051_RET : state <= #1 2'b11;
3051
          `OC8051_RETI : state <= #1 2'b11;
3052
          `OC8051_SJMP : state <= #1 2'b10;
3053
          `OC8051_JB : state <= #1 2'b10;
3054
          `OC8051_JBC : state <= #1 2'b10;
3055
          `OC8051_JC : state <= #1 2'b10;
3056
          `OC8051_JMP : state <= #1 2'b10;
3057
          `OC8051_JNC : state <= #1 2'b10;
3058
          `OC8051_JNB : state <= #1 2'b10;
3059
          `OC8051_JNZ : state <= #1 2'b10;
3060
          `OC8051_JZ : state <= #1 2'b10;
3061 20 markom
          `OC8051_DIV : state <= #1 2'b11;
3062
          `OC8051_MUL : state <= #1 2'b11;
3063 2 simont
          default: state <= #1 2'b00;
3064
        endcase
3065
      default: state <= #1 2'b00;
3066
    endcase
3067
  end
3068
end
3069
 
3070
//
3071
//in case of reti
3072
always @(posedge clk)
3073
  if (op==`OC8051_RETI) reti <= #1 1'b1;
3074
  else reti <= #1 1'b0;
3075
 
3076
//
3077
//in case of writing to external ram
3078
always @(op_in or rst or rd)
3079
begin
3080
  if (rst)
3081
    write_x = 1'b0;
3082
  else if (rd)
3083
  begin
3084
    casex (op_in)
3085
      `OC8051_MOVX_AI : write_x = 1'b1;
3086
      `OC8051_MOVX_AP : write_x = 1'b1;
3087
      default : write_x = 1'b0;
3088
    endcase
3089
  end else write_x = 1'b0;
3090
end
3091
 
3092
 
3093
endmodule
3094
 
3095
 

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