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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_dptr.v] - Blame information for rev 118

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1 82 simont
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 data pointer                                           ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   8051 special function register: data pointer               ////
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////                                                              ////
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////  To Do:                                                      ////
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////   nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 118 simont
// Revision 1.3  2003/01/13 14:14:40  simont
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// replace some modules
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//
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// Revision 1.2  2002/09/30 17:33:59  simont
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// prepared header
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//
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//
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// synopsys translate_off
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`include "oc8051_timescale.v"
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// synopsys translate_on
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`include "oc8051_defines.v"
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module oc8051_dptr(clk, rst, addr, data_in, data2_in, wr, wr_sfr, wr_bit, data_hi, data_lo);
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//
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// clk          (in)  clock
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// rst          (in)  reset
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// addr         (in)  write address input [oc8051_ram_wr_sel.out]
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// data_in      (in)  destination 1 from alu [oc8051_alu.des1]
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// data2_in     (in)  destination 2 from alu [oc8051_alu.des2]
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// wr           (in)  write to ram [oc8051_decoder.wr -r]
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// wd2          (in)  write from destination 2 [oc8051_decoder.ram_wr_sel -r]
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// wr_bit       (in)  write bit addresable [oc8051_decoder.bit_addr -r]
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// data_hi      (out) output (high bits) [oc8051_alu_src3_sel.dptr, oc8051_ext_addr_sel.dptr_hi, oc8051_ram_sel.dptr_hi]
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// data_lo      (out) output (low bits) [oc8051_ext_addr_sel.dptr_lo]
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//
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input clk, rst, wr, wr_bit;
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input [1:0] wr_sfr;
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input [7:0] addr, data_in, data2_in;
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output [7:0] data_hi, data_lo;
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reg [7:0] data_hi, data_lo;
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    data_hi <= #1 `OC8051_RST_DPH;
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    data_lo <= #1 `OC8051_RST_DPL;
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  end else if (wr_sfr==`OC8051_WRS_DPTR) begin
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//
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//write from destination 2 and 1
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    data_hi <= #1 data2_in;
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    data_lo <= #1 data_in;
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  end else if ((addr==`OC8051_SFR_DPTR_HI) & (wr) & !(wr_bit))
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//
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//case of writing to dptr
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    data_hi <= #1 data_in;
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  else if ((addr==`OC8051_SFR_DPTR_LO) & (wr) & !(wr_bit))
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    data_lo <= #1 data_in;
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end
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endmodule
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