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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_icache.v] - Blame information for rev 62

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 instruction cache                                      ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 instruction cache                                      ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,
        dat_i, cyc_o, adr_o, ack_i, stb_o);
//
// rst           (in)  reset - pin
// clk           (in)  clock - pini
input rst, clk;
 
//
// interface to oc8051 cpu
//
// adr_i    (in)  address
// dat_o    (out) data output
// stb_i    (in)  strobe
// ack_o    (out) acknowledge
// cyc_i    (in)  cycle
input stb_i, cyc_i;
input [15:0] adr_i;
output ack_o;
output [31:0] dat_o;
reg [31:0] dat_o;
 
//
// interface to instruction rom
//
// adr_o    (out) address
// dat_i    (in)  data input
// stb_o    (out) strobe
// ack_i    (in) acknowledge
// cyc_o    (out)  cycle
input ack_i;
input [31:0] dat_i;
output stb_o, cyc_o;
output [15:0] adr_o;
reg [15:0] adr_o;
reg stb_o, cyc_o;
 
//
// internal buffers adn wires
//
// con_buf control buffer
// con0, con2 contain temporal control information of current address and corrent address+2
reg [7:0] con_buf [15:0];
reg [15:0] vaild;
reg [8:0] con0, con2;
reg [7:0] cadr0, cadr2;
reg stb_b;
reg [1:0] byte_sel;
reg [1:0] cyc;
reg [31:0] data1_i;
reg [15:0] tmp_data1;
reg wr1, wr1_t, stb_it;
 
wire [31:0] data0, data1_o;
wire cy, cy1;
wire [3:0] adr_i2;
wire hit, hit_l, hit_h;
wire [5:0] adr_r, addr1;
reg [5:0] adr_w;
reg [15:0] mis_adr;
wire [15:0] data1;
wire [1:0] adr_r1;
 
assign cy = &adr_i[3:1];
assign {cy1, adr_i2} = {1'b0, adr_i[7:4]}+{4'b0000, cy};
assign hit_l =(con0=={cadr0,1'b1});
assign hit_h =(con2=={cadr2,1'b1});
assign hit = hit_l && hit_h;
 
assign adr_r = adr_i[7:2] + {5'b00000, adr_i[1]};
assign addr1 = wr1 ? adr_w : adr_r;
assign adr_r1 = adr_r[1:0] + 2'b01;
//assign ack_o = hit;
assign ack_o = hit && stb_it;
 
assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];
 
oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[7:2]),
       .addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),
       .wr1(wr1));
 
always @(stb_b or data0 or data1 or byte_sel)
begin
  if (stb_b) begin
    case (byte_sel)
      2'b00: dat_o = data0;
      2'b01: dat_o = {data0[23:0], data1[15:8]};
      2'b10: dat_o = {data0[15:0], data1};
      default: dat_o = {data0[7:0], data1, 8'h00};
    endcase
  end else begin
    dat_o = 32'h0;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    con0 <= #1 9'h0;
    con2 <= #1 9'h0;
  end else begin
    con0 <= #1 {con_buf[adr_i[7:4]], vaild[adr_i[7:4]]};
    con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    cadr0 <= #1 8'h00;
    cadr2 <= #1 8'h00;
  end else begin
    cadr0 <= #1 adr_i[15:8];
    cadr2 <= #1 adr_i[15:8]+{7'h0, cy1};
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    stb_b <= #1 1'b0;
    byte_sel <= #1 1'b0;
  end else begin
    stb_b <= #1 stb_i;
    byte_sel <= #1 adr_i[1:0];
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    cyc <= #1 2'b00;
    adr_o <= #1 16'd0;
    cyc_o <= #1 1'b0;
    stb_o <= #1 1'b0;
    data1_i<= #1 32'd0;
    wr1 <= #1 1'b0;
    adr_w <= #1 6'd0;
    vaild <= #1 16'd0;
  end if (stb_b && !hit && !stb_o && !wr1) begin
    cyc <= #1 2'b00;
    adr_o <= #1 {mis_adr[15:4], 4'b0000};
    cyc_o <= #1 1'b1;
    stb_o <= #1 1'b1;
    data1_i<= #1 32'h0;
    wr1 <= #1 1'b0;
  end if (stb_o && ack_i) begin
    data1_i<= #1 dat_i;
    wr1 <= #1 1'b1;
    adr_w <= #1 adr_o[7:2];
    case (cyc)
      2'b00: begin
        cyc <= #1 2'b01;
        adr_o <= #1 {mis_adr[15:4], 4'b0100};
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      2'b01: begin
        cyc <= #1 2'b10;
        adr_o <= #1 {mis_adr[15:4], 4'b1000};
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      2'b10: begin
        cyc <= #1 2'b11;
        adr_o <= #1 {mis_adr[15:4], 4'b1100};
        cyc_o <= #1 1'b1;
        stb_o <= #1 1'b1;
      end
      default: begin
        cyc <= #1 2'b00;
        adr_o <= #1 {mis_adr[15:4], 4'b0000};
        cyc_o <= #1 1'b0;
        stb_o <= #1 1'b0;
        con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];
        vaild[mis_adr[7:4]] <= #1 1'b1;
      end
    endcase
/*  end else if (wr1 && (cyc==2'b00)) begin
    vaild[mis_adr[7:4]] <= #1 1'b1;
    wr1 <= #1 1'b0;*/
  end else begin
    adr_o <= #1 {mis_adr[15:4], cyc, 2'b00};
    wr1 <= #1 1'b0;
  end
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    mis_adr <= #1 16'h0000;
  else if (!hit_l)
    mis_adr <= #1 adr_i;
  else if (!hit_h)
    mis_adr <= #1 adr_i+{16'd2};
end
 
always @(posedge clk or posedge rst)
begin
  if (rst)
    tmp_data1 <= #1 16'd0;
  else if (!hit_h && wr1 && (cyc==adr_r1))
    tmp_data1 <= #1 dat_i[31:16];
  else if (!hit_l && hit_h && wr1)
    tmp_data1 <= #1 data1_o[31:16];
end
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    wr1_t <= #1 1'b0;
    stb_it <= #1 1'b0;
  end else begin
    wr1_t <= #1 wr1;
    stb_it <= #1 stb_i;
  end
end
 
endmodule

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_icache.v] - Blame information for rev 62

Line No.	Rev	Author	Line
1	62	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 instruction cache ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 instruction cache ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48
49			`// synopsys translate_off`
50			`include "oc8051_timescale.v"
51			`// synopsys translate_on`
52
53
54			`module oc8051_icache (rst, clk, adr_i, dat_o,stb_i, ack_o, cyc_i,`
55			`dat_i, cyc_o, adr_o, ack_i, stb_o);`
56			`//`
57			`// rst (in) reset - pin`
58			`// clk (in) clock - pini`
59			`input rst, clk;`
60
61			`//`
62			`// interface to oc8051 cpu`
63			`//`
64			`// adr_i (in) address`
65			`// dat_o (out) data output`
66			`// stb_i (in) strobe`
67			`// ack_o (out) acknowledge`
68			`// cyc_i (in) cycle`
69			`input stb_i, cyc_i;`
70			`input [15:0] adr_i;`
71			`output ack_o;`
72			`output [31:0] dat_o;`
73			`reg [31:0] dat_o;`
74
75			`//`
76			`// interface to instruction rom`
77			`//`
78			`// adr_o (out) address`
79			`// dat_i (in) data input`
80			`// stb_o (out) strobe`
81			`// ack_i (in) acknowledge`
82			`// cyc_o (out) cycle`
83			`input ack_i;`
84			`input [31:0] dat_i;`
85			`output stb_o, cyc_o;`
86			`output [15:0] adr_o;`
87			`reg [15:0] adr_o;`
88			`reg stb_o, cyc_o;`
89
90			`//`
91			`// internal buffers adn wires`
92			`//`
93			`// con_buf control buffer`
94			`// con0, con2 contain temporal control information of current address and corrent address+2`
95			`reg [7:0] con_buf [15:0];`
96			`reg [15:0] vaild;`
97			`reg [8:0] con0, con2;`
98			`reg [7:0] cadr0, cadr2;`
99			`reg stb_b;`
100			`reg [1:0] byte_sel;`
101			`reg [1:0] cyc;`
102			`reg [31:0] data1_i;`
103			`reg [15:0] tmp_data1;`
104			`reg wr1, wr1_t, stb_it;`
105
106			`wire [31:0] data0, data1_o;`
107			`wire cy, cy1;`
108			`wire [3:0] adr_i2;`
109			`wire hit, hit_l, hit_h;`
110			`wire [5:0] adr_r, addr1;`
111			`reg [5:0] adr_w;`
112			`reg [15:0] mis_adr;`
113			`wire [15:0] data1;`
114			`wire [1:0] adr_r1;`
115
116			`assign cy = &adr_i[3:1];`
117			`assign {cy1, adr_i2} = {1'b0, adr_i[7:4]}+{4'b0000, cy};`
118			`assign hit_l =(con0=={cadr0,1'b1});`
119			`assign hit_h =(con2=={cadr2,1'b1});`
120			`assign hit = hit_l && hit_h;`
121
122			`assign adr_r = adr_i[7:2] + {5'b00000, adr_i[1]};`
123			`assign addr1 = wr1 ? adr_w : adr_r;`
124			`assign adr_r1 = adr_r[1:0] + 2'b01;`
125			`//assign ack_o = hit;`
126			`assign ack_o = hit && stb_it;`
127
128			`assign data1 = wr1_t ? tmp_data1 : data1_o[31:16];`
129
130			`oc8051_cache_ram oc8051_cache_ram1(.clk(clk), .rst(rst), .addr0(adr_i[7:2]),`
131			`.addr1(addr1), .data0(data0), .data1_o(data1_o), .data1_i(data1_i),`
132			`.wr1(wr1));`
133
134			`always @(stb_b or data0 or data1 or byte_sel)`
135			`begin`
136			`if (stb_b) begin`
137			`case (byte_sel)`
138			`2'b00: dat_o = data0;`
139			`2'b01: dat_o = {data0[23:0], data1[15:8]};`
140			`2'b10: dat_o = {data0[15:0], data1};`
141			`default: dat_o = {data0[7:0], data1, 8'h00};`
142			`endcase`
143			`end else begin`
144			`dat_o = 32'h0;`
145			`end`
146			`end`
147
148			`always @(posedge clk or posedge rst)`
149			`begin`
150			`if (rst) begin`
151			`con0 <= #1 9'h0;`
152			`con2 <= #1 9'h0;`
153			`end else begin`
154			`con0 <= #1 {con_buf[adr_i[7:4]], vaild[adr_i[7:4]]};`
155			`con2 <= #1 {con_buf[adr_i2], vaild[adr_i2]};`
156			`end`
157			`end`
158
159			`always @(posedge clk or posedge rst)`
160			`begin`
161			`if (rst) begin`
162			`cadr0 <= #1 8'h00;`
163			`cadr2 <= #1 8'h00;`
164			`end else begin`
165			`cadr0 <= #1 adr_i[15:8];`
166			`cadr2 <= #1 adr_i[15:8]+{7'h0, cy1};`
167			`end`
168			`end`
169
170			`always @(posedge clk or posedge rst)`
171			`begin`
172			`if (rst) begin`
173			`stb_b <= #1 1'b0;`
174			`byte_sel <= #1 1'b0;`
175			`end else begin`
176			`stb_b <= #1 stb_i;`
177			`byte_sel <= #1 adr_i[1:0];`
178			`end`
179			`end`
180
181			`always @(posedge clk or posedge rst)`
182			`begin`
183			`if (rst) begin`
184			`cyc <= #1 2'b00;`
185			`adr_o <= #1 16'd0;`
186			`cyc_o <= #1 1'b0;`
187			`stb_o <= #1 1'b0;`
188			`data1_i<= #1 32'd0;`
189			`wr1 <= #1 1'b0;`
190			`adr_w <= #1 6'd0;`
191			`vaild <= #1 16'd0;`
192			`end if (stb_b && !hit && !stb_o && !wr1) begin`
193			`cyc <= #1 2'b00;`
194			`adr_o <= #1 {mis_adr[15:4], 4'b0000};`
195			`cyc_o <= #1 1'b1;`
196			`stb_o <= #1 1'b1;`
197			`data1_i<= #1 32'h0;`
198			`wr1 <= #1 1'b0;`
199			`end if (stb_o && ack_i) begin`
200			`data1_i<= #1 dat_i;`
201			`wr1 <= #1 1'b1;`
202			`adr_w <= #1 adr_o[7:2];`
203			`case (cyc)`
204			`2'b00: begin`
205			`cyc <= #1 2'b01;`
206			`adr_o <= #1 {mis_adr[15:4], 4'b0100};`
207			`cyc_o <= #1 1'b1;`
208			`stb_o <= #1 1'b1;`
209			`end`
210			`2'b01: begin`
211			`cyc <= #1 2'b10;`
212			`adr_o <= #1 {mis_adr[15:4], 4'b1000};`
213			`cyc_o <= #1 1'b1;`
214			`stb_o <= #1 1'b1;`
215			`end`
216			`2'b10: begin`
217			`cyc <= #1 2'b11;`
218			`adr_o <= #1 {mis_adr[15:4], 4'b1100};`
219			`cyc_o <= #1 1'b1;`
220			`stb_o <= #1 1'b1;`
221			`end`
222			`default: begin`
223			`cyc <= #1 2'b00;`
224			`adr_o <= #1 {mis_adr[15:4], 4'b0000};`
225			`cyc_o <= #1 1'b0;`
226			`stb_o <= #1 1'b0;`
227			`con_buf[mis_adr[7:4]] <= #1 mis_adr[15:8];`
228			`vaild[mis_adr[7:4]] <= #1 1'b1;`
229			`end`
230			`endcase`
231			`/* end else if (wr1 && (cyc==2'b00)) begin`
232			`vaild[mis_adr[7:4]] <= #1 1'b1;`
233			`wr1 <= #1 1'b0;*/`
234			`end else begin`
235			`adr_o <= #1 {mis_adr[15:4], cyc, 2'b00};`
236			`wr1 <= #1 1'b0;`
237			`end`
238			`end`
239
240			`always @(posedge clk or posedge rst)`
241			`begin`
242			`if (rst)`
243			`mis_adr <= #1 16'h0000;`
244			`else if (!hit_l)`
245			`mis_adr <= #1 adr_i;`
246			`else if (!hit_h)`
247			`mis_adr <= #1 adr_i+{16'd2};`
248			`end`
249
250			`always @(posedge clk or posedge rst)`
251			`begin`
252			`if (rst)`
253			`tmp_data1 <= #1 16'd0;`
254			`else if (!hit_h && wr1 && (cyc==adr_r1))`
255			`tmp_data1 <= #1 dat_i[31:16];`
256			`else if (!hit_l && hit_h && wr1)`
257			`tmp_data1 <= #1 data1_o[31:16];`
258			`end`
259
260			`always @(posedge clk or posedge rst)`
261			`begin`
262			`if (rst) begin`
263			`wr1_t <= #1 1'b0;`
264			`stb_it <= #1 1'b0;`
265			`end else begin`
266			`wr1_t <= #1 wr1;`
267			`stb_it <= #1 stb_i;`
268			`end`
269			`end`
270
271			`endmodule`