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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores interrupt control module                         ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   contains sfr's: tcon, ip, ie;                              ////
////   interrupt handling                                         ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////      - Jaka Simsic, jakas@opencores.org                      ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/06/03 17:12:05  simont
// fix some bugs.
//
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/03/28 17:45:57  simont
// change module name.
//
// Revision 1.6  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.5  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_int (clk, rst,
        wr_addr,
        data_in, bit_in,
        wr, wr_bit,
//timer interrupts
        tf0, tf1, t2_int,
        tr0, tr1,
//external interrupts
        ie0, ie1,
//uart interrupts
        uart_int,
//to cpu
        intr, reti, int_vec, ack,
//registers
        ie, tcon, ip);
 
input [7:0] wr_addr, data_in;
input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;
 
output tr0, tr1, intr;
output [7:0] int_vec,
             ie,
             tcon,
             ip;
 
reg [7:0] ip, ie, int_vec;
 
reg [3:0] tcon_s;
reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;
 
//
// isrc         processing interrupt sources
// int_dept
wire [2:0] isrc_cur;
reg [2:0] isrc [1:0];
reg [1:0] int_dept;
wire [1:0] int_dept_1;
reg int_proc;
reg [1:0] int_lev [1:0];
wire cur_lev;
 
assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;
assign int_dept_1 = int_dept - 2'b01;
assign cur_lev = int_lev[int_dept_1];
 
//
// contains witch level of interrupts is running
//reg [1:0] int_levl, int_levl_w;
 
//
// int_ln       waiting interrupts on level n
// ip_ln        interrupts on level n
// int_src      interrupt sources
wire [5:0] int_l0, int_l1;
wire [5:0] ip_l0, ip_l1;
wire [5:0] int_src;
wire il0, il1;
 
 
reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;
 
//
//interrupt priority
assign ip_l0 = ~ip[5:0];
assign ip_l1 = ip[5:0];
 
assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};
 
//
// waiting interrupts
assign int_l0 = ip_l0 & {ie[5:0]} & int_src;
assign int_l1 = ip_l1 & {ie[5:0]} & int_src;
assign il0 = |int_l0;
assign il1 = |int_l1;
 
//
// TCON
assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};
assign tr0 = tcon_s[2];
assign tr1 = tcon_s[3];
assign intr = |int_vec;
 
 
//
// IP
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ip <=#1 `OC8051_RST_IP;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
   ip <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
   ip[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// IE
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   ie <=#1 `OC8051_RST_IE;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
   ie <= #1 data_in;
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
   ie[wr_addr[2:0]] <= #1 bit_in;
end
 
//
// tcon_s
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_s <=#1 4'b0000;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};
 end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
   case (wr_addr[2:0]) /* synopsys full_case parallel_case */
     3'b000: tcon_s[0] <= #1 bit_in;
     3'b010: tcon_s[1] <= #1 bit_in;
     3'b100: tcon_s[2] <= #1 bit_in;
     3'b110: tcon_s[3] <= #1 bit_in;
   endcase
 end
end
 
//
// tf1 (tmod.7)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf1 <= #1 data_in[7];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
   tcon_tf1 <= #1 bit_in;
 end else if (!(tf1_buff) & (tf1)) begin
   tcon_tf1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
   tcon_tf1 <= #1 1'b0;
 end
end
 
//
// tf0 (tmod.5)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_tf0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_tf0 <= #1 data_in[5];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
   tcon_tf0 <= #1 bit_in;
 end else if (!(tf0_buff) & (tf0)) begin
   tcon_tf0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
   tcon_tf0 <= #1 1'b0;
 end
end
 
 
//
// ie0 (tmod.1)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie0 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie0 <= #1 data_in[1];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
   tcon_ie0 <= #1 bit_in;
 end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) | (!(tcon_s[0]) & !(ie0))) begin
   tcon_ie0 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
   tcon_ie0 <= #1 1'b0;
 end else if (!(tcon_s[0]) & (ie0)) begin
   tcon_ie0 <= #1 1'b0;
 end
end
 
 
//
// ie1 (tmod.3)
//
always @(posedge clk or posedge rst)
begin
 if (rst) begin
   tcon_ie1 <=#1 1'b0;
 end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
   tcon_ie1 <= #1 data_in[3];
 end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
   tcon_ie1 <= #1 bit_in;
 end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) | (!(tcon_s[1]) & !(ie1))) begin
   tcon_ie1 <= #1 1'b1;
 end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
   tcon_ie1 <= #1 1'b0;
 end else if (!(tcon_s[1]) & (ie1)) begin
   tcon_ie1 <= #1 1'b0;
 end
end
 
//
// interrupt processing
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    int_vec <= #1 8'h00;
    int_dept <= #1 2'b0;
    isrc[0] <= #1 3'h0;
    isrc[1] <= #1 3'h0;
    int_proc <= #1 1'b0;
    int_lev[0] <= #1 1'b0;
    int_lev[1] <= #1 1'b0;
  end else if (reti & int_proc) begin  // return from interrupt
   if (int_dept==2'b01)
     int_proc <= #1 1'b0;
   int_dept <= #1 int_dept - 2'b01;
  end else if (((ie[7]) & (!cur_lev) || !int_proc) & il1) begin  // interrupt on level 1
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
   int_dept <= #1 int_dept + 2'b01;
   if (int_l1[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l1[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l1[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l1[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l1[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l1[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 
 end else if ((ie[7]) & !int_proc & il0) begin  // interrupt on level 0
   int_proc <= #1 1'b1;
   int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
   int_dept <= #1 2'b01;
   if (int_l0[0]) begin
     int_vec <= #1 `OC8051_INT_X0;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
   end else if (int_l0[1]) begin
     int_vec <= #1 `OC8051_INT_T0;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
   end else if (int_l0[2]) begin
     int_vec <= #1 `OC8051_INT_X1;
     isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
   end else if (int_l0[3]) begin
     int_vec <= #1 `OC8051_INT_T1;
     isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
   end else if (int_l0[4]) begin
     int_vec <= #1 `OC8051_INT_UART;
     isrc[int_dept] <= #1 `OC8051_ISRC_UART;
   end else if (int_l0[5]) begin
     int_vec <= #1 `OC8051_INT_T2;
     isrc[int_dept] <= #1 `OC8051_ISRC_T2;
   end
 end else begin
   int_vec <= #1 8'h00;
 end
end
 
 
always @(posedge clk or posedge rst)
  if (rst) begin
    tf0_buff <= #1 1'b0;
    tf1_buff <= #1 1'b0;
    ie0_buff <= #1 1'b0;
    ie1_buff <= #1 1'b0;
  end else begin
    tf0_buff <= #1 tf0;
    tf1_buff <= #1 tf1;
    ie0_buff <= #1 ie0;
    ie1_buff <= #1 ie1;
  end
 
endmodule

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores interrupt control module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// contains sfr's: tcon, ip, ie; ////`
10			`//// interrupt handling ////`
11			`//// ////`
12			`//// To Do: ////`
13			`//// Nothing ////`
14			`//// ////`
15			`//// Author(s): ////`
16			`//// - Simon Teran, simont@opencores.org ////`
17			`//// - Jaka Simsic, jakas@opencores.org ////`
18			`//// ////`
19			`//////////////////////////////////////////////////////////////////////`
20			`//// ////`
21			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
22			`//// ////`
23			`//// This source file may be used and distributed without ////`
24			`//// restriction provided that this copyright statement is not ////`
25			`//// removed from the file and that any derivative work contains ////`
26			`//// the original copyright notice and the associated disclaimer. ////`
27			`//// ////`
28			`//// This source file is free software; you can redistribute it ////`
29			`//// and/or modify it under the terms of the GNU Lesser General ////`
30			`//// Public License as published by the Free Software Foundation; ////`
31			`//// either version 2.1 of the License, or (at your option) any ////`
32			`//// later version. ////`
33			`//// ////`
34			`//// This source is distributed in the hope that it will be ////`
35			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
36			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
37			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
38			`//// details. ////`
39			`//// ////`
40			`//// You should have received a copy of the GNU Lesser General ////`
41			`//// Public License along with this source; if not, download it ////`
42			`//// from http://www.opencores.org/lgpl.shtml ////`
43			`//// ////`
44			`//////////////////////////////////////////////////////////////////////`
45			`//`
46			`// CVS Revision History`
47			`//`
48			`// $Log: not supported by cvs2svn $`
49	179	simont	`// Revision 1.9 2003/06/03 17:12:05 simont`
50			`// fix some bugs.`
51			`//`
52	150	simont	`// Revision 1.8 2003/04/07 14:58:02 simont`
53			`// change sfr's interface.`
54			`//`
55	116	simont	`// Revision 1.7 2003/03/28 17:45:57 simont`
56			`// change module name.`
57			`//`
58	90	simont	`// Revision 1.6 2003/01/13 14:14:41 simont`
59			`// replace some modules`
60			`//`
61	82	simont	`// Revision 1.5 2002/09/30 17:33:59 simont`
62			`// prepared header`
63			`//`
64			`//`
65
66
67			`include "oc8051_defines.v"
68
69			`//synopsys translate_off`
70			`include "oc8051_timescale.v"
71			`//synopsys translate_on`
72
73
74
75	116	simont	`module oc8051_int (clk, rst,`
76			`wr_addr,`
77			`data_in, bit_in,`
78			`wr, wr_bit,`
79	82	simont	`//timer interrupts`
80			`tf0, tf1, t2_int,`
81			`tr0, tr1,`
82			`//external interrupts`
83			`ie0, ie1,`
84			`//uart interrupts`
85			`uart_int,`
86			`//to cpu`
87	116	simont	`intr, reti, int_vec, ack,`
88			`//registers`
89			`ie, tcon, ip);`
90	82	simont
91	116	simont	`input [7:0] wr_addr, data_in;`
92	82	simont	`input wr, tf0, tf1, t2_int, ie0, ie1, clk, rst, reti, wr_bit, bit_in, ack, uart_int;`
93
94	116	simont	`output tr0, tr1, intr;`
95			`output [7:0] int_vec,`
96			`ie,`
97			`tcon,`
98			`ip;`
99	82	simont
100	116	simont	`reg [7:0] ip, ie, int_vec;`
101	82	simont
102			`reg [3:0] tcon_s;`
103	116	simont	`reg tcon_tf1, tcon_tf0, tcon_ie1, tcon_ie0;`
104	82	simont
105			`//`
106			`// isrc processing interrupt sources`
107			`// int_dept`
108			`wire [2:0] isrc_cur;`
109			`reg [2:0] isrc [1:0];`
110	150	simont	`reg [1:0] int_dept;`
111			`wire [1:0] int_dept_1;`
112	82	simont	`reg int_proc;`
113			`reg [1:0] int_lev [1:0];`
114			`wire cur_lev;`
115
116			`assign isrc_cur = int_proc ? isrc[int_dept_1] : 2'h0;`
117	150	simont	`assign int_dept_1 = int_dept - 2'b01;`
118	82	simont	`assign cur_lev = int_lev[int_dept_1];`
119
120			`//`
121			`// contains witch level of interrupts is running`
122			`//reg [1:0] int_levl, int_levl_w;`
123
124			`//`
125			`// int_ln waiting interrupts on level n`
126			`// ip_ln interrupts on level n`
127			`// int_src interrupt sources`
128			`wire [5:0] int_l0, int_l1;`
129			`wire [5:0] ip_l0, ip_l1;`
130			`wire [5:0] int_src;`
131			`wire il0, il1;`
132
133
134			`reg tf0_buff, tf1_buff, ie0_buff, ie1_buff;`
135
136			`//`
137			`//interrupt priority`
138			`assign ip_l0 = ~ip[5:0];`
139			`assign ip_l1 = ip[5:0];`
140
141			`assign int_src = {t2_int, uart_int, tcon_tf1, tcon_ie1, tcon_tf0, tcon_ie0};`
142
143			`//`
144			`// waiting interrupts`
145			`assign int_l0 = ip_l0 & {ie[5:0]} & int_src;`
146			`assign int_l1 = ip_l1 & {ie[5:0]} & int_src;`
147			`assign il0 = \|int_l0;`
148			`assign il1 = \|int_l1;`
149
150			`//`
151			`// TCON`
152			`assign tcon = {tcon_tf1, tcon_s[3], tcon_tf0, tcon_s[2], tcon_ie1, tcon_s[1], tcon_ie0, tcon_s[0]};`
153			`assign tr0 = tcon_s[2];`
154			`assign tr1 = tcon_s[3];`
155			`assign intr = \|int_vec;`
156
157
158			`//`
159			`// IP`
160			`always @(posedge clk or posedge rst)`
161			`begin`
162			`if (rst) begin`
163			ip <=#1 `OC8051_RST_IP;
164			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IP)) begin
165			`ip <= #1 data_in;`
166			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IP))
167			`ip[wr_addr[2:0]] <= #1 bit_in;`
168			`end`
169
170			`//`
171			`// IE`
172			`always @(posedge clk or posedge rst)`
173			`begin`
174			`if (rst) begin`
175			ie <=#1 `OC8051_RST_IE;
176			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_IE)) begin
177			`ie <= #1 data_in;`
178			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_IE))
179			`ie[wr_addr[2:0]] <= #1 bit_in;`
180			`end`
181
182			`//`
183			`// tcon_s`
184			`//`
185			`always @(posedge clk or posedge rst)`
186			`begin`
187			`if (rst) begin`
188			`tcon_s <=#1 4'b0000;`
189			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
190			`tcon_s <= #1 {data_in[6], data_in[4], data_in[2], data_in[0]};`
191			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_TCON)) begin
192	179	simont	`case (wr_addr[2:0]) /* synopsys full_case parallel_case */`
193	82	simont	`3'b000: tcon_s[0] <= #1 bit_in;`
194			`3'b010: tcon_s[1] <= #1 bit_in;`
195			`3'b100: tcon_s[2] <= #1 bit_in;`
196			`3'b110: tcon_s[3] <= #1 bit_in;`
197			`endcase`
198			`end`
199			`end`
200
201			`//`
202			`// tf1 (tmod.7)`
203			`//`
204			`always @(posedge clk or posedge rst)`
205			`begin`
206			`if (rst) begin`
207			`tcon_tf1 <=#1 1'b0;`
208			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
209			`tcon_tf1 <= #1 data_in[7];`
210			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b111})) begin
211			`tcon_tf1 <= #1 bit_in;`
212			`end else if (!(tf1_buff) & (tf1)) begin`
213			`tcon_tf1 <= #1 1'b1;`
214			end else if (ack & (isrc_cur==`OC8051_ISRC_TF1)) begin
215			`tcon_tf1 <= #1 1'b0;`
216			`end`
217			`end`
218
219			`//`
220			`// tf0 (tmod.5)`
221			`//`
222			`always @(posedge clk or posedge rst)`
223			`begin`
224			`if (rst) begin`
225			`tcon_tf0 <=#1 1'b0;`
226			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
227			`tcon_tf0 <= #1 data_in[5];`
228			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b101})) begin
229			`tcon_tf0 <= #1 bit_in;`
230			`end else if (!(tf0_buff) & (tf0)) begin`
231			`tcon_tf0 <= #1 1'b1;`
232			end else if (ack & (isrc_cur==`OC8051_ISRC_TF0)) begin
233			`tcon_tf0 <= #1 1'b0;`
234			`end`
235			`end`
236
237
238			`//`
239			`// ie0 (tmod.1)`
240			`//`
241			`always @(posedge clk or posedge rst)`
242			`begin`
243			`if (rst) begin`
244			`tcon_ie0 <=#1 1'b0;`
245			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
246			`tcon_ie0 <= #1 data_in[1];`
247			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b001})) begin
248			`tcon_ie0 <= #1 bit_in;`
249			`end else if (((tcon_s[0]) & (ie0_buff) & !(ie0)) \| (!(tcon_s[0]) & !(ie0))) begin`
250			`tcon_ie0 <= #1 1'b1;`
251			end else if (ack & (isrc_cur==`OC8051_ISRC_IE0) & (tcon_s[0])) begin
252			`tcon_ie0 <= #1 1'b0;`
253			`end else if (!(tcon_s[0]) & (ie0)) begin`
254			`tcon_ie0 <= #1 1'b0;`
255			`end`
256			`end`
257
258
259			`//`
260			`// ie1 (tmod.3)`
261			`//`
262			`always @(posedge clk or posedge rst)`
263			`begin`
264			`if (rst) begin`
265			`tcon_ie1 <=#1 1'b0;`
266			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TCON)) begin
267			`tcon_ie1 <= #1 data_in[3];`
268			end else if ((wr) & (wr_bit) & (wr_addr=={`OC8051_SFR_B_TCON, 3'b011})) begin
269			`tcon_ie1 <= #1 bit_in;`
270			`end else if (((tcon_s[1]) & (ie1_buff) & !(ie1)) \| (!(tcon_s[1]) & !(ie1))) begin`
271			`tcon_ie1 <= #1 1'b1;`
272			end else if (ack & (isrc_cur==`OC8051_ISRC_IE1) & (tcon_s[1])) begin
273			`tcon_ie1 <= #1 1'b0;`
274			`end else if (!(tcon_s[1]) & (ie1)) begin`
275			`tcon_ie1 <= #1 1'b0;`
276			`end`
277			`end`
278
279			`//`
280			`// interrupt processing`
281			`always @(posedge clk or posedge rst)`
282			`begin`
283	150	simont	`if (rst) begin`
284			`int_vec <= #1 8'h00;`
285			`int_dept <= #1 2'b0;`
286			`isrc[0] <= #1 3'h0;`
287			`isrc[1] <= #1 3'h0;`
288			`int_proc <= #1 1'b0;`
289			`int_lev[0] <= #1 1'b0;`
290			`int_lev[1] <= #1 1'b0;`
291			`end else if (reti & int_proc) begin // return from interrupt`
292	82	simont	`if (int_dept==2'b01)`
293			`int_proc <= #1 1'b0;`
294			`int_dept <= #1 int_dept - 2'b01;`
295			`end else if (((ie[7]) & (!cur_lev) \|\| !int_proc) & il1) begin // interrupt on level 1`
296			`int_proc <= #1 1'b1;`
297			int_lev[int_dept] <= #1 `OC8051_ILEV_L1;
298			`int_dept <= #1 int_dept + 2'b01;`
299			`if (int_l1[0]) begin`
300			int_vec <= #1 `OC8051_INT_X0;
301			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
302			`end else if (int_l1[1]) begin`
303			int_vec <= #1 `OC8051_INT_T0;
304			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
305			`end else if (int_l1[2]) begin`
306			int_vec <= #1 `OC8051_INT_X1;
307			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
308			`end else if (int_l1[3]) begin`
309			int_vec <= #1 `OC8051_INT_T1;
310			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
311			`end else if (int_l1[4]) begin`
312			int_vec <= #1 `OC8051_INT_UART;
313			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
314			`end else if (int_l1[5]) begin`
315			int_vec <= #1 `OC8051_INT_T2;
316			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
317			`end`
318
319			`end else if ((ie[7]) & !int_proc & il0) begin // interrupt on level 0`
320			`int_proc <= #1 1'b1;`
321			int_lev[int_dept] <= #1 `OC8051_ILEV_L0;
322	150	simont	`int_dept <= #1 2'b01;`
323	82	simont	`if (int_l0[0]) begin`
324			int_vec <= #1 `OC8051_INT_X0;
325			isrc[int_dept] <= #1 `OC8051_ISRC_IE0;
326			`end else if (int_l0[1]) begin`
327			int_vec <= #1 `OC8051_INT_T0;
328			isrc[int_dept] <= #1 `OC8051_ISRC_TF0;
329			`end else if (int_l0[2]) begin`
330			int_vec <= #1 `OC8051_INT_X1;
331			isrc[int_dept] <= #1 `OC8051_ISRC_IE1;
332			`end else if (int_l0[3]) begin`
333			int_vec <= #1 `OC8051_INT_T1;
334			isrc[int_dept] <= #1 `OC8051_ISRC_TF1;
335			`end else if (int_l0[4]) begin`
336			int_vec <= #1 `OC8051_INT_UART;
337			isrc[int_dept] <= #1 `OC8051_ISRC_UART;
338			`end else if (int_l0[5]) begin`
339			int_vec <= #1 `OC8051_INT_T2;
340			isrc[int_dept] <= #1 `OC8051_ISRC_T2;
341			`end`
342			`end else begin`
343			`int_vec <= #1 8'h00;`
344			`end`
345			`end`
346
347
348			`always @(posedge clk or posedge rst)`
349			`if (rst) begin`
350			`tf0_buff <= #1 1'b0;`
351			`tf1_buff <= #1 1'b0;`
352			`ie0_buff <= #1 1'b0;`
353			`ie1_buff <= #1 1'b0;`
354			`end else begin`
355			`tf0_buff <= #1 tf0;`
356			`tf1_buff <= #1 tf1;`
357			`ie0_buff <= #1 ie0;`
358			`ie1_buff <= #1 ie1;`
359			`end`
360
361			`endmodule`

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_int.v] - Blame information for rev 179