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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 186

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 port output                                            ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   8051 special function registers: port 0:3 - output         ////
////                                                              ////
////  To Do:                                                      ////
////   nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.9  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.8  2003/04/07 14:58:02  simont
// change sfr's interface.
//
// Revision 1.7  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.6  2002/09/30 17:33:59  simont
// prepared header
//
//
 
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
`include "oc8051_defines.v"
 
 
module oc8051_ports (clk,
                    rst,
                    bit_in,
                    data_in,
                    wr,
                    wr_bit,
                    wr_addr,
 
        `ifdef OC8051_PORT0
                    p0_out,
                    p0_in,
                    p0_data,
        `endif
 
        `ifdef OC8051_PORT1
                    p1_out,
                    p1_in,
                    p1_data,
 
        `endif
 
        `ifdef OC8051_PORT2
                    p2_out,
                    p2_in,
                    p2_data,
        `endif
 
        `ifdef OC8051_PORT3
                    p3_out,
                    p3_in,
                    p3_data,
        `endif
 
                    rmw);
 
input        clk,       //clock
             rst,       //reset
             wr,        //write [oc8051_decoder.wr -r]
             wr_bit,    //write bit addresable [oc8051_decoder.bit_addr -r]
             bit_in,    //bit input [oc8051_alu.desCy]
             rmw;       //read modify write feature [oc8051_decoder.rmw]
input [7:0]  wr_addr,    //write address [oc8051_ram_wr_sel.out]
             data_in;   //data input (from alu destiantion 1) [oc8051_alu.des1]
 
`ifdef OC8051_PORT0
  input  [7:0] p0_in;
  output [7:0] p0_out,
               p0_data;
  reg    [7:0] p0_out;
 
  assign p0_data = rmw ? p0_out : p0_in;
`endif
 
 
`ifdef OC8051_PORT1
  input  [7:0] p1_in;
  output [7:0] p1_out,
               p1_data;
  reg    [7:0] p1_out;
 
  assign p1_data = rmw ? p1_out : p1_in;
`endif
 
 
`ifdef OC8051_PORT2
  input  [7:0] p2_in;
  output [7:0] p2_out,
               p2_data;
  reg    [7:0] p2_out;
 
  assign p2_data = rmw ? p2_out : p2_in;
`endif
 
 
`ifdef OC8051_PORT3
  input  [7:0] p3_in;
  output [7:0] p3_out,
               p3_data;
  reg    [7:0] p3_out;
 
  assign p3_data = rmw ? p3_out : p3_in;
`endif
 
//
// case of writing to port
always @(posedge clk or posedge rst)
begin
  if (rst) begin
`ifdef OC8051_PORT0
    p0_out <= #1 `OC8051_RST_P0;
`endif
 
`ifdef OC8051_PORT1
    p1_out <= #1 `OC8051_RST_P1;
`endif
 
`ifdef OC8051_PORT2
    p2_out <= #1 `OC8051_RST_P2;
`endif
 
`ifdef OC8051_PORT3
    p3_out <= #1 `OC8051_RST_P3;
`endif
  end else if (wr) begin
    if (!wr_bit) begin
      case (wr_addr) /* synopsys full_case parallel_case */
//
// bytaddresable
`ifdef OC8051_PORT0
        `OC8051_SFR_P0: p0_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_P1: p1_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_P2: p2_out <= #1 data_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_P3: p3_out <= #1 data_in;
`endif
      endcase
    end else begin
      case (wr_addr[7:3]) /* synopsys full_case parallel_case */
 
//
// bit addressable
`ifdef OC8051_PORT0
        `OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT1
        `OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT2
        `OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
`endif
 
`ifdef OC8051_PORT3
        `OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
`endif
      endcase
    end
  end
end
 
 
endmodule
 

Line No.	Rev	Author	Line
1	82	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 port output ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 special function registers: port 0:3 - output ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47	179	simont	`// Revision 1.9 2003/04/10 12:43:19 simont`
48			`// defines for pherypherals added`
49			`//`
50	120	simont	`// Revision 1.8 2003/04/07 14:58:02 simont`
51			`// change sfr's interface.`
52			`//`
53	116	simont	`// Revision 1.7 2003/01/13 14:14:41 simont`
54			`// replace some modules`
55			`//`
56	82	simont	`// Revision 1.6 2002/09/30 17:33:59 simont`
57			`// prepared header`
58			`//`
59			`//`
60
61
62			`// synopsys translate_off`
63			`include "oc8051_timescale.v"
64			`// synopsys translate_on`
65
66			`include "oc8051_defines.v"
67
68
69	120	simont	`module oc8051_ports (clk,`
70			`rst,`
71			`bit_in,`
72			`data_in,`
73			`wr,`
74			`wr_bit,`
75			`wr_addr,`
76	82	simont
77	120	simont	`ifdef OC8051_PORT0
78			`p0_out,`
79			`p0_in,`
80			`p0_data,`
81			`endif
82	82	simont
83	120	simont	`ifdef OC8051_PORT1
84			`p1_out,`
85			`p1_in,`
86			`p1_data,`
87	82	simont
88	120	simont	`endif
89	82	simont
90	120	simont	`ifdef OC8051_PORT2
91			`p2_out,`
92			`p2_in,`
93			`p2_data,`
94			`endif
95	82	simont
96	120	simont	`ifdef OC8051_PORT3
97			`p3_out,`
98			`p3_in,`
99			`p3_data,`
100			`endif
101	116	simont
102	120	simont	`rmw);`
103
104			`input clk, //clock`
105			`rst, //reset`
106			`wr, //write [oc8051_decoder.wr -r]`
107			`wr_bit, //write bit addresable [oc8051_decoder.bit_addr -r]`
108			`bit_in, //bit input [oc8051_alu.desCy]`
109			`rmw; //read modify write feature [oc8051_decoder.rmw]`
110			`input [7:0] wr_addr, //write address [oc8051_ram_wr_sel.out]`
111			`data_in; //data input (from alu destiantion 1) [oc8051_alu.des1]`
112
113			`ifdef OC8051_PORT0
114			`input [7:0] p0_in;`
115			`output [7:0] p0_out,`
116			`p0_data;`
117			`reg [7:0] p0_out;`
118
119			`assign p0_data = rmw ? p0_out : p0_in;`
120			`endif
121
122
123			`ifdef OC8051_PORT1
124			`input [7:0] p1_in;`
125			`output [7:0] p1_out,`
126			`p1_data;`
127			`reg [7:0] p1_out;`
128
129			`assign p1_data = rmw ? p1_out : p1_in;`
130			`endif
131
132
133			`ifdef OC8051_PORT2
134			`input [7:0] p2_in;`
135			`output [7:0] p2_out,`
136			`p2_data;`
137			`reg [7:0] p2_out;`
138
139			`assign p2_data = rmw ? p2_out : p2_in;`
140			`endif
141
142
143			`ifdef OC8051_PORT3
144			`input [7:0] p3_in;`
145			`output [7:0] p3_out,`
146			`p3_data;`
147			`reg [7:0] p3_out;`
148
149			`assign p3_data = rmw ? p3_out : p3_in;`
150			`endif
151
152	82	simont	`//`
153			`// case of writing to port`
154			`always @(posedge clk or posedge rst)`
155			`begin`
156			`if (rst) begin`
157	120	simont	`ifdef OC8051_PORT0
158	82	simont	p0_out <= #1 `OC8051_RST_P0;
159	120	simont	`endif
160
161			`ifdef OC8051_PORT1
162	82	simont	p1_out <= #1 `OC8051_RST_P1;
163	120	simont	`endif
164
165			`ifdef OC8051_PORT2
166	82	simont	p2_out <= #1 `OC8051_RST_P2;
167	120	simont	`endif
168
169			`ifdef OC8051_PORT3
170	82	simont	p3_out <= #1 `OC8051_RST_P3;
171	120	simont	`endif
172	82	simont	`end else if (wr) begin`
173			`if (!wr_bit) begin`
174	179	simont	`case (wr_addr) /* synopsys full_case parallel_case */`
175	82	simont	`//`
176			`// bytaddresable`
177	120	simont	`ifdef OC8051_PORT0
178	82	simont	`OC8051_SFR_P0: p0_out <= #1 data_in;
179	120	simont	`endif
180
181			`ifdef OC8051_PORT1
182	82	simont	`OC8051_SFR_P1: p1_out <= #1 data_in;
183	120	simont	`endif
184
185			`ifdef OC8051_PORT2
186	82	simont	`OC8051_SFR_P2: p2_out <= #1 data_in;
187	120	simont	`endif
188
189			`ifdef OC8051_PORT3
190	82	simont	`OC8051_SFR_P3: p3_out <= #1 data_in;
191	120	simont	`endif
192	82	simont	`endcase`
193			`end else begin`
194	179	simont	`case (wr_addr[7:3]) /* synopsys full_case parallel_case */`
195	82	simont
196			`//`
197			`// bit addressable`
198	120	simont	`ifdef OC8051_PORT0
199	82	simont	`OC8051_SFR_B_P0: p0_out[wr_addr[2:0]] <= #1 bit_in;
200	120	simont	`endif
201
202			`ifdef OC8051_PORT1
203	82	simont	`OC8051_SFR_B_P1: p1_out[wr_addr[2:0]] <= #1 bit_in;
204	120	simont	`endif
205
206			`ifdef OC8051_PORT2
207	82	simont	`OC8051_SFR_B_P2: p2_out[wr_addr[2:0]] <= #1 bit_in;
208	120	simont	`endif
209
210			`ifdef OC8051_PORT3
211	82	simont	`OC8051_SFR_B_P3: p3_out[wr_addr[2:0]] <= #1 bit_in;
212	120	simont	`endif
213	82	simont	`endcase`
214			`end`
215			`end`
216			`end`
217
218
219			`endmodule`
220

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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_ports.v] - Blame information for rev 186