OpenCores
URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_psw.v] - Blame information for rev 186

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 76 simont
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  8051 program status word                                    ////
4
////                                                              ////
5
////  This file is part of the 8051 cores project                 ////
6
////  http://www.opencores.org/cores/8051/                        ////
7
////                                                              ////
8
////  Description                                                 ////
9
////   program status word                                        ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   nothing                                                    ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Simon Teran, simont@opencores.org                     ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43
//
44
// CVS Revision History
45
//
46
// $Log: not supported by cvs2svn $
47 179 simont
// Revision 1.11  2003/04/09 15:49:42  simont
48
// Register oc8051_sfr dato output, add signal wait_data.
49
//
50 117 simont
// Revision 1.10  2003/04/07 14:58:02  simont
51
// change sfr's interface.
52
//
53 116 simont
// Revision 1.9  2003/01/13 14:14:41  simont
54
// replace some modules
55
//
56 82 simont
// Revision 1.8  2002/11/05 17:23:54  simont
57
// add module oc8051_sfr, 256 bytes internal ram
58
//
59 76 simont
// Revision 1.7  2002/09/30 17:33:59  simont
60
// prepared header
61
//
62
//
63
 
64
 
65
// synopsys translate_off
66
`include "oc8051_timescale.v"
67
// synopsys translate_on
68
 
69
`include "oc8051_defines.v"
70
 
71
 
72 116 simont
module oc8051_psw (clk, rst, wr_addr, data_in, wr, wr_bit, data_out, p,
73 82 simont
                cy_in, ac_in, ov_in, set, bank_sel);
74 76 simont
//
75
// clk          (in)  clock
76
// rst          (in)  reset
77
// addr         (in)  write address [oc8051_ram_wr_sel.out]
78
// data_in      (in)  data input [oc8051_alu.des1]
79
// wr           (in)  write [oc8051_decoder.wr -r]
80
// wr_bit       (in)  write bit addresable [oc8051_decoder.bit_addr -r]
81
// p            (in)  parity [oc8051_acc.p]
82
// cy_in        (in)  input bit data [oc8051_alu.desCy]
83
// ac_in        (in)  auxiliary carry input [oc8051_alu.desAc]
84
// ov_in        (in)  overflov input [oc8051_alu.desOv]
85
// set          (in)  set psw (write to caryy, carry and overflov or carry, owerflov and ac) [oc8051_decoder.psw_set -r]
86
//
87
 
88
 
89
input clk, rst, wr, p, cy_in, ac_in, ov_in, wr_bit;
90
input [1:0] set;
91
input [7:0] wr_addr, data_in;
92
 
93
output [1:0] bank_sel;
94
output [7:0] data_out;
95
 
96 117 simont
reg [7:1] data;
97 76 simont
wire wr_psw;
98
 
99
assign wr_psw = (wr & (wr_addr==`OC8051_SFR_PSW) && !wr_bit);
100
 
101
assign bank_sel = wr_psw ? data_in[4:3]:data[4:3];
102 117 simont
assign data_out = {data[7:1], p};
103 76 simont
 
104
//
105
//case writing to psw
106
always @(posedge clk or posedge rst)
107
begin
108
  if (rst)
109
    data <= #1 `OC8051_RST_PSW;
110
 
111
//
112
// write to psw (byte addressable)
113
  else begin
114
    if (wr & (wr_bit==1'b0) & (wr_addr==`OC8051_SFR_PSW))
115
      data[7:1] <= #1 data_in[7:1];
116
//
117
// write to psw (bit addressable)
118
    else if (wr & wr_bit & (wr_addr[7:3]==`OC8051_SFR_B_PSW))
119
      data[wr_addr[2:0]] <= #1 cy_in;
120
    else begin
121 179 simont
      case (set) /* synopsys full_case parallel_case */
122 76 simont
        `OC8051_PS_CY: begin
123
//
124
//write carry
125
          data[7] <= #1 cy_in;
126
        end
127
        `OC8051_PS_OV: begin
128
//
129
//write carry and overflov
130
          data[7] <= #1 cy_in;
131
          data[2] <= #1 ov_in;
132
        end
133
        `OC8051_PS_AC:begin
134
//
135
//write carry, overflov and ac
136
          data[7] <= #1 cy_in;
137
          data[6] <= #1 ac_in;
138
          data[2] <= #1 ov_in;
139
 
140
        end
141
      endcase
142
    end
143
  end
144
end
145
 
146
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.