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[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc2.v] - Blame information for rev 116

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1 81 simont 
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  8051 cores timer/counter2 control                           ////
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////                                                              ////
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////  This file is part of the 8051 cores project                 ////
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////  http://www.opencores.org/cores/8051/                        ////
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////                                                              ////
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////  Description                                                 ////
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////   timers and counters 2 8051 core                            ////
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////                                                              ////
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////  To Do:                                                      ////
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////   Nothing                                                    ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Simon Teran, simont@opencores.org                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
47 116 simont 
// Revision 1.2  2003/04/04 10:34:13  simont
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// change timers to meet timing specifications (add divider with 12)
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//
50 112 simont 
// Revision 1.1  2003/01/13 14:13:12  simont
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// initial import
52 81 simont 
//
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//
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//
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`include "oc8051_defines.v"
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//synopsys translate_off
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`include "oc8051_timescale.v"
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//synopsys translate_on
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64 116 simont 
module oc8051_tc2 (clk, rst,
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            wr_addr,
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            data_in, bit_in,
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            wr, wr_bit,
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            t2, t2ex,
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            rclk, tclk,
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            brate2, tc2_int,
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            pres_ow,
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//registers
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            t2con, tl2, th2, rcap2l, rcap2h);
74 81 simont 
 
75 112 simont 
input [7:0]  wr_addr,
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             data_in;
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input        clk,
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             rst,
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             wr,
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             wr_bit,
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             t2,
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             t2ex,
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             bit_in,
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             pres_ow;   //prescalre owerflov
85 116 simont 
output [7:0] t2con,
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             tl2,
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             th2,
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             rcap2l,
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             rcap2h;
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output       tc2_int,
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             rclk,
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             tclk,
93 112 simont 
             brate2;
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95 81 simont 
 
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reg brate2;
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reg [7:0] t2con, tl2, th2, rcap2l, rcap2h;
98 81 simont 
 
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reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
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wire run;
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//
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// t2con
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wire tf2, exf2, exen2, tr2, ct2, cprl2;
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assign tc2_int = tf2 | exf2;
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assign tf2   = t2con[7];
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assign exf2  = t2con[6];
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assign rclk  = t2con[5];
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assign tclk  = t2con[4];
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assign exen2 = t2con[3];
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assign tr2   = t2con[2];
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assign ct2   = t2con[1];
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assign cprl2 = t2con[0];
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    t2con <= #1 `OC8051_RST_T2CON;
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
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    t2con <= #1 data_in;
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  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
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    t2con[wr_addr[2:0]] <= #1 bit_in;
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  end else if (tf2_set) begin
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    t2con[7] <= #1 1'b1;
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  end else if (exen2 & neg_trans) begin
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    t2con[6] <= #1 1'b1;
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  end
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end
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//
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//th2, tl2
135 112 simont 
assign run = tr2 & ((!ct2 & pres_ow) | (ct2 & tc2_event));
136 81 simont 
 
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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//
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// reset
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//
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    tl2 <= #1 `OC8051_RST_TL2;
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    th2 <= #1 `OC8051_RST_TH2;
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    brate2 <= #1 1'b0;
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    tf2_set <= #1 1'b0;
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
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//
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// write to timer 2 high
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//
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    th2 <= #1 data_in;
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
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//
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// write to timer 2 low
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//
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    tl2 <= #1 data_in;
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  end else if (!(rclk | tclk) & !cprl2 & exen2 & neg_trans) begin
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//
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// avto reload mode, exen2=1, 0-1 transition on t2ex pin
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//
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    th2 <= #1 rcap2h;
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    tl2 <= #1 rcap2l;
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    tf2_set <= #1 1'b0;
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  end else if (run) begin
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    if (rclk | tclk) begin
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//
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// boud rate generator mode
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//
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      if (&{th2, tl2}) begin
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        th2 <= #1 rcap2h;
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        tl2 <= #1 rcap2l;
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        brate2 <= #1 1'b1;
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      end else begin
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        {brate2, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
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      end
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      tf2_set <= #1 1'b0;
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    end else if (cprl2) begin
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//
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// capture mode
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//
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      {tf2_set, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
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    end else begin
183 81 simont 
//
184 112 simont 
// auto reload mode
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//
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      if (&{th2, tl2}) begin
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        th2 <= #1 rcap2h;
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        tl2 <= #1 rcap2l;
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        tf2_set <= #1 1'b1;
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      end else begin
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        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
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      end
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    end
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  end else tf2_set <= #1 1'b0;
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end
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//
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// rcap2l, rcap2h
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    rcap2l <= #1 `OC8051_RST_RCAP2L;
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    rcap2h <= #1 `OC8051_RST_RCAP2H;
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
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    rcap2h <= #1 data_in;
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  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
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    rcap2l <= #1 data_in;
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  end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
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    rcap2l <= #1 tl2;
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    rcap2h <= #1 th2;
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  end
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end
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//
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//
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    neg_trans <= #1 1'b0;
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    t2ex_r <= #1 1'b0;
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  end else if (t2ex) begin
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    neg_trans <= #1 1'b0;
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    t2ex_r <= #1 1'b1;
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  end else if (t2ex_r) begin
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    neg_trans <= #1 1'b1;
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    t2ex_r <= #1 1'b0;
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  end else begin
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    neg_trans <= #1 1'b0;
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    t2ex_r <= #1 t2ex_r;
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  end
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end
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//
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//
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always @(posedge clk or posedge rst)
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begin
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  if (rst) begin
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    tc2_event <= #1 1'b0;
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    t2_r <= #1 1'b0;
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  end else if (t2) begin
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    tc2_event <= #1 1'b0;
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    t2_r <= #1 1'b1;
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  end else if (!t2 & t2_r) begin
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    tc2_event <= #1 1'b1;
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    t2_r <= #1 1'b0;
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  end else begin
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    tc2_event <= #1 1'b0;
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  end
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end
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endmodule

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