URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc2.v] - Blame information for rev 81

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores timer/counter2 control                           ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////   timers and counters 2 8051 core                            ////
////                                                              ////
////  To Do:                                                      ////
////   Nothing                                                    ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
 
`include "oc8051_defines.v"
 
//synopsys translate_off
`include "oc8051_timescale.v"
//synopsys translate_on
 
 
 
module oc8051_tc2 (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, bit_in, t2, t2ex, data_out, bit_out,
            rclk, tclk, brate2, tc2_int);
 
input [7:0] wr_addr, data_in, rd_addr;
input clk, rst, wr, wr_bit, t2, t2ex, bit_in;
output [7:0] data_out;
output tc2_int, bit_out, rclk, tclk, brate2;
reg [7:0] data_out;
 
reg brate2;
reg [7:0] t2con, t2mod, tl2, th2, rcap2l, rcap2h;
 
reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;
 
wire run;
 
wire dcen;
assign dcen = t2mod[0];
 
//
// t2con
wire tf2, exf2, exen2, tr2, ct2, cprl2;
 
assign tc2_int = tf2 | exf2;
assign tf2   = t2con[7];
assign exf2  = t2con[6];
assign rclk  = t2con[5];
assign tclk  = t2con[4];
assign exen2 = t2con[3];
assign tr2   = t2con[2];
assign ct2   = t2con[1];
assign cprl2 = t2con[0];
 
assign bit_out = t2con[rd_addr[2:0]];
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    t2con <= #1 `OC8051_RST_T2CON;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
    t2con <= #1 data_in;
  end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
    t2con[wr_addr[2:0]] <= #1 bit_in;
  end else if (tf2_set) begin
    t2con[7] <= #1 1'b1;
//auto reload mode, dcen=1 : toggle exf2;
    if (!(rclk | tclk) & !cprl2 & dcen)
      t2con[6] <= #1 !t2con[6];
  end else if (exen2 & (rclk | tclk | cprl2 | !dcen) & neg_trans) begin
    t2con <= #1 {t2con[7], 1'b1, t2con[5:0]};
  end
end
 
 
//
// t2mod
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    t2mod <= #1 `OC8051_RST_T2MOD;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2MOD)) begin
    t2mod <= #1 data_in;
  end
end
 
//
//th2, tl2
assign run = tr2 & (!ct2 | (ct2 & tc2_event));
 
always @(posedge clk or posedge rst)
begin
  if (rst) begin
//
// reset
//
    tl2 <= #1 `OC8051_RST_TL2;
    th2 <= #1 `OC8051_RST_TH2;
    brate2 <= #1 1'b0;
    tf2_set <= #1 1'b0;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
//
// write to timer 2 high
//
    th2 <= #1 data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
//
// write to timer 2 low
//
    tl2 <= #1 data_in;
  end else if (!(rclk | tclk) & !cprl2 & exen2 & !dcen) begin
//
// avto reload mode, exen2=1, 0-1 transition on t2ex pin
//
    th2 <= #1 rcap2h;
    tl2 <= #1 rcap2l;
    tf2_set <= #1 1'b0;
  end else if (run) begin
    if (rclk | tclk) begin
//
// boud rate generator mode
//
      if (&{th2, tl2}) begin
        th2 <= #1 rcap2h;
        tl2 <= #1 rcap2l;
        brate2 <= #1 1'b1;
      end else begin
        {brate2, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
      end
      tf2_set <= #1 1'b0;
    end else if (cprl2) begin
//
// capture mode
//
      {tf2_set, th2, tl2}  <= #1 {1'b0, th2, tl2} + 17'h1;
    end else if (!dcen | t2ex) begin
//
// auto reload mode, up counter
//
      if (&{th2, tl2}) begin
        th2 <= #1 rcap2h;
        tl2 <= #1 rcap2l;
        tf2_set <= #1 1'b1;
      end else begin
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;
      end
    end else begin
//
// auto reload mode, down counter
//
      if ({th2, tl2}=={rcap2h, rcap2l}) begin
        th2 <= #1 8'hff;
        tl2 <= #1 8'hff;
        tf2_set <= #1 1'b1;
      end else begin
        {tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} - 17'h1;
      end
    end
  end else tf2_set <= #1 1'b0;
end
 
 
//
// rcap2l, rcap2h
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    rcap2l <= #1 `OC8051_RST_RCAP2L;
    rcap2h <= #1 `OC8051_RST_RCAP2H;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
    rcap2h <= #1 data_in;
  end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
    rcap2l <= #1 data_in;
  end else if (!(rclk | tclk) & exen2 & cprl2 & neg_trans) begin
    rcap2l <= #1 tl2;
    rcap2h <= #1 th2;
  end
end
 
 
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 1'b0;
  end else if (t2ex) begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 1'b1;
  end else if (t2ex_r) begin
    neg_trans <= #1 1'b1;
    t2ex_r <= #1 1'b0;
  end else begin
    neg_trans <= #1 1'b0;
    t2ex_r <= #1 t2ex_r;
  end
end
 
//
//
always @(posedge clk or posedge rst)
begin
  if (rst) begin
    tc2_event <= #1 1'b0;
    t2_r <= #1 1'b0;
  end else if (t2) begin
    tc2_event <= #1 1'b0;
    t2_r <= #1 1'b1;
  end else if (!t2 & t2_r) begin
//  end if (t2_r) begin
    tc2_event <= #1 1'b1;
    t2_r <= #1 1'b0;
  end else begin
    tc2_event <= #1 1'b0;
  end
end
 
always @(rd_addr or t2con or t2mod or tl2 or th2 or rcap2l or rcap2h)
begin
  case (rd_addr)
    `OC8051_SFR_RCAP2H: data_out = rcap2h;
    `OC8051_SFR_RCAP2L: data_out = rcap2l;
    `OC8051_SFR_TH2:    data_out = th2;
    `OC8051_SFR_TL2:    data_out = tl2;
    `OC8051_SFR_T2MOD:  data_out = t2mod;
    default:            data_out = t2con;
  endcase
 
end
 
endmodule

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_tc2.v] - Blame information for rev 81

Line No.	Rev	Author	Line
1	81	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores timer/counter2 control ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// timers and counters 2 8051 core ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// Nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46			`// $Log: not supported by cvs2svn $`
47			`//`
48			`//`
49
50			`include "oc8051_defines.v"
51
52			`//synopsys translate_off`
53			`include "oc8051_timescale.v"
54			`//synopsys translate_on`
55
56
57
58			`module oc8051_tc2 (clk, rst, wr_addr, rd_addr, data_in, wr, wr_bit, bit_in, t2, t2ex, data_out, bit_out,`
59			`rclk, tclk, brate2, tc2_int);`
60
61			`input [7:0] wr_addr, data_in, rd_addr;`
62			`input clk, rst, wr, wr_bit, t2, t2ex, bit_in;`
63			`output [7:0] data_out;`
64			`output tc2_int, bit_out, rclk, tclk, brate2;`
65			`reg [7:0] data_out;`
66
67			`reg brate2;`
68			`reg [7:0] t2con, t2mod, tl2, th2, rcap2l, rcap2h;`
69
70			`reg neg_trans, t2ex_r, t2_r, tc2_event, tf2_set;`
71
72			`wire run;`
73
74			`wire dcen;`
75			`assign dcen = t2mod[0];`
76
77			`//`
78			`// t2con`
79			`wire tf2, exf2, exen2, tr2, ct2, cprl2;`
80
81			`assign tc2_int = tf2 \| exf2;`
82			`assign tf2 = t2con[7];`
83			`assign exf2 = t2con[6];`
84			`assign rclk = t2con[5];`
85			`assign tclk = t2con[4];`
86			`assign exen2 = t2con[3];`
87			`assign tr2 = t2con[2];`
88			`assign ct2 = t2con[1];`
89			`assign cprl2 = t2con[0];`
90
91			`assign bit_out = t2con[rd_addr[2:0]];`
92
93			`always @(posedge clk or posedge rst)`
94			`begin`
95			`if (rst) begin`
96			t2con <= #1 `OC8051_RST_T2CON;
97			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2CON)) begin
98			`t2con <= #1 data_in;`
99			end else if ((wr) & (wr_bit) & (wr_addr[7:3]==`OC8051_SFR_B_T2CON)) begin
100			`t2con[wr_addr[2:0]] <= #1 bit_in;`
101			`end else if (tf2_set) begin`
102			`t2con[7] <= #1 1'b1;`
103			`//auto reload mode, dcen=1 : toggle exf2;`
104			`if (!(rclk \| tclk) & !cprl2 & dcen)`
105			`t2con[6] <= #1 !t2con[6];`
106			`end else if (exen2 & (rclk \| tclk \| cprl2 \| !dcen) & neg_trans) begin`
107			`t2con <= #1 {t2con[7], 1'b1, t2con[5:0]};`
108			`end`
109			`end`
110
111
112			`//`
113			`// t2mod`
114
115			`always @(posedge clk or posedge rst)`
116			`begin`
117			`if (rst) begin`
118			t2mod <= #1 `OC8051_RST_T2MOD;
119			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_T2MOD)) begin
120			`t2mod <= #1 data_in;`
121			`end`
122			`end`
123
124			`//`
125			`//th2, tl2`
126			`assign run = tr2 & (!ct2 \| (ct2 & tc2_event));`
127
128			`always @(posedge clk or posedge rst)`
129			`begin`
130			`if (rst) begin`
131			`//`
132			`// reset`
133			`//`
134			tl2 <= #1 `OC8051_RST_TL2;
135			th2 <= #1 `OC8051_RST_TH2;
136			`brate2 <= #1 1'b0;`
137			`tf2_set <= #1 1'b0;`
138			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TH2)) begin
139			`//`
140			`// write to timer 2 high`
141			`//`
142			`th2 <= #1 data_in;`
143			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_TL2)) begin
144			`//`
145			`// write to timer 2 low`
146			`//`
147			`tl2 <= #1 data_in;`
148			`end else if (!(rclk \| tclk) & !cprl2 & exen2 & !dcen) begin`
149			`//`
150			`// avto reload mode, exen2=1, 0-1 transition on t2ex pin`
151			`//`
152			`th2 <= #1 rcap2h;`
153			`tl2 <= #1 rcap2l;`
154			`tf2_set <= #1 1'b0;`
155			`end else if (run) begin`
156			`if (rclk \| tclk) begin`
157			`//`
158			`// boud rate generator mode`
159			`//`
160			`if (&{th2, tl2}) begin`
161			`th2 <= #1 rcap2h;`
162			`tl2 <= #1 rcap2l;`
163			`brate2 <= #1 1'b1;`
164			`end else begin`
165			`{brate2, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
166			`end`
167			`tf2_set <= #1 1'b0;`
168			`end else if (cprl2) begin`
169			`//`
170			`// capture mode`
171			`//`
172			`{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
173			`end else if (!dcen \| t2ex) begin`
174			`//`
175			`// auto reload mode, up counter`
176			`//`
177			`if (&{th2, tl2}) begin`
178			`th2 <= #1 rcap2h;`
179			`tl2 <= #1 rcap2l;`
180			`tf2_set <= #1 1'b1;`
181			`end else begin`
182			`{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} + 17'h1;`
183			`end`
184			`end else begin`
185			`//`
186			`// auto reload mode, down counter`
187			`//`
188			`if ({th2, tl2}=={rcap2h, rcap2l}) begin`
189			`th2 <= #1 8'hff;`
190			`tl2 <= #1 8'hff;`
191			`tf2_set <= #1 1'b1;`
192			`end else begin`
193			`{tf2_set, th2, tl2} <= #1 {1'b0, th2, tl2} - 17'h1;`
194			`end`
195			`end`
196			`end else tf2_set <= #1 1'b0;`
197			`end`
198
199
200			`//`
201			`// rcap2l, rcap2h`
202			`always @(posedge clk or posedge rst)`
203			`begin`
204			`if (rst) begin`
205			rcap2l <= #1 `OC8051_RST_RCAP2L;
206			rcap2h <= #1 `OC8051_RST_RCAP2H;
207			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2H)) begin
208			`rcap2h <= #1 data_in;`
209			end else if ((wr) & !(wr_bit) & (wr_addr==`OC8051_SFR_RCAP2L)) begin
210			`rcap2l <= #1 data_in;`
211			`end else if (!(rclk \| tclk) & exen2 & cprl2 & neg_trans) begin`
212			`rcap2l <= #1 tl2;`
213			`rcap2h <= #1 th2;`
214			`end`
215			`end`
216
217
218			`//`
219			`//`
220			`always @(posedge clk or posedge rst)`
221			`begin`
222			`if (rst) begin`
223			`neg_trans <= #1 1'b0;`
224			`t2ex_r <= #1 1'b0;`
225			`end else if (t2ex) begin`
226			`neg_trans <= #1 1'b0;`
227			`t2ex_r <= #1 1'b1;`
228			`end else if (t2ex_r) begin`
229			`neg_trans <= #1 1'b1;`
230			`t2ex_r <= #1 1'b0;`
231			`end else begin`
232			`neg_trans <= #1 1'b0;`
233			`t2ex_r <= #1 t2ex_r;`
234			`end`
235			`end`
236
237			`//`
238			`//`
239			`always @(posedge clk or posedge rst)`
240			`begin`
241			`if (rst) begin`
242			`tc2_event <= #1 1'b0;`
243			`t2_r <= #1 1'b0;`
244			`end else if (t2) begin`
245			`tc2_event <= #1 1'b0;`
246			`t2_r <= #1 1'b1;`
247			`end else if (!t2 & t2_r) begin`
248			`// end if (t2_r) begin`
249			`tc2_event <= #1 1'b1;`
250			`t2_r <= #1 1'b0;`
251			`end else begin`
252			`tc2_event <= #1 1'b0;`
253			`end`
254			`end`
255
256			`always @(rd_addr or t2con or t2mod or tl2 or th2 or rcap2l or rcap2h)`
257			`begin`
258			`case (rd_addr)`
259			`OC8051_SFR_RCAP2H: data_out = rcap2h;
260			`OC8051_SFR_RCAP2L: data_out = rcap2l;
261			`OC8051_SFR_TH2: data_out = th2;
262			`OC8051_SFR_TL2: data_out = tl2;
263			`OC8051_SFR_T2MOD: data_out = t2mod;
264			`default: data_out = t2con;`
265			`endcase`
266
267			`end`
268
269			`endmodule`