URL https://opencores.org/ocsvn/8051/8051/trunk

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Blame information for rev 144

Go to most recent revision | Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  8051 cores top level module                                 ////
////                                                              ////
////  This file is part of the 8051 cores project                 ////
////  http://www.opencores.org/cores/8051/                        ////
////                                                              ////
////  Description                                                 ////
////  8051 definitions.                                           ////
////                                                              ////
////  To Do:                                                      ////
////    nothing                                                   ////
////                                                              ////
////  Author(s):                                                  ////
////      - Simon Teran, simont@opencores.org                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.28  2003/05/06 09:41:35  simont
// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.
//
// Revision 1.27  2003/05/05 15:46:37  simont
// add aditional alu destination to solve critical path.
//
// Revision 1.26  2003/04/29 11:24:31  simont
// fix bug in case execution of two data dependent instructions.
//
// Revision 1.25  2003/04/25 17:15:51  simont
// change branch instruction execution (reduse needed clock periods).
//
// Revision 1.24  2003/04/11 10:05:59  simont
// deifne OC8051_ROM added
//
// Revision 1.23  2003/04/10 12:43:19  simont
// defines for pherypherals added
//
// Revision 1.22  2003/04/09 16:24:04  simont
// change wr_sft to 2 bit wire.
//
// Revision 1.21  2003/04/09 15:49:42  simont
// Register oc8051_sfr dato output, add signal wait_data.
//
// Revision 1.20  2003/04/03 19:13:28  simont
// Include instruction cache.
//
// Revision 1.19  2003/04/02 15:08:30  simont
// raname signals.
//
// Revision 1.18  2003/01/13 14:14:41  simont
// replace some modules
//
// Revision 1.17  2002/11/05 17:23:54  simont
// add module oc8051_sfr, 256 bytes internal ram
//
// Revision 1.16  2002/10/28 14:55:00  simont
// fix bug in interface to external data ram
//
// Revision 1.15  2002/10/23 16:53:39  simont
// fix bugs in instruction interface
//
// Revision 1.14  2002/10/17 18:50:00  simont
// cahnge interface to instruction rom
//
// Revision 1.13  2002/09/30 17:33:59  simont
// prepared header
//
//
 
// synopsys translate_off
`include "oc8051_timescale.v"
// synopsys translate_on
 
 
module oc8051_top (wb_rst_i, wb_clk_i,
//interface to instruction rom
                wbi_adr_o,
                wbi_dat_i,
                wbi_stb_o,
                wbi_ack_i,
                wbi_cyc_o,
                wbi_err_i,
 
//interface to data ram
                wbd_dat_i,
                wbd_dat_o,
                wbd_adr_o,
                wbd_we_o,
                wbd_ack_i,
                wbd_stb_o,
                wbd_cyc_o,
                wbd_err_i,
 
// interrupt interface
                int0_i,
                int1_i,
 
// external access (active low)
                ea_in,
 
// port interface
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                p0_i,
                p0_o,
        `endif
 
        `ifdef OC8051_PORT1
                p1_i,
                p1_o,
        `endif
 
        `ifdef OC8051_PORT2
                p2_i,
                p2_o,
        `endif
 
        `ifdef OC8051_PORT3
                p3_i,
                p3_o,
        `endif
  `endif
 
// serial interface
        `ifdef OC8051_UART
                rxd_i, txd_o,
        `endif
 
// counter interface
        `ifdef OC8051_TC01
                t0_i, t1_i,
        `endif
 
        `ifdef OC8051_TC2
                t2_i, t2ex_i
        `endif
                );
 
 
 
input         wb_rst_i,         // reset input
              wb_clk_i,         // clock input
              int0_i,           // interrupt 0
              int1_i,           // interrupt 1
              ea_in,            // external access
              wbd_ack_i,        // data acknowalge
              wbi_ack_i,        // instruction acknowlage
              wbd_err_i,        // data error
              wbi_err_i;        // instruction error
 
input [7:0]   wbd_dat_i; // ram data input
input [31:0]  wbi_dat_i; // rom data input
 
output        wbd_we_o,         // data write enable
              wbd_stb_o,        // data strobe
              wbd_cyc_o,        // data cycle
              wbi_stb_o,        // instruction strobe
              wbi_cyc_o;        // instruction cycle
 
output [7:0]  wbd_dat_o; // data output
 
output [15:0] wbd_adr_o, // data address
              wbi_adr_o;        // instruction address
 
`ifdef OC8051_PORTS
 
`ifdef OC8051_PORT0
input  [7:0]  p0_i;              // port 0 input
output [7:0]  p0_o;              // port 0 output
`endif
 
`ifdef OC8051_PORT1
input  [7:0]  p1_i;              // port 1 input
output [7:0]  p1_o;              // port 1 output
`endif
 
`ifdef OC8051_PORT2
input  [7:0]  p2_i;              // port 2 input
output [7:0]  p2_o;              // port 2 output
`endif
 
`ifdef OC8051_PORT3
input  [7:0]  p3_i;              // port 3 input
output [7:0]  p3_o;              // port 3 output
`endif
 
`endif
 
 
 
 
 
 
`ifdef OC8051_UART
input         rxd_i;            // receive
output        txd_o;            // transnmit
`endif
 
`ifdef OC8051_TC01
input         t0_i,             // counter 0 input
              t1_i;             // counter 1 input
`endif
 
`ifdef OC8051_TC2
input         t2_i,             // counter 2 input
              t2ex_i;           //
`endif
 
wire [7:0]  op1_i,
            op2_i,
            op3_i,
            dptr_hi,
            dptr_lo,
            ri,
            data_out,
            op1,
            op2,
            op3,
            acc,
            p0_out,
            p1_out,
            p2_out,
            p3_out,
            sp,
            sp_w;
 
wire [15:0] pc;
 
assign wbd_cyc_o = wbd_stb_o;
 
wire        src_sel3;
wire [1:0]  wr_sfr,
            src_sel2;
wire [2:0]  ram_rd_sel,  // ram read
            ram_wr_sel, // ram write
            src_sel1;
 
wire [7:0]  ram_data,
            ram_out,    //data from ram
            sfr_out,
            wr_dat,
            wr_addr,    //ram write addres
            rd_addr;    //data ram read addres
wire        sfr_bit;
 
wire [1:0]  cy_sel,      //carry select; from decoder to cy_selct1
            bank_sel;
wire        rom_addr_sel,       //rom addres select; alu or pc
            rmw,
            ea_int;
 
wire        reti,
            intr,
            int_ack,
            istb;
wire [7:0]  int_src;
 
wire        mem_wait;
wire [2:0]  mem_act;
wire [3:0]  alu_op;      //alu operation (from decoder)
wire [1:0]  psw_set;    //write to psw or not; from decoder to psw (through register)
 
wire [7:0]  src1,        //alu sources 1
            src2,       //alu sources 2
            src3,       //alu sources 3
            des_acc,
            des1,       //alu destination 1
            des2;       //alu destinations 2
wire        desCy,      //carry out
            desAc,
            desOv,      //overflow
            alu_cy,
            wr,         //write to data ram
            wr_o;
 
wire        rd,         //read program rom
            pc_wr;
wire [2:0]  pc_wr_sel;   //program counter write select (from decoder to pc)
 
wire [7:0]  op1_n, //from memory_interface to decoder
            op2_n,
            op3_n;
 
wire [1:0]  comp_sel;    //select source1 and source2 to compare
wire        eq,         //result (from comp1 to decoder)
            srcAc,
            cy,
            rd_ind,
            wr_ind,
            comp_wait;
wire [2:0]  op1_cur;
 
wire        bit_addr,   //bit addresable instruction
            bit_data,   //bit data from ram to ram_select
            bit_out,    //bit data from ram_select to alu and cy_select
            bit_addr_o,
            wait_data;
 
//
// cpu to cache/wb_interface
wire        iack_i,
            istb_o,
            icyc_o;
wire [31:0] idat_i;
wire [15:0] iadr_o;
 
 
//
// decoder
oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),
                               .rst(wb_rst_i),
                               .op_in(op1_n),
                               .op1_c(op1_cur),
                               .ram_rd_sel_o(ram_rd_sel),
                               .ram_wr_sel_o(ram_wr_sel),
                               .bit_addr(bit_addr),
 
                               .src_sel1(src_sel1),
                               .src_sel2(src_sel2),
                               .src_sel3(src_sel3),
 
                               .alu_op_o(alu_op),
                               .psw_set(psw_set),
                               .cy_sel(cy_sel),
                               .wr_o(wr),
                               .pc_wr(pc_wr),
                               .pc_sel(pc_wr_sel),
                               .comp_sel(comp_sel),
                               .eq(eq),
                               .wr_sfr_o(wr_sfr),
                               .rd(rd),
                               .rmw(rmw),
                               .istb(istb),
                               .mem_act(mem_act),
                               .mem_wait(mem_wait),
                               .wait_data(wait_data));
 
 
//
//alu
oc8051_alu oc8051_alu1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .op_code(alu_op),
                       .src1(src1),
                       .src2(src2),
                       .src3(src3),
                       .srcCy(alu_cy),
                       .srcAc(srcAc),
                       .des_acc(des_acc),
                       .des1(des1),
                       .des2(des2),
                       .desCy(desCy),
                       .desAc(desAc),
                       .desOv(desOv),
                       .bit_in(bit_out));
 
//
//data ram
oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),
                               .rst(wb_rst_i),
                               .rd_addr(rd_addr),
                               .rd_data(ram_data),
                               .wr_addr(wr_addr),
                               .bit_addr(bit_addr_o),
                               .wr_data(wr_dat),
                               .wr(wr_o && (!wr_addr[7] || wr_ind)),
                               .bit_data_in(desCy),
                               .bit_data_out(bit_data));
 
//
 
oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),
                                       .rst(wb_rst_i),
                                       .rd(rd),
 
                                       .sel1(src_sel1),
                                       .sel2(src_sel2),
                                       .sel3(src_sel3),
 
                                       .acc(acc),
                                       .ram(ram_out),
                                       .pc(pc),
                                       .dptr({dptr_hi, dptr_lo}),
                                       .op1(op1_n),
                                       .op2(op2_n),
                                       .op3(op3_n),
 
                                       .src1(src1),
                                       .src2(src2),
                                       .src3(src3));
 
 
//
//
oc8051_comp oc8051_comp1(.sel(comp_sel),
                         .eq(eq),
                         .b_in(bit_out),
                         .cy(cy),
                         .acc(acc),
                         .des(des1)
                         );
 
 
//
//program rom
`ifdef OC8051_ROM
  oc8051_rom oc8051_rom1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .ea_int(ea_int),
                       .addr(iadr_o),
                       .data1(op1_i),
                       .data2(op2_i),
                       .data3(op3_i));
`else
  assign ea_int = 1'b0;
  assign op1_i = 8'h00;
  assign op2_i = 8'h00;
  assign op3_i = 8'h00;
`endif
 
//
//
oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),
                                   .cy_in(cy),
                                   .data_in(bit_out),
                                   .data_out(alu_cy));
//
//
oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),
                                    .rst(wb_rst_i),
                                    .wr_addr(wr_addr),
                                    .data_in(wr_dat),
                                    .wr(wr_o),
                                    .wr_bit(bit_addr_o),
                                    .ri_out(ri),
                                    .sel(op1_cur[0]),
                                    .bank(bank_sel));
 
 
 
assign icyc_o = istb_o;
//
//
oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),
                       .rst(wb_rst_i),
// internal ram
                       .wr_i(wr),
                       .wr_o(wr_o),
                       .wr_bit_i(bit_addr),
                       .wr_bit_o(bit_addr_o),
                       .wr_dat(wr_dat),
                       .des_acc(des_acc),
                       .des1(des1),
                       .des2(des2),
                       .rd_addr(rd_addr),
                       .wr_addr(wr_addr),
                       .wr_ind(wr_ind),
                       .bit_in(bit_data),
                       .in_ram(ram_data),
                       .sfr(sfr_out),
                       .sfr_bit(sfr_bit),
                       .bit_out(bit_out),
                       .iram_out(ram_out),
 
// external instrauction rom
                       .iack_i(iack_i),
                       .iadr_o(iadr_o),
                       .idat_i(idat_i),
                       .istb_o(istb_o),
 
// internal instruction rom
                       .op1_i(op1_i),
                       .op2_i(op2_i),
                       .op3_i(op3_i),
 
// data memory
                       .dadr_o(wbd_adr_o),
                       .ddat_o(wbd_dat_o),
                       .dwe_o(wbd_we_o),
                       .dstb_o(wbd_stb_o),
                       .ddat_i(wbd_dat_i),
                       .dack_i(wbd_ack_i),
 
// from decoder
                       .rd_sel(ram_rd_sel),
                       .wr_sel(ram_wr_sel),
                       .rn({bank_sel, op1_cur}),
                       .rd_ind(rd_ind),
                       .rd(rd),
                       .mem_act(mem_act),
                       .mem_wait(mem_wait),
 
// external access
                       .ea(ea_in),
                       .ea_int(ea_int),
 
// instructions outputs to cpu
                       .op1_out(op1_n),
                       .op2_out(op2_n),
                       .op3_out(op3_n),
 
// interrupt interface
                       .intr(intr),
                       .int_v(int_src),
                       .int_ack(int_ack),
                       .istb(istb),
                       .reti(reti),
 
//pc
                       .pc_wr_sel(pc_wr_sel),
                       .pc_wr(pc_wr & comp_wait),
                       .pc(pc),
 
// sfr's
                       .sp_w(sp_w),
                       .dptr({dptr_hi, dptr_lo}),
                       .ri(ri),
                       .acc(acc),
                       .sp(sp)
                       );
 
 
//
//
 
oc8051_sfr oc8051_sfr1(.rst(wb_rst_i),
                       .clk(wb_clk_i),
                       .adr0(rd_addr[7:0]),
                       .adr1(wr_addr[7:0]),
                       .dat0(sfr_out),
                       .dat1(wr_dat),
                       .dat2(des2),
                       .des_acc(des_acc),
                       .we(wr_o && !wr_ind),
                       .bit_in(desCy),
                       .bit_out(sfr_bit),
                       .wr_bit(bit_addr_o),
                       .ram_rd_sel(ram_rd_sel),
                       .ram_wr_sel(ram_wr_sel),
                       .wr_sfr(wr_sfr),
                       .comp_sel(comp_sel),
                       .comp_wait(comp_wait),
// acc
                       .acc(acc),
// sp
                       .sp(sp),
                       .sp_w(sp_w),
// psw
                       .bank_sel(bank_sel),
                       .desAc(desAc),
                       .desOv(desOv),
                       .psw_set(psw_set),
                       .srcAc(srcAc),
                       .cy(cy),
// ports
                       .rmw(rmw),
 
  `ifdef OC8051_PORTS
        `ifdef OC8051_PORT0
                       .p0_out(p0_o),
                       .p0_in(p0_i),
        `endif
 
        `ifdef OC8051_PORT1
                       .p1_out(p1_o),
                       .p1_in(p1_i),
        `endif
 
        `ifdef OC8051_PORT2
                       .p2_out(p2_o),
                       .p2_in(p2_i),
        `endif
 
        `ifdef OC8051_PORT3
                       .p3_out(p3_o),
                       .p3_in(p3_i),
        `endif
  `endif
 
// uart
        `ifdef OC8051_UART
                       .rxd(rxd_i), .txd(txd_o),
        `endif
 
// int
                       .int_ack(int_ack),
                       .intr(intr),
                       .int0(int0_i),
                       .int1(int1_i),
                       .reti(reti),
                       .int_src(int_src),
 
// t/c 0,1
        `ifdef OC8051_TC01
                       .t0(t0_i),
                       .t1(t1_i),
        `endif
 
// t/c 2
        `ifdef OC8051_TC2
                       .t2(t2_i),
                       .t2ex(t2ex_i),
        `endif
 
// dptr
                       .dptr_hi(dptr_hi),
                       .dptr_lo(dptr_lo),
                       .wait_data(wait_data)
                       );
 
 
 
 
`ifdef OC8051_CACHE
 
 
oc8051_icache oc8051_icache1(.rst(wb_rst_i), .clk(wb_clk_i),
// cpu
        .adr_i(iadr_o),
        .dat_o(idat_i),
        .stb_i(istb_o),
        .ack_o(iack_i),
        .cyc_i(icyc_o),
// pins
        .dat_i(wbi_dat_i),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
 
defparam oc8051_icache1.ADR_WIDTH = 7;  // cache address wihth
defparam oc8051_icache1.LINE_WIDTH = 2; // line address width (2 => 4x32)
defparam oc8051_icache1.BL_NUM = 31; // number of blocks (2^BL_WIDTH-1); BL_WIDTH = ADR_WIDTH - LINE_WIDTH
defparam oc8051_icache1.CACHE_RAM = 128; // cache ram x 32 (2^ADR_WIDTH)
 
//
//    no cache
//
`else
 
oc8051_wb_iinterface oc8051_wb_iinterface(.rst(wb_rst_i), .clk(wb_clk_i),
// cpu
        .adr_i(iadr_o),
        .dat_o(idat_i),
        .stb_i(istb_o),
        .ack_o(iack_i),
        .cyc_i(icyc_o),
// external rom
        .dat_i(wbi_dat_i),
        .stb_o(wbi_stb_o),
        .adr_o(wbi_adr_o),
        .ack_i(wbi_ack_i),
        .cyc_o(wbi_cyc_o));
 
 
`endif
 
 
 
endmodule

Line No.	Rev	Author	Line
1	72	simont	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// 8051 cores top level module ////`
4			`//// ////`
5			`//// This file is part of the 8051 cores project ////`
6			`//// http://www.opencores.org/cores/8051/ ////`
7			`//// ////`
8			`//// Description ////`
9			`//// 8051 definitions. ////`
10			`//// ////`
11			`//// To Do: ////`
12			`//// nothing ////`
13			`//// ////`
14			`//// Author(s): ////`
15			`//// - Simon Teran, simont@opencores.org ////`
16			`//// ////`
17			`//////////////////////////////////////////////////////////////////////`
18			`//// ////`
19			`//// Copyright (C) 2000 Authors and OPENCORES.ORG ////`
20			`//// ////`
21			`//// This source file may be used and distributed without ////`
22			`//// restriction provided that this copyright statement is not ////`
23			`//// removed from the file and that any derivative work contains ////`
24			`//// the original copyright notice and the associated disclaimer. ////`
25			`//// ////`
26			`//// This source file is free software; you can redistribute it ////`
27			`//// and/or modify it under the terms of the GNU Lesser General ////`
28			`//// Public License as published by the Free Software Foundation; ////`
29			`//// either version 2.1 of the License, or (at your option) any ////`
30			`//// later version. ////`
31			`//// ////`
32			`//// This source is distributed in the hope that it will be ////`
33			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
34			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
35			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
36			`//// details. ////`
37			`//// ////`
38			`//// You should have received a copy of the GNU Lesser General ////`
39			`//// Public License along with this source; if not, download it ////`
40			`//// from http://www.opencores.org/lgpl.shtml ////`
41			`//// ////`
42			`//////////////////////////////////////////////////////////////////////`
43			`//`
44			`// CVS Revision History`
45			`//`
46	54	simont	`// $Log: not supported by cvs2svn $`
47	144	simont	`// Revision 1.28 2003/05/06 09:41:35 simont`
48			`// remove define OC8051_AS2_PCL, chane signal src_sel2 to 2 bit wide.`
49			`//`
50	141	simont	`// Revision 1.27 2003/05/05 15:46:37 simont`
51			`// add aditional alu destination to solve critical path.`
52			`//`
53	139	simont	`// Revision 1.26 2003/04/29 11:24:31 simont`
54			`// fix bug in case execution of two data dependent instructions.`
55			`//`
56	134	simont	`// Revision 1.25 2003/04/25 17:15:51 simont`
57			`// change branch instruction execution (reduse needed clock periods).`
58			`//`
59	132	simont	`// Revision 1.24 2003/04/11 10:05:59 simont`
60			`// deifne OC8051_ROM added`
61			`//`
62	122	simont	`// Revision 1.23 2003/04/10 12:43:19 simont`
63			`// defines for pherypherals added`
64			`//`
65	120	simont	`// Revision 1.22 2003/04/09 16:24:04 simont`
66			`// change wr_sft to 2 bit wire.`
67			`//`
68	118	simont	`// Revision 1.21 2003/04/09 15:49:42 simont`
69			`// Register oc8051_sfr dato output, add signal wait_data.`
70			`//`
71	117	simont	`// Revision 1.20 2003/04/03 19:13:28 simont`
72			`// Include instruction cache.`
73			`//`
74	107	simont	`// Revision 1.19 2003/04/02 15:08:30 simont`
75			`// raname signals.`
76			`//`
77	102	simont	`// Revision 1.18 2003/01/13 14:14:41 simont`
78			`// replace some modules`
79			`//`
80	82	simont	`// Revision 1.17 2002/11/05 17:23:54 simont`
81			`// add module oc8051_sfr, 256 bytes internal ram`
82			`//`
83	76	simont	`// Revision 1.16 2002/10/28 14:55:00 simont`
84			`// fix bug in interface to external data ram`
85			`//`
86	72	simont	`// Revision 1.15 2002/10/23 16:53:39 simont`
87			`// fix bugs in instruction interface`
88			`//`
89	62	simont	`// Revision 1.14 2002/10/17 18:50:00 simont`
90			`// cahnge interface to instruction rom`
91			`//`
92	54	simont	`// Revision 1.13 2002/09/30 17:33:59 simont`
93			`// prepared header`
94	72	simont	`//`
95			`//`
96
97			`// synopsys translate_off`
98			`include "oc8051_timescale.v"
99			`// synopsys translate_on`
100
101
102	102	simont	`module oc8051_top (wb_rst_i, wb_clk_i,`
103			`//interface to instruction rom`
104	120	simont	`wbi_adr_o,`
105			`wbi_dat_i,`
106			`wbi_stb_o,`
107			`wbi_ack_i,`
108			`wbi_cyc_o,`
109			`wbi_err_i,`
110
111	102	simont	`//interface to data ram`
112	120	simont	`wbd_dat_i,`
113			`wbd_dat_o,`
114			`wbd_adr_o,`
115			`wbd_we_o,`
116	132	simont	`wbd_ack_i,`
117	120	simont	`wbd_stb_o,`
118			`wbd_cyc_o,`
119			`wbd_err_i,`
120
121	102	simont	`// interrupt interface`
122	120	simont	`int0_i,`
123			`int1_i,`
124
125	102	simont	`// external access (active low)`
126			`ea_in,`
127	120	simont
128	102	simont	`// port interface`
129	120	simont	`ifdef OC8051_PORTS
130			`ifdef OC8051_PORT0
131			`p0_i,`
132			`p0_o,`
133			`endif
134
135			`ifdef OC8051_PORT1
136			`p1_i,`
137			`p1_o,`
138			`endif
139
140			`ifdef OC8051_PORT2
141			`p2_i,`
142			`p2_o,`
143			`endif
144
145			`ifdef OC8051_PORT3
146			`p3_i,`
147			`p3_o,`
148			`endif
149			`endif
150
151	102	simont	`// serial interface`
152	120	simont	`ifdef OC8051_UART
153	102	simont	`rxd_i, txd_o,`
154	120	simont	`endif
155
156	102	simont	`// counter interface`
157	120	simont	`ifdef OC8051_TC01
158			`t0_i, t1_i,`
159			`endif
160	72	simont
161	120	simont	`ifdef OC8051_TC2
162			`t2_i, t2ex_i`
163			`endif
164			`);`
165	72	simont
166
167	120	simont
168	102	simont	`input wb_rst_i, // reset input`
169			`wb_clk_i, // clock input`
170			`int0_i, // interrupt 0`
171			`int1_i, // interrupt 1`
172			`ea_in, // external access`
173			`wbd_ack_i, // data acknowalge`
174			`wbi_ack_i, // instruction acknowlage`
175			`wbd_err_i, // data error`
176	120	simont	`wbi_err_i; // instruction error`
177	72	simont
178	120	simont	`input [7:0] wbd_dat_i; // ram data input`
179	102	simont	`input [31:0] wbi_dat_i; // rom data input`
180	72	simont
181	102	simont	`output wbd_we_o, // data write enable`
182			`wbd_stb_o, // data strobe`
183			`wbd_cyc_o, // data cycle`
184			`wbi_stb_o, // instruction strobe`
185			`wbi_cyc_o; // instruction cycle`
186	82	simont
187	120	simont	`output [7:0] wbd_dat_o; // data output`
188	102	simont
189			`output [15:0] wbd_adr_o, // data address`
190			`wbi_adr_o; // instruction address`
191
192	120	simont	`ifdef OC8051_PORTS
193	102	simont
194	120	simont	`ifdef OC8051_PORT0
195			`input [7:0] p0_i; // port 0 input`
196			`output [7:0] p0_o; // port 0 output`
197			`endif
198	72	simont
199	120	simont	`ifdef OC8051_PORT1
200			`input [7:0] p1_i; // port 1 input`
201			`output [7:0] p1_o; // port 1 output`
202			`endif
203	72	simont
204	120	simont	`ifdef OC8051_PORT2
205			`input [7:0] p2_i; // port 2 input`
206			`output [7:0] p2_o; // port 2 output`
207			`endif
208	72	simont
209	120	simont	`ifdef OC8051_PORT3
210			`input [7:0] p3_i; // port 3 input`
211			`output [7:0] p3_o; // port 3 output`
212			`endif
213	72	simont
214	120	simont	`endif
215	72	simont
216
217
218
219
220
221	120	simont	`ifdef OC8051_UART
222			`input rxd_i; // receive`
223			`output txd_o; // transnmit`
224			`endif
225	72	simont
226	120	simont	`ifdef OC8051_TC01
227			`input t0_i, // counter 0 input`
228			`t1_i; // counter 1 input`
229			`endif
230	72	simont
231	120	simont	`ifdef OC8051_TC2
232			`input t2_i, // counter 2 input`
233			`t2ex_i; //`
234			`endif
235	72	simont
236	120	simont	`wire [7:0] op1_i,`
237			`op2_i,`
238			`op3_i,`
239			`dptr_hi,`
240			`dptr_lo,`
241			`ri,`
242			`data_out,`
243			`op1,`
244			`op2,`
245			`op3,`
246			`acc,`
247			`p0_out,`
248			`p1_out,`
249			`p2_out,`
250			`p3_out,`
251			`sp,`
252			`sp_w;`
253	72	simont
254	120	simont	`wire [15:0] pc;`
255	72	simont
256	120	simont	`assign wbd_cyc_o = wbd_stb_o;`
257	72	simont
258	120	simont	`wire src_sel3;`
259	141	simont	`wire [1:0] wr_sfr,`
260			`src_sel2;`
261	120	simont	`wire [2:0] ram_rd_sel, // ram read`
262			`ram_wr_sel, // ram write`
263			`src_sel1;`
264
265			`wire [7:0] ram_data,`
266			`ram_out, //data from ram`
267			`sfr_out,`
268			`wr_dat,`
269			`wr_addr, //ram write addres`
270			`rd_addr; //data ram read addres`
271			`wire sfr_bit;`
272
273			`wire [1:0] cy_sel, //carry select; from decoder to cy_selct1`
274			`bank_sel;`
275			`wire rom_addr_sel, //rom addres select; alu or pc`
276			`rmw,`
277			`ea_int;`
278
279			`wire reti,`
280			`intr,`
281			`int_ack,`
282			`istb;`
283			`wire [7:0] int_src;`
284
285			`wire mem_wait;`
286			`wire [2:0] mem_act;`
287			`wire [3:0] alu_op; //alu operation (from decoder)`
288			`wire [1:0] psw_set; //write to psw or not; from decoder to psw (through register)`
289
290			`wire [7:0] src1, //alu sources 1`
291			`src2, //alu sources 2`
292			`src3, //alu sources 3`
293	139	simont	`des_acc,`
294	120	simont	`des1, //alu destination 1`
295	132	simont	`des2; //alu destinations 2`
296	120	simont	`wire desCy, //carry out`
297			`desAc,`
298			`desOv, //overflow`
299			`alu_cy,`
300			`wr, //write to data ram`
301			`wr_o;`
302
303			`wire rd, //read program rom`
304			`pc_wr;`
305			`wire [2:0] pc_wr_sel; //program counter write select (from decoder to pc)`
306
307			`wire [7:0] op1_n, //from memory_interface to decoder`
308			`op2_n,`
309			`op3_n;`
310
311			`wire [1:0] comp_sel; //select source1 and source2 to compare`
312			`wire eq, //result (from comp1 to decoder)`
313			`srcAc,`
314			`cy,`
315			`rd_ind,`
316	132	simont	`wr_ind,`
317			`comp_wait;`
318	120	simont	`wire [2:0] op1_cur;`
319
320			`wire bit_addr, //bit addresable instruction`
321			`bit_data, //bit data from ram to ram_select`
322			`bit_out, //bit data from ram_select to alu and cy_select`
323			`bit_addr_o,`
324			`wait_data;`
325
326	72	simont	`//`
327	107	simont	`// cpu to cache/wb_interface`
328			`wire iack_i,`
329			`istb_o,`
330			`icyc_o;`
331			`wire [31:0] idat_i;`
332			`wire [15:0] iadr_o;`
333	72	simont
334
335			`//`
336			`// decoder`
337	120	simont	`oc8051_decoder oc8051_decoder1(.clk(wb_clk_i),`
338			`.rst(wb_rst_i),`
339			`.op_in(op1_n),`
340			`.op1_c(op1_cur),`
341			`.ram_rd_sel_o(ram_rd_sel),`
342			`.ram_wr_sel_o(ram_wr_sel),`
343			`.bit_addr(bit_addr),`
344	72	simont
345	120	simont	`.src_sel1(src_sel1),`
346			`.src_sel2(src_sel2),`
347			`.src_sel3(src_sel3),`
348	72	simont
349	120	simont	`.alu_op_o(alu_op),`
350			`.psw_set(psw_set),`
351			`.cy_sel(cy_sel),`
352			`.wr_o(wr),`
353			`.pc_wr(pc_wr),`
354			`.pc_sel(pc_wr_sel),`
355			`.comp_sel(comp_sel),`
356			`.eq(eq),`
357			`.wr_sfr_o(wr_sfr),`
358			`.rd(rd),`
359			`.rmw(rmw),`
360			`.istb(istb),`
361			`.mem_act(mem_act),`
362			`.mem_wait(mem_wait),`
363			`.wait_data(wait_data));`
364
365
366	72	simont	`//`
367			`//alu`
368	120	simont	`oc8051_alu oc8051_alu1(.rst(wb_rst_i),`
369	139	simont	`.clk(wb_clk_i),`
370	120	simont	`.op_code(alu_op),`
371	132	simont	`.src1(src1),`
372	120	simont	`.src2(src2),`
373			`.src3(src3),`
374			`.srcCy(alu_cy),`
375			`.srcAc(srcAc),`
376	139	simont	`.des_acc(des_acc),`
377	132	simont	`.des1(des1),`
378			`.des2(des2),`
379	120	simont	`.desCy(desCy),`
380			`.desAc(desAc),`
381			`.desOv(desOv),`
382			`.bit_in(bit_out));`
383	72	simont
384			`//`
385			`//data ram`
386	134	simont	`oc8051_ram_top oc8051_ram_top1(.clk(wb_clk_i),`
387	120	simont	`.rst(wb_rst_i),`
388			`.rd_addr(rd_addr),`
389			`.rd_data(ram_data),`
390			`.wr_addr(wr_addr),`
391			`.bit_addr(bit_addr_o),`
392			`.wr_data(wr_dat),`
393			`.wr(wr_o && (!wr_addr[7] \|\| wr_ind)),`
394			`.bit_data_in(desCy),`
395			`.bit_data_out(bit_data));`
396	72	simont
397			`//`
398
399	120	simont	`oc8051_alu_src_sel oc8051_alu_src_sel1(.clk(wb_clk_i),`
400			`.rst(wb_rst_i),`
401			`.rd(rd),`
402	82	simont
403	120	simont	`.sel1(src_sel1),`
404			`.sel2(src_sel2),`
405			`.sel3(src_sel3),`
406	82	simont
407	120	simont	`.acc(acc),`
408			`.ram(ram_out),`
409			`.pc(pc),`
410			`.dptr({dptr_hi, dptr_lo}),`
411			`.op1(op1_n),`
412			`.op2(op2_n),`
413			`.op3(op3_n),`
414
415			`.src1(src1),`
416			`.src2(src2),`
417			`.src3(src3));`
418
419
420	72	simont	`//`
421			`//`
422	120	simont	`oc8051_comp oc8051_comp1(.sel(comp_sel),`
423	132	simont	`.eq(eq),`
424			`.b_in(bit_out),`
425			`.cy(cy),`
426			`.acc(acc),`
427	144	simont	`.des(des1)`
428	132	simont	`);`
429	72	simont
430
431			`//`
432			`//program rom`
433	122	simont	`ifdef OC8051_ROM
434			`oc8051_rom oc8051_rom1(.rst(wb_rst_i),`
435			`.clk(wb_clk_i),`
436			`.ea_int(ea_int),`
437	120	simont	`.addr(iadr_o),`
438	122	simont	`.data1(op1_i),`
439			`.data2(op2_i),`
440	120	simont	`.data3(op3_i));`
441	122	simont	`else
442			`assign ea_int = 1'b0;`
443			`assign op1_i = 8'h00;`
444			`assign op2_i = 8'h00;`
445			`assign op3_i = 8'h00;`
446			`endif
447	72	simont
448			`//`
449			`//`
450	120	simont	`oc8051_cy_select oc8051_cy_select1(.cy_sel(cy_sel),`
451			`.cy_in(cy),`
452			`.data_in(bit_out),`
453			`.data_out(alu_cy));`
454	72	simont	`//`
455			`//`
456	120	simont	`oc8051_indi_addr oc8051_indi_addr1 (.clk(wb_clk_i),`
457			`.rst(wb_rst_i),`
458			`.wr_addr(wr_addr),`
459	139	simont	`.data_in(wr_dat),`
460	134	simont	`.wr(wr_o),`
461	120	simont	`.wr_bit(bit_addr_o),`
462	139	simont	`.ri_out(ri),`
463			`.sel(op1_cur[0]),`
464	120	simont	`.bank(bank_sel));`
465	72	simont
466
467	107	simont
468			`assign icyc_o = istb_o;`
469	72	simont	`//`
470			`//`
471	120	simont	`oc8051_memory_interface oc8051_memory_interface1(.clk(wb_clk_i),`
472			`.rst(wb_rst_i),`
473	107	simont	`// internal ram`
474	120	simont	`.wr_i(wr),`
475			`.wr_o(wr_o),`
476			`.wr_bit_i(bit_addr),`
477			`.wr_bit_o(bit_addr_o),`
478			`.wr_dat(wr_dat),`
479	139	simont	`.des_acc(des_acc),`
480	132	simont	`.des1(des1),`
481	120	simont	`.des2(des2),`
482	139	simont	`.rd_addr(rd_addr),`
483	120	simont	`.wr_addr(wr_addr),`
484			`.wr_ind(wr_ind),`
485	139	simont	`.bit_in(bit_data),`
486	120	simont	`.in_ram(ram_data),`
487	139	simont	`.sfr(sfr_out),`
488			`.sfr_bit(sfr_bit),`
489	134	simont	`.bit_out(bit_out),`
490	120	simont	`.iram_out(ram_out),`
491	72	simont
492	107	simont	`// external instrauction rom`
493	120	simont	`.iack_i(iack_i),`
494			`.iadr_o(iadr_o),`
495			`.idat_i(idat_i),`
496			`.istb_o(istb_o),`
497	82	simont
498	107	simont	`// internal instruction rom`
499	139	simont	`.op1_i(op1_i),`
500			`.op2_i(op2_i),`

Browse

Tools

Subversion Repositories 8051

[/] [8051/] [trunk/] [rtl/] [verilog/] [oc8051_top.v] - Blame information for rev 144