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TimeQuest Timing Analyzer report for FPz8_Cyclone_IV
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Fri Nov 11 10:25:14 2016
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Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. TimeQuest Timing Analyzer Summary
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3. Parallel Compilation
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4. SDC File List
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5. Clocks
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6. Slow 1200mV 85C Model Fmax Summary
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7. Slow 1200mV 85C Model Setup Summary
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8. Slow 1200mV 85C Model Hold Summary
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9. Slow 1200mV 85C Model Recovery Summary
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10. Slow 1200mV 85C Model Removal Summary
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11. Slow 1200mV 85C Model Minimum Pulse Width Summary
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12. Slow 1200mV 85C Model Setup: 'CLOCK'
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13. Slow 1200mV 85C Model Hold: 'CLOCK'
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14. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK'
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15. Setup Times
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16. Hold Times
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17. Clock to Output Times
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18. Minimum Clock to Output Times
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19. Slow 1200mV 85C Model Metastability Report
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20. Slow 1200mV 0C Model Fmax Summary
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21. Slow 1200mV 0C Model Setup Summary
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22. Slow 1200mV 0C Model Hold Summary
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23. Slow 1200mV 0C Model Recovery Summary
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24. Slow 1200mV 0C Model Removal Summary
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25. Slow 1200mV 0C Model Minimum Pulse Width Summary
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26. Slow 1200mV 0C Model Setup: 'CLOCK'
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27. Slow 1200mV 0C Model Hold: 'CLOCK'
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28. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK'
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29. Setup Times
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30. Hold Times
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31. Clock to Output Times
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32. Minimum Clock to Output Times
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33. Slow 1200mV 0C Model Metastability Report
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34. Fast 1200mV 0C Model Setup Summary
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35. Fast 1200mV 0C Model Hold Summary
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36. Fast 1200mV 0C Model Recovery Summary
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37. Fast 1200mV 0C Model Removal Summary
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38. Fast 1200mV 0C Model Minimum Pulse Width Summary
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39. Fast 1200mV 0C Model Setup: 'CLOCK'
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40. Fast 1200mV 0C Model Hold: 'CLOCK'
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41. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK'
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42. Setup Times
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43. Hold Times
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44. Clock to Output Times
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45. Minimum Clock to Output Times
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46. Fast 1200mV 0C Model Metastability Report
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47. Multicorner Timing Analysis Summary
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48. Setup Times
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49. Hold Times
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50. Clock to Output Times
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51. Minimum Clock to Output Times
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52. Board Trace Model Assignments
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53. Input Transition Times
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54. Slow Corner Signal Integrity Metrics
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55. Fast Corner Signal Integrity Metrics
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56. Setup Transfers
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57. Hold Transfers
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58. Report TCCS
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59. Report RSKM
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60. Unconstrained Paths
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61. TimeQuest Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+-------------------------------------------------------------------------------------+
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; TimeQuest Timing Analyzer Summary ;
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+--------------------+----------------------------------------------------------------+
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; Quartus II Version ; Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition ;
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; Revision Name ; FPz8_Cyclone_IV ;
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; Device Family ; Cyclone IV E ;
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; Device Name ; EP4CE6E22C8 ;
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; Timing Models ; Preliminary ;
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; Delay Model ; Combined ;
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; Rise/Fall Delays ; Enabled ;
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+--------------------+----------------------------------------------------------------+
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 4 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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+-------------------------------------------------------------+
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; SDC File List ;
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+-------------------------+--------+--------------------------+
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; SDC File Path ; Status ; Read at ;
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+-------------------------+--------+--------------------------+
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; FPz8_Cyclone_IV.out.sdc ; OK ; Fri Nov 11 10:25:03 2016 ;
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+-------------------------+--------+--------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clocks ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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; CLOCK ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { CLOCK } ;
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+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------+
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+-------------------------------------------------+
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; Slow 1200mV 85C Model Fmax Summary ;
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+-----------+-----------------+------------+------+
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; Fmax ; Restricted Fmax ; Clock Name ; Note ;
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+-----------+-----------------+------------+------+
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; 21.13 MHz ; 21.13 MHz ; CLOCK ; ;
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+-----------+-----------------+------------+------+
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This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
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+-------------------------------------+
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; Slow 1200mV 85C Model Setup Summary ;
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+-------+---------+-------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+---------+-------------------+
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; CLOCK ; -26.441 ; -8505.086 ;
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+-------+---------+-------------------+
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+------------------------------------+
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; Slow 1200mV 85C Model Hold Summary ;
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+-------+-------+--------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+-------+--------------------+
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; CLOCK ; 0.432 ; 0.000 ;
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+-------+-------+--------------------+
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------------------------------------------
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; Slow 1200mV 85C Model Recovery Summary ;
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------------------------------------------
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No paths to report.
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-----------------------------------------
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; Slow 1200mV 85C Model Removal Summary ;
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-----------------------------------------
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No paths to report.
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+---------------------------------------------------+
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; Slow 1200mV 85C Model Minimum Pulse Width Summary ;
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+-------+--------+----------------------------------+
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; Clock ; Slack ; End Point TNS ;
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+-------+--------+----------------------------------+
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; CLOCK ; -3.201 ; -910.432 ;
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+-------+--------+----------------------------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Slow 1200mV 85C Model Setup: 'CLOCK' ;
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+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
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; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
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+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
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; -26.441 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 27.361 ;
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; -26.305 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 27.225 ;
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; -25.869 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.788 ;
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; -25.822 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.741 ;
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; -25.770 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.690 ;
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; -25.758 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.653 ;
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; -25.705 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.624 ;
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; -25.668 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.588 ;
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; -25.631 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.540 ;
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; -25.622 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.517 ;
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; -25.569 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.496 ;
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; -25.545 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.081 ; 26.465 ;
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; -25.511 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.430 ;
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; -25.493 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.390 ;
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; -25.489 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.398 ;
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; -25.434 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.329 ;
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; -25.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.360 ;
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; -25.401 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.320 ;
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; -25.396 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.315 ;
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; -25.393 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 26.303 ;
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; -25.378 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 26.288 ;
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; -25.366 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.263 ;
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; -25.357 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.254 ;
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; -25.355 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 26.271 ;
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| 212 |
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; -25.352 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 26.265 ;
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| 213 |
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; -25.343 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.251 ;
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| 214 |
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; -25.328 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.246 ;
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| 215 |
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; -25.299 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 26.208 ;
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| 216 |
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; -25.298 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 26.193 ;
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| 217 |
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; -25.260 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 26.179 ;
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| 218 |
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; -25.236 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.144 ;
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| 219 |
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; -25.232 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 26.158 ;
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| 220 |
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; -25.230 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.127 ;
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| 221 |
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; -25.219 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 26.135 ;
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| 222 |
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; -25.216 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 26.129 ;
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| 223 |
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; -25.212 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 26.109 ;
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| 224 |
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; -25.200 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.118 ;
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; -25.195 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.103 ;
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; -25.192 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.110 ;
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; -25.191 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 26.119 ;
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| 228 |
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; -25.186 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 26.080 ;
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| 229 |
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; -25.177 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 26.077 ;
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| 230 |
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; -25.139 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 26.033 ;
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|
|
; -25.132 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 26.040 ;
|
| 232 |
|
|
; -25.126 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 26.053 ;
|
| 233 |
|
|
; -25.121 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 26.039 ;
|
| 234 |
|
|
; -25.107 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.090 ; 26.018 ;
|
| 235 |
|
|
; -25.098 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.998 ;
|
| 236 |
|
|
; -25.096 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 26.022 ;
|
| 237 |
|
|
; -25.087 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.982 ;
|
| 238 |
|
|
; -25.076 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 25.973 ;
|
| 239 |
|
|
; -25.064 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.982 ;
|
| 240 |
|
|
; -25.055 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.983 ;
|
| 241 |
|
|
; -25.041 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.941 ;
|
| 242 |
|
|
; -25.029 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 25.937 ;
|
| 243 |
|
|
; -25.027 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.942 ;
|
| 244 |
|
|
; -25.026 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.936 ;
|
| 245 |
|
|
; -25.025 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.953 ;
|
| 246 |
|
|
; -25.022 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.916 ;
|
| 247 |
|
|
; -25.019 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 25.928 ;
|
| 248 |
|
|
; -25.013 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.929 ;
|
| 249 |
|
|
; -25.011 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.925 ;
|
| 250 |
|
|
; -24.997 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.923 ;
|
| 251 |
|
|
; -24.996 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.914 ;
|
| 252 |
|
|
; -24.994 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 25.907 ;
|
| 253 |
|
|
; -24.990 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.917 ;
|
| 254 |
|
|
; -24.985 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.903 ;
|
| 255 |
|
|
; -24.985 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.880 ;
|
| 256 |
|
|
; -24.979 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.058 ; 25.922 ;
|
| 257 |
|
|
; -24.972 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.891 ;
|
| 258 |
|
|
; -24.971 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.090 ; 25.882 ;
|
| 259 |
|
|
; -24.962 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.101 ; 25.862 ;
|
| 260 |
|
|
; -24.950 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.876 ;
|
| 261 |
|
|
; -24.945 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.117 ; 25.829 ;
|
| 262 |
|
|
; -24.944 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[10] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.859 ;
|
| 263 |
|
|
; -24.944 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 25.866 ;
|
| 264 |
|
|
; -24.926 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.845 ;
|
| 265 |
|
|
; -24.922 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[11] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.836 ;
|
| 266 |
|
|
; -24.921 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.105 ; 25.817 ;
|
| 267 |
|
|
; -24.907 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.093 ; 25.815 ;
|
| 268 |
|
|
; -24.898 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.825 ;
|
| 269 |
|
|
; -24.891 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.806 ;
|
| 270 |
|
|
; -24.889 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.817 ;
|
| 271 |
|
|
; -24.882 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.801 ;
|
| 272 |
|
|
; -24.875 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.087 ; 25.789 ;
|
| 273 |
|
|
; -24.874 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.105 ; 25.770 ;
|
| 274 |
|
|
; -24.871 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.787 ;
|
| 275 |
|
|
; -24.862 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 25.757 ;
|
| 276 |
|
|
; -24.862 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.756 ;
|
| 277 |
|
|
; -24.860 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.778 ;
|
| 278 |
|
|
; -24.858 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.088 ; 25.771 ;
|
| 279 |
|
|
; -24.833 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 25.759 ;
|
| 280 |
|
|
; -24.828 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.722 ;
|
| 281 |
|
|
; -24.824 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.742 ;
|
| 282 |
|
|
; -24.822 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.104 ; 25.719 ;
|
| 283 |
|
|
; -24.821 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[7] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.731 ;
|
| 284 |
|
|
; -24.817 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.091 ; 25.727 ;
|
| 285 |
|
|
; -24.815 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 25.709 ;
|
| 286 |
|
|
; -24.808 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[10] ; CLOCK ; CLOCK ; 1.000 ; -0.086 ; 25.723 ;
|
| 287 |
|
|
; -24.808 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 25.730 ;
|
| 288 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 292 |
|
|
; Slow 1200mV 85C Model Hold: 'CLOCK' ;
|
| 293 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 294 |
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
| 295 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 296 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 297 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 298 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 299 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 300 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 301 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 302 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 303 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 304 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 305 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 306 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 307 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 308 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 309 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 310 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 311 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 312 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 313 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 314 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 315 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 316 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 317 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 318 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 319 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 320 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 321 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 322 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 323 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 324 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|FCTL[2] ; fpz8_cpu_v1:inst|FCTL[2] ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 325 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 326 |
|
|
; 0.432 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.082 ; 0.746 ;
|
| 327 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 328 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 329 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 330 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 331 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 332 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 333 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 334 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 335 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 336 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 337 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 338 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 339 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 340 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 341 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 342 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 343 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 344 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 345 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 346 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 347 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 348 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 349 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 350 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 351 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 352 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 353 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 354 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 355 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 356 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 357 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 358 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 359 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 360 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 361 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 362 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 363 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 364 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 365 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 366 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 367 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 368 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 369 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 370 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 371 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 372 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 373 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 374 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 375 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 376 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 377 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 378 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 379 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 380 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 381 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 382 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 383 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 384 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 385 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 386 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][0] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 387 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 388 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 389 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 390 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 391 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_DMAB ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_DMAB ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 392 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM2 ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 393 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 394 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 395 |
|
|
; 0.433 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.081 ; 0.746 ;
|
| 396 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 397 |
|
|
|
| 398 |
|
|
|
| 399 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 400 |
|
|
; Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK' ;
|
| 401 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 402 |
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
| 403 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 404 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 405 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 406 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 407 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 408 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 409 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 410 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 411 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 412 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 413 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;
|
| 414 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;
|
| 415 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;
|
| 416 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;
|
| 417 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;
|
| 418 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;
|
| 419 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;
|
| 420 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;
|
| 421 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;
|
| 422 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;
|
| 423 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;
|
| 424 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;
|
| 425 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;
|
| 426 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;
|
| 427 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;
|
| 428 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;
|
| 429 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;
|
| 430 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;
|
| 431 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;
|
| 432 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;
|
| 433 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;
|
| 434 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;
|
| 435 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;
|
| 436 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;
|
| 437 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;
|
| 438 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;
|
| 439 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;
|
| 440 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 441 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 442 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 443 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;
|
| 444 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;
|
| 445 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;
|
| 446 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;
|
| 447 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;
|
| 448 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;
|
| 449 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;
|
| 450 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;
|
| 451 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;
|
| 452 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;
|
| 453 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;
|
| 454 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;
|
| 455 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;
|
| 456 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;
|
| 457 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;
|
| 458 |
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;
|
| 459 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;
|
| 460 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;
|
| 461 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;
|
| 462 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;
|
| 463 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;
|
| 464 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;
|
| 465 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;
|
| 466 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;
|
| 467 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;
|
| 468 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;
|
| 469 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;
|
| 470 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;
|
| 471 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;
|
| 472 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;
|
| 473 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;
|
| 474 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;
|
| 475 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;
|
| 476 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;
|
| 477 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;
|
| 478 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;
|
| 479 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;
|
| 480 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;
|
| 481 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;
|
| 482 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;
|
| 483 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;
|
| 484 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;
|
| 485 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;
|
| 486 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;
|
| 487 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;
|
| 488 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;
|
| 489 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;
|
| 490 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;
|
| 491 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;
|
| 492 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;
|
| 493 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;
|
| 494 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;
|
| 495 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;
|
| 496 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;
|
| 497 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;
|
| 498 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;
|
| 499 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;
|
| 500 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;
|
| 501 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;
|
| 502 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;
|
| 503 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;
|
| 504 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 505 |
|
|
|
| 506 |
|
|
|
| 507 |
|
|
+-----------------------------------------------------------------------+
|
| 508 |
|
|
; Setup Times ;
|
| 509 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 510 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 511 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 512 |
|
|
; DBG_RX ; CLOCK ; 0.279 ; 0.485 ; Rise ; CLOCK ;
|
| 513 |
|
|
; RESET ; CLOCK ; 7.699 ; 8.228 ; Rise ; CLOCK ;
|
| 514 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 515 |
|
|
|
| 516 |
|
|
|
| 517 |
|
|
+-------------------------------------------------------------------------+
|
| 518 |
|
|
; Hold Times ;
|
| 519 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 520 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 521 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 522 |
|
|
; DBG_RX ; CLOCK ; 0.206 ; -0.008 ; Rise ; CLOCK ;
|
| 523 |
|
|
; RESET ; CLOCK ; -1.507 ; -1.769 ; Rise ; CLOCK ;
|
| 524 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 525 |
|
|
|
| 526 |
|
|
|
| 527 |
|
|
+-----------------------------------------------------------------------+
|
| 528 |
|
|
; Clock to Output Times ;
|
| 529 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 530 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 531 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 532 |
|
|
; DBG_TX ; CLOCK ; 7.165 ; 7.071 ; Rise ; CLOCK ;
|
| 533 |
|
|
; PAOUT[*] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;
|
| 534 |
|
|
; PAOUT[0] ; CLOCK ; 7.699 ; 7.560 ; Rise ; CLOCK ;
|
| 535 |
|
|
; PAOUT[1] ; CLOCK ; 7.832 ; 7.656 ; Rise ; CLOCK ;
|
| 536 |
|
|
; PAOUT[2] ; CLOCK ; 7.578 ; 7.452 ; Rise ; CLOCK ;
|
| 537 |
|
|
; PAOUT[3] ; CLOCK ; 7.472 ; 7.354 ; Rise ; CLOCK ;
|
| 538 |
|
|
; PAOUT[4] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;
|
| 539 |
|
|
; PAOUT[5] ; CLOCK ; 7.332 ; 7.221 ; Rise ; CLOCK ;
|
| 540 |
|
|
; PAOUT[6] ; CLOCK ; 7.464 ; 7.309 ; Rise ; CLOCK ;
|
| 541 |
|
|
; PAOUT[7] ; CLOCK ; 7.445 ; 7.306 ; Rise ; CLOCK ;
|
| 542 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 543 |
|
|
|
| 544 |
|
|
|
| 545 |
|
|
+-----------------------------------------------------------------------+
|
| 546 |
|
|
; Minimum Clock to Output Times ;
|
| 547 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 548 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 549 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 550 |
|
|
; DBG_TX ; CLOCK ; 6.915 ; 6.825 ; Rise ; CLOCK ;
|
| 551 |
|
|
; PAOUT[*] ; CLOCK ; 7.073 ; 6.965 ; Rise ; CLOCK ;
|
| 552 |
|
|
; PAOUT[0] ; CLOCK ; 7.429 ; 7.295 ; Rise ; CLOCK ;
|
| 553 |
|
|
; PAOUT[1] ; CLOCK ; 7.556 ; 7.387 ; Rise ; CLOCK ;
|
| 554 |
|
|
; PAOUT[2] ; CLOCK ; 7.313 ; 7.191 ; Rise ; CLOCK ;
|
| 555 |
|
|
; PAOUT[3] ; CLOCK ; 7.211 ; 7.098 ; Rise ; CLOCK ;
|
| 556 |
|
|
; PAOUT[4] ; CLOCK ; 8.799 ; 8.735 ; Rise ; CLOCK ;
|
| 557 |
|
|
; PAOUT[5] ; CLOCK ; 7.073 ; 6.965 ; Rise ; CLOCK ;
|
| 558 |
|
|
; PAOUT[6] ; CLOCK ; 7.200 ; 7.050 ; Rise ; CLOCK ;
|
| 559 |
|
|
; PAOUT[7] ; CLOCK ; 7.181 ; 7.047 ; Rise ; CLOCK ;
|
| 560 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 561 |
|
|
|
| 562 |
|
|
|
| 563 |
|
|
----------------------------------------------
|
| 564 |
|
|
; Slow 1200mV 85C Model Metastability Report ;
|
| 565 |
|
|
----------------------------------------------
|
| 566 |
|
|
No synchronizer chains to report.
|
| 567 |
|
|
|
| 568 |
|
|
|
| 569 |
|
|
+-------------------------------------------------+
|
| 570 |
|
|
; Slow 1200mV 0C Model Fmax Summary ;
|
| 571 |
|
|
+-----------+-----------------+------------+------+
|
| 572 |
|
|
; Fmax ; Restricted Fmax ; Clock Name ; Note ;
|
| 573 |
|
|
+-----------+-----------------+------------+------+
|
| 574 |
|
|
; 22.45 MHz ; 22.45 MHz ; CLOCK ; ;
|
| 575 |
|
|
+-----------+-----------------+------------+------+
|
| 576 |
|
|
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
|
| 577 |
|
|
|
| 578 |
|
|
|
| 579 |
|
|
+------------------------------------+
|
| 580 |
|
|
; Slow 1200mV 0C Model Setup Summary ;
|
| 581 |
|
|
+-------+---------+------------------+
|
| 582 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 583 |
|
|
+-------+---------+------------------+
|
| 584 |
|
|
; CLOCK ; -24.794 ; -7986.414 ;
|
| 585 |
|
|
+-------+---------+------------------+
|
| 586 |
|
|
|
| 587 |
|
|
|
| 588 |
|
|
+-----------------------------------+
|
| 589 |
|
|
; Slow 1200mV 0C Model Hold Summary ;
|
| 590 |
|
|
+-------+-------+-------------------+
|
| 591 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 592 |
|
|
+-------+-------+-------------------+
|
| 593 |
|
|
; CLOCK ; 0.380 ; 0.000 ;
|
| 594 |
|
|
+-------+-------+-------------------+
|
| 595 |
|
|
|
| 596 |
|
|
|
| 597 |
|
|
-----------------------------------------
|
| 598 |
|
|
; Slow 1200mV 0C Model Recovery Summary ;
|
| 599 |
|
|
-----------------------------------------
|
| 600 |
|
|
No paths to report.
|
| 601 |
|
|
|
| 602 |
|
|
|
| 603 |
|
|
----------------------------------------
|
| 604 |
|
|
; Slow 1200mV 0C Model Removal Summary ;
|
| 605 |
|
|
----------------------------------------
|
| 606 |
|
|
No paths to report.
|
| 607 |
|
|
|
| 608 |
|
|
|
| 609 |
|
|
+--------------------------------------------------+
|
| 610 |
|
|
; Slow 1200mV 0C Model Minimum Pulse Width Summary ;
|
| 611 |
|
|
+-------+--------+---------------------------------+
|
| 612 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 613 |
|
|
+-------+--------+---------------------------------+
|
| 614 |
|
|
; CLOCK ; -3.201 ; -910.432 ;
|
| 615 |
|
|
+-------+--------+---------------------------------+
|
| 616 |
|
|
|
| 617 |
|
|
|
| 618 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 619 |
|
|
; Slow 1200mV 0C Model Setup: 'CLOCK' ;
|
| 620 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 621 |
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
| 622 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 623 |
|
|
; -24.794 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.723 ;
|
| 624 |
|
|
; -24.709 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.638 ;
|
| 625 |
|
|
; -24.428 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.347 ;
|
| 626 |
|
|
; -24.309 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.237 ;
|
| 627 |
|
|
; -24.216 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 25.135 ;
|
| 628 |
|
|
; -24.187 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 25.116 ;
|
| 629 |
|
|
; -24.187 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.115 ;
|
| 630 |
|
|
; -24.107 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 25.024 ;
|
| 631 |
|
|
; -24.104 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 25.009 ;
|
| 632 |
|
|
; -24.094 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 25.014 ;
|
| 633 |
|
|
; -24.083 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 25.011 ;
|
| 634 |
|
|
; -24.077 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.997 ;
|
| 635 |
|
|
; -24.048 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 24.977 ;
|
| 636 |
|
|
; -24.019 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.924 ;
|
| 637 |
|
|
; -24.007 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.924 ;
|
| 638 |
|
|
; -23.945 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.073 ; 24.874 ;
|
| 639 |
|
|
; -23.944 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.863 ;
|
| 640 |
|
|
; -23.919 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.847 ;
|
| 641 |
|
|
; -23.886 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.803 ;
|
| 642 |
|
|
; -23.869 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.804 ;
|
| 643 |
|
|
; -23.828 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.756 ;
|
| 644 |
|
|
; -23.825 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.084 ; 24.743 ;
|
| 645 |
|
|
; -23.825 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.752 ;
|
| 646 |
|
|
; -23.784 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.719 ;
|
| 647 |
|
|
; -23.783 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.690 ;
|
| 648 |
|
|
; -23.768 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.673 ;
|
| 649 |
|
|
; -23.754 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.678 ;
|
| 650 |
|
|
; -23.748 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.673 ;
|
| 651 |
|
|
; -23.740 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.667 ;
|
| 652 |
|
|
; -23.731 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.648 ;
|
| 653 |
|
|
; -23.701 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.621 ;
|
| 654 |
|
|
; -23.698 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.605 ;
|
| 655 |
|
|
; -23.697 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.592 ;
|
| 656 |
|
|
; -23.685 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.084 ; 24.603 ;
|
| 657 |
|
|
; -23.683 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.588 ;
|
| 658 |
|
|
; -23.669 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.593 ;
|
| 659 |
|
|
; -23.668 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.595 ;
|
| 660 |
|
|
; -23.663 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.080 ; 24.585 ;
|
| 661 |
|
|
; -23.661 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.578 ;
|
| 662 |
|
|
; -23.619 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.523 ;
|
| 663 |
|
|
; -23.583 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.075 ; 24.510 ;
|
| 664 |
|
|
; -23.578 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.080 ; 24.500 ;
|
| 665 |
|
|
; -23.572 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.479 ;
|
| 666 |
|
|
; -23.562 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.496 ;
|
| 667 |
|
|
; -23.548 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.072 ; 24.478 ;
|
| 668 |
|
|
; -23.539 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.459 ;
|
| 669 |
|
|
; -23.536 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.461 ;
|
| 670 |
|
|
; -23.534 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.469 ;
|
| 671 |
|
|
; -23.527 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 24.478 ;
|
| 672 |
|
|
; -23.520 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.446 ;
|
| 673 |
|
|
; -23.497 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.402 ;
|
| 674 |
|
|
; -23.497 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.401 ;
|
| 675 |
|
|
; -23.494 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.429 ;
|
| 676 |
|
|
; -23.487 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.394 ;
|
| 677 |
|
|
; -23.485 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.380 ;
|
| 678 |
|
|
; -23.483 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.403 ;
|
| 679 |
|
|
; -23.477 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.411 ;
|
| 680 |
|
|
; -23.466 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.376 ;
|
| 681 |
|
|
; -23.454 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.371 ;
|
| 682 |
|
|
; -23.452 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.085 ; 24.369 ;
|
| 683 |
|
|
; -23.449 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.384 ;
|
| 684 |
|
|
; -23.441 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.365 ;
|
| 685 |
|
|
; -23.440 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.368 ;
|
| 686 |
|
|
; -23.438 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.345 ;
|
| 687 |
|
|
; -23.435 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.361 ;
|
| 688 |
|
|
; -23.427 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.350 ;
|
| 689 |
|
|
; -23.424 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.349 ;
|
| 690 |
|
|
; -23.414 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.340 ;
|
| 691 |
|
|
; -23.413 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.338 ;
|
| 692 |
|
|
; -23.409 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.067 ; 24.344 ;
|
| 693 |
|
|
; -23.407 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.331 ;
|
| 694 |
|
|
; -23.405 ; fpz8_cpu_v1:inst|IRQ0ENL[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.324 ;
|
| 695 |
|
|
; -23.402 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.107 ; 24.297 ;
|
| 696 |
|
|
; -23.397 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.323 ;
|
| 697 |
|
|
; -23.397 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.322 ;
|
| 698 |
|
|
; -23.393 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.297 ;
|
| 699 |
|
|
; -23.384 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.068 ; 24.318 ;
|
| 700 |
|
|
; -23.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.291 ;
|
| 701 |
|
|
; -23.376 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.109 ; 24.269 ;
|
| 702 |
|
|
; -23.372 ; fpz8_cpu_v1:inst|IRQ0ENH[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.291 ;
|
| 703 |
|
|
; -23.366 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.286 ;
|
| 704 |
|
|
; -23.365 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.082 ; 24.285 ;
|
| 705 |
|
|
; -23.363 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 24.259 ;
|
| 706 |
|
|
; -23.363 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.074 ; 24.291 ;
|
| 707 |
|
|
; -23.362 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.285 ;
|
| 708 |
|
|
; -23.358 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.097 ; 24.263 ;
|
| 709 |
|
|
; -23.353 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.095 ; 24.260 ;
|
| 710 |
|
|
; -23.346 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.106 ; 24.242 ;
|
| 711 |
|
|
; -23.341 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.092 ; 24.251 ;
|
| 712 |
|
|
; -23.340 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.076 ; 24.266 ;
|
| 713 |
|
|
; -23.339 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.264 ;
|
| 714 |
|
|
; -23.327 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.079 ; 24.250 ;
|
| 715 |
|
|
; -23.325 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.115 ; 24.212 ;
|
| 716 |
|
|
; -23.322 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.078 ; 24.246 ;
|
| 717 |
|
|
; -23.316 ; fpz8_cpu_v1:inst|IRQ0ENL[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.083 ; 24.235 ;
|
| 718 |
|
|
; -23.312 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.077 ; 24.237 ;
|
| 719 |
|
|
; -23.298 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.096 ; 24.204 ;
|
| 720 |
|
|
; -23.293 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[1] ; CLOCK ; CLOCK ; 1.000 ; -0.072 ; 24.223 ;
|
| 721 |
|
|
; -23.292 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.061 ; 24.233 ;
|
| 722 |
|
|
; -23.283 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.098 ; 24.187 ;
|
| 723 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 724 |
|
|
|
| 725 |
|
|
|
| 726 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 727 |
|
|
; Slow 1200mV 0C Model Hold: 'CLOCK' ;
|
| 728 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 729 |
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
| 730 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 731 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 732 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 733 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 734 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 735 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 736 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 737 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 738 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 739 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 740 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 741 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 742 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|FCTL[2] ; fpz8_cpu_v1:inst|FCTL[2] ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 743 |
|
|
; 0.380 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.074 ; 0.669 ;
|
| 744 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 745 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 746 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 747 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 748 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 749 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 750 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 751 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 752 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 753 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 754 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 755 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 756 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 757 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 758 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 759 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 760 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 761 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 762 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 763 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 764 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 765 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 766 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 767 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 768 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 769 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 770 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 771 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 772 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 773 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 774 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 775 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 776 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 777 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 778 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 779 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 780 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL1 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL1 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 781 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 782 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 783 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 784 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 785 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; fpz8_cpu_v1:inst|\main:DBG_UART.TX_STATE.DBGTX_IDLE ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 786 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 787 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 788 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG4 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG4 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 789 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.WRT ; fpz8_cpu_v1:inst|\main:DBG_UART.WRT ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 790 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 791 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 792 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 793 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 794 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 795 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 796 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 797 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.TXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 798 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 799 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 800 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 801 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 802 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; fpz8_cpu_v1:inst|\main:ATM_COUNTER[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 803 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_PROGMEM5 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_PROGMEM5 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 804 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 805 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WRITE_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_WRITE_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 806 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 807 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 808 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 809 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 810 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 811 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDMTOP2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDMTOP2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 812 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 813 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 814 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_REG2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 815 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS3 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 816 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 817 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 818 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 819 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 820 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 821 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 822 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 823 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 824 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_VECTOR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_VECTOR ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 825 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM4 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOM4 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 826 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MTOXAD2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 827 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRD3 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 828 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_MUL2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 829 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRS2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 830 |
|
|
; 0.381 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS2 ; CLOCK ; CLOCK ; 0.000 ; 0.073 ; 0.669 ;
|
| 831 |
|
|
+-------+-----------------------------------------------------+-----------------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 832 |
|
|
|
| 833 |
|
|
|
| 834 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 835 |
|
|
; Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK' ;
|
| 836 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 837 |
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
| 838 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 839 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 840 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 841 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 842 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 843 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 844 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 845 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 846 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 847 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 848 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;
|
| 849 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;
|
| 850 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;
|
| 851 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;
|
| 852 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;
|
| 853 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;
|
| 854 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;
|
| 855 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;
|
| 856 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;
|
| 857 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;
|
| 858 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;
|
| 859 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;
|
| 860 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;
|
| 861 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;
|
| 862 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;
|
| 863 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;
|
| 864 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;
|
| 865 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;
|
| 866 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;
|
| 867 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;
|
| 868 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;
|
| 869 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;
|
| 870 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;
|
| 871 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;
|
| 872 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;
|
| 873 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;
|
| 874 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;
|
| 875 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 876 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 877 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 878 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;
|
| 879 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;
|
| 880 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;
|
| 881 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;
|
| 882 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;
|
| 883 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;
|
| 884 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;
|
| 885 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;
|
| 886 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;
|
| 887 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;
|
| 888 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;
|
| 889 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;
|
| 890 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;
|
| 891 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;
|
| 892 |
|
|
; -3.201 ; 1.000 ; 4.201 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;
|
| 893 |
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;
|
| 894 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;
|
| 895 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;
|
| 896 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;
|
| 897 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;
|
| 898 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;
|
| 899 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;
|
| 900 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;
|
| 901 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;
|
| 902 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;
|
| 903 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;
|
| 904 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;
|
| 905 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;
|
| 906 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;
|
| 907 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;
|
| 908 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;
|
| 909 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;
|
| 910 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;
|
| 911 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;
|
| 912 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;
|
| 913 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;
|
| 914 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;
|
| 915 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;
|
| 916 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;
|
| 917 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;
|
| 918 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;
|
| 919 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;
|
| 920 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;
|
| 921 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;
|
| 922 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;
|
| 923 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;
|
| 924 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;
|
| 925 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;
|
| 926 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;
|
| 927 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;
|
| 928 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;
|
| 929 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;
|
| 930 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;
|
| 931 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;
|
| 932 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;
|
| 933 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;
|
| 934 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;
|
| 935 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;
|
| 936 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;
|
| 937 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;
|
| 938 |
|
|
; -1.487 ; 1.000 ; 2.487 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;
|
| 939 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 940 |
|
|
|
| 941 |
|
|
|
| 942 |
|
|
+-----------------------------------------------------------------------+
|
| 943 |
|
|
; Setup Times ;
|
| 944 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 945 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 946 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 947 |
|
|
; DBG_RX ; CLOCK ; 0.243 ; 0.565 ; Rise ; CLOCK ;
|
| 948 |
|
|
; RESET ; CLOCK ; 6.928 ; 7.992 ; Rise ; CLOCK ;
|
| 949 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 950 |
|
|
|
| 951 |
|
|
|
| 952 |
|
|
+-------------------------------------------------------------------------+
|
| 953 |
|
|
; Hold Times ;
|
| 954 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 955 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 956 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 957 |
|
|
; DBG_RX ; CLOCK ; 0.189 ; -0.129 ; Rise ; CLOCK ;
|
| 958 |
|
|
; RESET ; CLOCK ; -1.364 ; -1.806 ; Rise ; CLOCK ;
|
| 959 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 960 |
|
|
|
| 961 |
|
|
|
| 962 |
|
|
+-----------------------------------------------------------------------+
|
| 963 |
|
|
; Clock to Output Times ;
|
| 964 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 965 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 966 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 967 |
|
|
; DBG_TX ; CLOCK ; 6.868 ; 6.718 ; Rise ; CLOCK ;
|
| 968 |
|
|
; PAOUT[*] ; CLOCK ; 8.797 ; 8.602 ; Rise ; CLOCK ;
|
| 969 |
|
|
; PAOUT[0] ; CLOCK ; 7.426 ; 7.133 ; Rise ; CLOCK ;
|
| 970 |
|
|
; PAOUT[1] ; CLOCK ; 7.563 ; 7.230 ; Rise ; CLOCK ;
|
| 971 |
|
|
; PAOUT[2] ; CLOCK ; 7.268 ; 7.037 ; Rise ; CLOCK ;
|
| 972 |
|
|
; PAOUT[3] ; CLOCK ; 7.183 ; 6.968 ; Rise ; CLOCK ;
|
| 973 |
|
|
; PAOUT[4] ; CLOCK ; 8.797 ; 8.602 ; Rise ; CLOCK ;
|
| 974 |
|
|
; PAOUT[5] ; CLOCK ; 7.042 ; 6.832 ; Rise ; CLOCK ;
|
| 975 |
|
|
; PAOUT[6] ; CLOCK ; 7.172 ; 6.916 ; Rise ; CLOCK ;
|
| 976 |
|
|
; PAOUT[7] ; CLOCK ; 7.146 ; 6.915 ; Rise ; CLOCK ;
|
| 977 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 978 |
|
|
|
| 979 |
|
|
|
| 980 |
|
|
+-----------------------------------------------------------------------+
|
| 981 |
|
|
; Minimum Clock to Output Times ;
|
| 982 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 983 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 984 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 985 |
|
|
; DBG_TX ; CLOCK ; 6.623 ; 6.479 ; Rise ; CLOCK ;
|
| 986 |
|
|
; PAOUT[*] ; CLOCK ; 6.788 ; 6.585 ; Rise ; CLOCK ;
|
| 987 |
|
|
; PAOUT[0] ; CLOCK ; 7.159 ; 6.878 ; Rise ; CLOCK ;
|
| 988 |
|
|
; PAOUT[1] ; CLOCK ; 7.291 ; 6.971 ; Rise ; CLOCK ;
|
| 989 |
|
|
; PAOUT[2] ; CLOCK ; 7.008 ; 6.786 ; Rise ; CLOCK ;
|
| 990 |
|
|
; PAOUT[3] ; CLOCK ; 6.926 ; 6.720 ; Rise ; CLOCK ;
|
| 991 |
|
|
; PAOUT[4] ; CLOCK ; 8.530 ; 8.346 ; Rise ; CLOCK ;
|
| 992 |
|
|
; PAOUT[5] ; CLOCK ; 6.788 ; 6.585 ; Rise ; CLOCK ;
|
| 993 |
|
|
; PAOUT[6] ; CLOCK ; 6.912 ; 6.666 ; Rise ; CLOCK ;
|
| 994 |
|
|
; PAOUT[7] ; CLOCK ; 6.886 ; 6.663 ; Rise ; CLOCK ;
|
| 995 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 996 |
|
|
|
| 997 |
|
|
|
| 998 |
|
|
---------------------------------------------
|
| 999 |
|
|
; Slow 1200mV 0C Model Metastability Report ;
|
| 1000 |
|
|
---------------------------------------------
|
| 1001 |
|
|
No synchronizer chains to report.
|
| 1002 |
|
|
|
| 1003 |
|
|
|
| 1004 |
|
|
+------------------------------------+
|
| 1005 |
|
|
; Fast 1200mV 0C Model Setup Summary ;
|
| 1006 |
|
|
+-------+---------+------------------+
|
| 1007 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 1008 |
|
|
+-------+---------+------------------+
|
| 1009 |
|
|
; CLOCK ; -10.913 ; -3387.206 ;
|
| 1010 |
|
|
+-------+---------+------------------+
|
| 1011 |
|
|
|
| 1012 |
|
|
|
| 1013 |
|
|
+-----------------------------------+
|
| 1014 |
|
|
; Fast 1200mV 0C Model Hold Summary ;
|
| 1015 |
|
|
+-------+-------+-------------------+
|
| 1016 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 1017 |
|
|
+-------+-------+-------------------+
|
| 1018 |
|
|
; CLOCK ; 0.166 ; 0.000 ;
|
| 1019 |
|
|
+-------+-------+-------------------+
|
| 1020 |
|
|
|
| 1021 |
|
|
|
| 1022 |
|
|
-----------------------------------------
|
| 1023 |
|
|
; Fast 1200mV 0C Model Recovery Summary ;
|
| 1024 |
|
|
-----------------------------------------
|
| 1025 |
|
|
No paths to report.
|
| 1026 |
|
|
|
| 1027 |
|
|
|
| 1028 |
|
|
----------------------------------------
|
| 1029 |
|
|
; Fast 1200mV 0C Model Removal Summary ;
|
| 1030 |
|
|
----------------------------------------
|
| 1031 |
|
|
No paths to report.
|
| 1032 |
|
|
|
| 1033 |
|
|
|
| 1034 |
|
|
+--------------------------------------------------+
|
| 1035 |
|
|
; Fast 1200mV 0C Model Minimum Pulse Width Summary ;
|
| 1036 |
|
|
+-------+--------+---------------------------------+
|
| 1037 |
|
|
; Clock ; Slack ; End Point TNS ;
|
| 1038 |
|
|
+-------+--------+---------------------------------+
|
| 1039 |
|
|
; CLOCK ; -3.000 ; -587.993 ;
|
| 1040 |
|
|
+-------+--------+---------------------------------+
|
| 1041 |
|
|
|
| 1042 |
|
|
|
| 1043 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1044 |
|
|
; Fast 1200mV 0C Model Setup: 'CLOCK' ;
|
| 1045 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1046 |
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
| 1047 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1048 |
|
|
; -10.913 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.855 ;
|
| 1049 |
|
|
; -10.860 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.802 ;
|
| 1050 |
|
|
; -10.674 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.615 ;
|
| 1051 |
|
|
; -10.672 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.610 ;
|
| 1052 |
|
|
; -10.652 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.593 ;
|
| 1053 |
|
|
; -10.627 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.565 ;
|
| 1054 |
|
|
; -10.627 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.569 ;
|
| 1055 |
|
|
; -10.607 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.544 ;
|
| 1056 |
|
|
; -10.594 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.535 ;
|
| 1057 |
|
|
; -10.583 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.525 ;
|
| 1058 |
|
|
; -10.577 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.515 ;
|
| 1059 |
|
|
; -10.538 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.474 ;
|
| 1060 |
|
|
; -10.519 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.461 ;
|
| 1061 |
|
|
; -10.511 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.452 ;
|
| 1062 |
|
|
; -10.498 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.434 ;
|
| 1063 |
|
|
; -10.461 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.397 ;
|
| 1064 |
|
|
; -10.458 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.399 ;
|
| 1065 |
|
|
; -10.429 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.365 ;
|
| 1066 |
|
|
; -10.428 ; fpz8_cpu_v1:inst|IRQ0ENL[4] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.364 ;
|
| 1067 |
|
|
; -10.417 ; fpz8_cpu_v1:inst|IRQ0ENL[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.354 ;
|
| 1068 |
|
|
; -10.417 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.362 ;
|
| 1069 |
|
|
; -10.409 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.360 ;
|
| 1070 |
|
|
; -10.408 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.344 ;
|
| 1071 |
|
|
; -10.408 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.344 ;
|
| 1072 |
|
|
; -10.398 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.344 ;
|
| 1073 |
|
|
; -10.394 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.330 ;
|
| 1074 |
|
|
; -10.385 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.328 ;
|
| 1075 |
|
|
; -10.364 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.309 ;
|
| 1076 |
|
|
; -10.360 ; fpz8_cpu_v1:inst|IRQ0ENH[6] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.298 ;
|
| 1077 |
|
|
; -10.356 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.307 ;
|
| 1078 |
|
|
; -10.348 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.296 ;
|
| 1079 |
|
|
; -10.347 ; fpz8_cpu_v1:inst|\main:IQUEUE.FULL ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.290 ;
|
| 1080 |
|
|
; -10.346 ; fpz8_cpu_v1:inst|IRQ0ENL[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.282 ;
|
| 1081 |
|
|
; -10.345 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.291 ;
|
| 1082 |
|
|
; -10.341 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.277 ;
|
| 1083 |
|
|
; -10.332 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.275 ;
|
| 1084 |
|
|
; -10.321 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.257 ;
|
| 1085 |
|
|
; -10.320 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.256 ;
|
| 1086 |
|
|
; -10.314 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.266 ;
|
| 1087 |
|
|
; -10.314 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.262 ;
|
| 1088 |
|
|
; -10.298 ; fpz8_cpu_v1:inst|\main:CAN_FETCH ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.030 ; 11.255 ;
|
| 1089 |
|
|
; -10.298 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.236 ;
|
| 1090 |
|
|
; -10.295 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.243 ;
|
| 1091 |
|
|
; -10.290 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.056 ; 11.221 ;
|
| 1092 |
|
|
; -10.289 ; fpz8_cpu_v1:inst|IRQ0ENH[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.049 ; 11.227 ;
|
| 1093 |
|
|
; -10.285 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.236 ;
|
| 1094 |
|
|
; -10.280 ; fpz8_cpu_v1:inst|IRQ0ENH[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.217 ;
|
| 1095 |
|
|
; -10.279 ; fpz8_cpu_v1:inst|IRQ0ENL[5] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.216 ;
|
| 1096 |
|
|
; -10.267 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[12] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.203 ;
|
| 1097 |
|
|
; -10.264 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.200 ;
|
| 1098 |
|
|
; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.204 ;
|
| 1099 |
|
|
; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[4] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.213 ;
|
| 1100 |
|
|
; -10.261 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[11] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.209 ;
|
| 1101 |
|
|
; -10.240 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.187 ;
|
| 1102 |
|
|
; -10.237 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[3] ; CLOCK ; CLOCK ; 1.000 ; -0.056 ; 11.168 ;
|
| 1103 |
|
|
; -10.232 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[6] ; CLOCK ; CLOCK ; 1.000 ; -0.036 ; 11.183 ;
|
| 1104 |
|
|
; -10.231 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.175 ;
|
| 1105 |
|
|
; -10.229 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.055 ; 11.161 ;
|
| 1106 |
|
|
; -10.228 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[0] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.038 ; 11.177 ;
|
| 1107 |
|
|
; -10.224 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[8] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.165 ;
|
| 1108 |
|
|
; -10.223 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.175 ;
|
| 1109 |
|
|
; -10.222 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.157 ;
|
| 1110 |
|
|
; -10.218 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.168 ;
|
| 1111 |
|
|
; -10.215 ; fpz8_cpu_v1:inst|IRQ0ENL[7] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.152 ;
|
| 1112 |
|
|
; -10.211 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[10] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.147 ;
|
| 1113 |
|
|
; -10.208 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[8] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.151 ;
|
| 1114 |
|
|
; -10.205 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.151 ;
|
| 1115 |
|
|
; -10.200 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.053 ; 11.134 ;
|
| 1116 |
|
|
; -10.200 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.135 ;
|
| 1117 |
|
|
; -10.195 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.142 ;
|
| 1118 |
|
|
; -10.188 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[9] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.046 ; 11.129 ;
|
| 1119 |
|
|
; -10.178 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[9] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.122 ;
|
| 1120 |
|
|
; -10.178 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.122 ;
|
| 1121 |
|
|
; -10.176 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[6] ; CLOCK ; CLOCK ; 1.000 ; -0.055 ; 11.108 ;
|
| 1122 |
|
|
; -10.175 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.121 ;
|
| 1123 |
|
|
; -10.175 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[1] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.051 ; 11.111 ;
|
| 1124 |
|
|
; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|MAB[8] ; CLOCK ; CLOCK ; 1.000 ; -0.039 ; 11.118 ;
|
| 1125 |
|
|
; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.120 ;
|
| 1126 |
|
|
; -10.170 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[5] ; CLOCK ; CLOCK ; 1.000 ; -0.035 ; 11.122 ;
|
| 1127 |
|
|
; -10.168 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[7] ; CLOCK ; CLOCK ; 1.000 ; -0.044 ; 11.111 ;
|
| 1128 |
|
|
; -10.165 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|MAB[7] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.115 ;
|
| 1129 |
|
|
; -10.161 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|MAB[10] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.105 ;
|
| 1130 |
|
|
; -10.161 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[12] ; CLOCK ; CLOCK ; 1.000 ; -0.050 ; 11.098 ;
|
| 1131 |
|
|
; -10.159 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.104 ;
|
| 1132 |
|
|
; -10.156 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.063 ; 11.080 ;
|
| 1133 |
|
|
; -10.156 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[0] ; CLOCK ; CLOCK ; 1.000 ; -0.043 ; 11.100 ;
|
| 1134 |
|
|
; -10.155 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.053 ; 11.089 ;
|
| 1135 |
|
|
; -10.155 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.090 ;
|
| 1136 |
|
|
; -10.152 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[0] ; fpz8_cpu_v1:inst|\main:PC[5] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.098 ;
|
| 1137 |
|
|
; -10.151 ; fpz8_cpu_v1:inst|\main:IQUEUE.RDPOS[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.034 ; 11.104 ;
|
| 1138 |
|
|
; -10.150 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[14] ; CLOCK ; CLOCK ; 1.000 ; -0.041 ; 11.096 ;
|
| 1139 |
|
|
; -10.149 ; fpz8_cpu_v1:inst|IRQ0ENH[4] ; fpz8_cpu_v1:inst|\main:PC[14] ; CLOCK ; CLOCK ; 1.000 ; -0.063 ; 11.073 ;
|
| 1140 |
|
|
; -10.149 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[11] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.094 ;
|
| 1141 |
|
|
; -10.148 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.037 ; 11.098 ;
|
| 1142 |
|
|
; -10.146 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[0] ; fpz8_cpu_v1:inst|\main:PC[13] ; CLOCK ; CLOCK ; 1.000 ; -0.045 ; 11.088 ;
|
| 1143 |
|
|
; -10.145 ; fpz8_cpu_v1:inst|IRQ0ENH[5] ; fpz8_cpu_v1:inst|MAB[9] ; CLOCK ; CLOCK ; 1.000 ; -0.040 ; 11.092 ;
|
| 1144 |
|
|
; -10.142 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[2] ; fpz8_cpu_v1:inst|\main:PC[15] ; CLOCK ; CLOCK ; 1.000 ; -0.052 ; 11.077 ;
|
| 1145 |
|
|
; -10.137 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDCNTRX[3] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.042 ; 11.082 ;
|
| 1146 |
|
|
; -10.135 ; fpz8_cpu_v1:inst|\main:IQUEUE.WRPOS[1] ; fpz8_cpu_v1:inst|MAB[2] ; CLOCK ; CLOCK ; 1.000 ; -0.038 ; 11.084 ;
|
| 1147 |
|
|
; -10.135 ; fpz8_cpu_v1:inst|IRQ0ENH[1] ; fpz8_cpu_v1:inst|\main:DEST_ADDR16[15] ; CLOCK ; CLOCK ; 1.000 ; -0.054 ; 11.068 ;
|
| 1148 |
|
|
+---------+----------------------------------------------+----------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1149 |
|
|
|
| 1150 |
|
|
|
| 1151 |
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1152 |
|
|
; Fast 1200mV 0C Model Hold: 'CLOCK' ;
|
| 1153 |
|
|
+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1154 |
|
|
; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
|
| 1155 |
|
|
+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1156 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1157 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[7] ; fpz8_cpu_v1:inst|IRQ0[7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1158 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1159 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[4] ; fpz8_cpu_v1:inst|IRQ0[4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1160 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[5] ; fpz8_cpu_v1:inst|IRQ0[5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1161 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[6] ; fpz8_cpu_v1:inst|IRQ0[6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1162 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[1] ; fpz8_cpu_v1:inst|IRQ0[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1163 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[3] ; fpz8_cpu_v1:inst|IRQ0[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1164 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[2] ; fpz8_cpu_v1:inst|IRQ0[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1165 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|IRQ0[0] ; fpz8_cpu_v1:inst|IRQ0[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1166 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1167 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDW2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1168 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; fpz8_cpu_v1:inst|CPU_FLAGS.V ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1169 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; fpz8_cpu_v1:inst|CPU_FLAGS.S ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1170 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1171 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1172 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1173 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1174 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1175 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1176 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1177 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1178 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1179 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1180 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1181 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1182 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1183 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1184 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1185 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1186 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1187 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1188 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1189 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1190 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1191 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1192 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1193 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1194 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[6][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1195 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1196 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1197 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1198 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1199 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1200 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1201 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1202 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; fpz8_cpu_v1:inst|\main:TEMP_OP[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1203 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; fpz8_cpu_v1:inst|\main:TEMP_OP[3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1204 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1205 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1206 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[0][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1207 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[1][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1208 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IMTOIRR ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1209 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_IRRS ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1210 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|DBG_TX ; fpz8_cpu_v1:inst|DBG_TX ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1211 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[8] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1212 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1213 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1214 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1215 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BITTIMETX[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1216 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.BAUDPRE[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1217 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; fpz8_cpu_v1:inst|\main:DBG_UART.DBG_SYNC ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1218 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1219 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; fpz8_cpu_v1:inst|\main:OCDCR.DBGACK ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1220 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_REV2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1221 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_SEND_PC2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1222 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1223 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1224 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1225 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK3 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK3 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1226 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; fpz8_cpu_v1:inst|\main:DBG_UART.RX_DATA[6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1227 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1228 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; fpz8_cpu_v1:inst|CPU_FLAGS.C ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1229 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][3] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1230 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK1 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STACK1 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1231 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][2] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1232 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][7] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1233 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][5] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1234 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][4] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1235 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][6] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1236 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][1] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1237 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[2][0] ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1238 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR4 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_XRRTORR4 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1239 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_LDPTOIM2 ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1240 |
|
|
; 0.166 ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; fpz8_cpu_v1:inst|ALU_FLAGS.H ; CLOCK ; CLOCK ; 0.000 ; 0.037 ; 0.307 ;
|
| 1241 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[0] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1242 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[2] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1243 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[1] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1244 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; fpz8_cpu_v1:inst|\main:DBG_UART.RXCNT[3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1245 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; fpz8_cpu_v1:inst|\main:DBG_CMD.DBG_EXEC2 ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1246 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_HALTED ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1247 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_ILLEGAL ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1248 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; fpz8_cpu_v1:inst|\main:CPU_STATE.CPU_STORE ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1249 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; fpz8_cpu_v1:inst|\main:OCDCR.RST ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1250 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[4][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1251 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1252 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][5] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1253 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[5][5] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1254 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[3][3] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1255 |
|
|
; 0.167 ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; fpz8_cpu_v1:inst|\main:IQUEUE.QUEUE[7][2] ; CLOCK ; CLOCK ; 0.000 ; 0.036 ; 0.307 ;
|
| 1256 |
|
|
+-------+-----------------------------------------------+-----------------------------------------------+--------------+-------------+--------------+------------+------------+
|
| 1257 |
|
|
|
| 1258 |
|
|
|
| 1259 |
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1260 |
|
|
; Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK' ;
|
| 1261 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 1262 |
|
|
; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
|
| 1263 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 1264 |
|
|
; -3.000 ; 1.000 ; 4.000 ; Port Rate ; CLOCK ; Rise ; CLOCK ;
|
| 1265 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 1266 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 1267 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 1268 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 1269 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 1270 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram1:File_Registers|altsyncram:altsyncram_component|altsyncram_t2b1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 1271 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|address_reg_a[0] ;
|
| 1272 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_address_reg0 ;
|
| 1273 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_datain_reg0 ;
|
| 1274 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a0~porta_we_reg ;
|
| 1275 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_address_reg0 ;
|
| 1276 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_datain_reg0 ;
|
| 1277 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a10~porta_we_reg ;
|
| 1278 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_address_reg0 ;
|
| 1279 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_datain_reg0 ;
|
| 1280 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a11~porta_we_reg ;
|
| 1281 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_address_reg0 ;
|
| 1282 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_datain_reg0 ;
|
| 1283 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a12~porta_we_reg ;
|
| 1284 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_address_reg0 ;
|
| 1285 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_datain_reg0 ;
|
| 1286 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a13~porta_we_reg ;
|
| 1287 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_address_reg0 ;
|
| 1288 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_datain_reg0 ;
|
| 1289 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a14~porta_we_reg ;
|
| 1290 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_address_reg0 ;
|
| 1291 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_datain_reg0 ;
|
| 1292 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a15~porta_we_reg ;
|
| 1293 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_address_reg0 ;
|
| 1294 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_datain_reg0 ;
|
| 1295 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a1~porta_we_reg ;
|
| 1296 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_address_reg0 ;
|
| 1297 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_datain_reg0 ;
|
| 1298 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a2~porta_we_reg ;
|
| 1299 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_address_reg0 ;
|
| 1300 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_datain_reg0 ;
|
| 1301 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a3~porta_we_reg ;
|
| 1302 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_address_reg0 ;
|
| 1303 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_datain_reg0 ;
|
| 1304 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a4~porta_we_reg ;
|
| 1305 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_address_reg0 ;
|
| 1306 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_datain_reg0 ;
|
| 1307 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a5~porta_we_reg ;
|
| 1308 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_address_reg0 ;
|
| 1309 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_datain_reg0 ;
|
| 1310 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a6~porta_we_reg ;
|
| 1311 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_address_reg0 ;
|
| 1312 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_datain_reg0 ;
|
| 1313 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a7~porta_we_reg ;
|
| 1314 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_address_reg0 ;
|
| 1315 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_datain_reg0 ;
|
| 1316 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a8~porta_we_reg ;
|
| 1317 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_address_reg0 ;
|
| 1318 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_datain_reg0 ;
|
| 1319 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Fall ; altsyncram2:Program_Memory|altsyncram:altsyncram_component|altsyncram_7le1:auto_generated|ram_block1a9~porta_we_reg ;
|
| 1320 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.C ;
|
| 1321 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.H ;
|
| 1322 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.S ;
|
| 1323 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.V ;
|
| 1324 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|ALU_FLAGS.Z ;
|
| 1325 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.C ;
|
| 1326 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.D ;
|
| 1327 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F1 ;
|
| 1328 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.F2 ;
|
| 1329 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.H ;
|
| 1330 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.S ;
|
| 1331 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.V ;
|
| 1332 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|CPU_FLAGS.Z ;
|
| 1333 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|DBG_TX ;
|
| 1334 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[0] ;
|
| 1335 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[1] ;
|
| 1336 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[2] ;
|
| 1337 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|FCTL[7] ;
|
| 1338 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[0] ;
|
| 1339 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[10] ;
|
| 1340 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[11] ;
|
| 1341 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[12] ;
|
| 1342 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[13] ;
|
| 1343 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[1] ;
|
| 1344 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[2] ;
|
| 1345 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[3] ;
|
| 1346 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[4] ;
|
| 1347 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[5] ;
|
| 1348 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[6] ;
|
| 1349 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[7] ;
|
| 1350 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[8] ;
|
| 1351 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IAB[9] ;
|
| 1352 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[0] ;
|
| 1353 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[1] ;
|
| 1354 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[2] ;
|
| 1355 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[3] ;
|
| 1356 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[4] ;
|
| 1357 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[5] ;
|
| 1358 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[6] ;
|
| 1359 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENH[7] ;
|
| 1360 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[0] ;
|
| 1361 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[1] ;
|
| 1362 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[2] ;
|
| 1363 |
|
|
; -1.000 ; 1.000 ; 2.000 ; Min Period ; CLOCK ; Rise ; fpz8_cpu_v1:inst|IRQ0ENL[3] ;
|
| 1364 |
|
|
+--------+--------------+----------------+------------+-------+------------+----------------------------------------------------------------------------------------------------------------------------+
|
| 1365 |
|
|
|
| 1366 |
|
|
|
| 1367 |
|
|
+-----------------------------------------------------------------------+
|
| 1368 |
|
|
; Setup Times ;
|
| 1369 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1370 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1371 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1372 |
|
|
; DBG_RX ; CLOCK ; 0.157 ; 0.449 ; Rise ; CLOCK ;
|
| 1373 |
|
|
; RESET ; CLOCK ; 3.725 ; 3.615 ; Rise ; CLOCK ;
|
| 1374 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1375 |
|
|
|
| 1376 |
|
|
|
| 1377 |
|
|
+-------------------------------------------------------------------------+
|
| 1378 |
|
|
; Hold Times ;
|
| 1379 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1380 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1381 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1382 |
|
|
; DBG_RX ; CLOCK ; 0.057 ; -0.247 ; Rise ; CLOCK ;
|
| 1383 |
|
|
; RESET ; CLOCK ; -0.714 ; -0.959 ; Rise ; CLOCK ;
|
| 1384 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1385 |
|
|
|
| 1386 |
|
|
|
| 1387 |
|
|
+-----------------------------------------------------------------------+
|
| 1388 |
|
|
; Clock to Output Times ;
|
| 1389 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1390 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1391 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1392 |
|
|
; DBG_TX ; CLOCK ; 3.352 ; 3.451 ; Rise ; CLOCK ;
|
| 1393 |
|
|
; PAOUT[*] ; CLOCK ; 4.455 ; 4.617 ; Rise ; CLOCK ;
|
| 1394 |
|
|
; PAOUT[0] ; CLOCK ; 3.563 ; 3.689 ; Rise ; CLOCK ;
|
| 1395 |
|
|
; PAOUT[1] ; CLOCK ; 3.637 ; 3.749 ; Rise ; CLOCK ;
|
| 1396 |
|
|
; PAOUT[2] ; CLOCK ; 3.520 ; 3.637 ; Rise ; CLOCK ;
|
| 1397 |
|
|
; PAOUT[3] ; CLOCK ; 3.481 ; 3.595 ; Rise ; CLOCK ;
|
| 1398 |
|
|
; PAOUT[4] ; CLOCK ; 4.455 ; 4.617 ; Rise ; CLOCK ;
|
| 1399 |
|
|
; PAOUT[5] ; CLOCK ; 3.422 ; 3.498 ; Rise ; CLOCK ;
|
| 1400 |
|
|
; PAOUT[6] ; CLOCK ; 3.446 ; 3.545 ; Rise ; CLOCK ;
|
| 1401 |
|
|
; PAOUT[7] ; CLOCK ; 3.463 ; 3.555 ; Rise ; CLOCK ;
|
| 1402 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1403 |
|
|
|
| 1404 |
|
|
|
| 1405 |
|
|
+-----------------------------------------------------------------------+
|
| 1406 |
|
|
; Minimum Clock to Output Times ;
|
| 1407 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1408 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1409 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1410 |
|
|
; DBG_TX ; CLOCK ; 3.247 ; 3.343 ; Rise ; CLOCK ;
|
| 1411 |
|
|
; PAOUT[*] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;
|
| 1412 |
|
|
; PAOUT[0] ; CLOCK ; 3.450 ; 3.572 ; Rise ; CLOCK ;
|
| 1413 |
|
|
; PAOUT[1] ; CLOCK ; 3.521 ; 3.630 ; Rise ; CLOCK ;
|
| 1414 |
|
|
; PAOUT[2] ; CLOCK ; 3.408 ; 3.522 ; Rise ; CLOCK ;
|
| 1415 |
|
|
; PAOUT[3] ; CLOCK ; 3.372 ; 3.482 ; Rise ; CLOCK ;
|
| 1416 |
|
|
; PAOUT[4] ; CLOCK ; 4.341 ; 4.500 ; Rise ; CLOCK ;
|
| 1417 |
|
|
; PAOUT[5] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;
|
| 1418 |
|
|
; PAOUT[6] ; CLOCK ; 3.336 ; 3.431 ; Rise ; CLOCK ;
|
| 1419 |
|
|
; PAOUT[7] ; CLOCK ; 3.352 ; 3.441 ; Rise ; CLOCK ;
|
| 1420 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1421 |
|
|
|
| 1422 |
|
|
|
| 1423 |
|
|
---------------------------------------------
|
| 1424 |
|
|
; Fast 1200mV 0C Model Metastability Report ;
|
| 1425 |
|
|
---------------------------------------------
|
| 1426 |
|
|
No synchronizer chains to report.
|
| 1427 |
|
|
|
| 1428 |
|
|
|
| 1429 |
|
|
+---------------------------------------------------------------------------------+
|
| 1430 |
|
|
; Multicorner Timing Analysis Summary ;
|
| 1431 |
|
|
+------------------+-----------+-------+----------+---------+---------------------+
|
| 1432 |
|
|
; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ;
|
| 1433 |
|
|
+------------------+-----------+-------+----------+---------+---------------------+
|
| 1434 |
|
|
; Worst-case Slack ; -26.441 ; 0.166 ; N/A ; N/A ; -3.201 ;
|
| 1435 |
|
|
; CLOCK ; -26.441 ; 0.166 ; N/A ; N/A ; -3.201 ;
|
| 1436 |
|
|
; Design-wide TNS ; -8505.086 ; 0.0 ; 0.0 ; 0.0 ; -910.432 ;
|
| 1437 |
|
|
; CLOCK ; -8505.086 ; 0.000 ; N/A ; N/A ; -910.432 ;
|
| 1438 |
|
|
+------------------+-----------+-------+----------+---------+---------------------+
|
| 1439 |
|
|
|
| 1440 |
|
|
|
| 1441 |
|
|
+-----------------------------------------------------------------------+
|
| 1442 |
|
|
; Setup Times ;
|
| 1443 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1444 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1445 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1446 |
|
|
; DBG_RX ; CLOCK ; 0.279 ; 0.565 ; Rise ; CLOCK ;
|
| 1447 |
|
|
; RESET ; CLOCK ; 7.699 ; 8.228 ; Rise ; CLOCK ;
|
| 1448 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1449 |
|
|
|
| 1450 |
|
|
|
| 1451 |
|
|
+-------------------------------------------------------------------------+
|
| 1452 |
|
|
; Hold Times ;
|
| 1453 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1454 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1455 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1456 |
|
|
; DBG_RX ; CLOCK ; 0.206 ; -0.008 ; Rise ; CLOCK ;
|
| 1457 |
|
|
; RESET ; CLOCK ; -0.714 ; -0.959 ; Rise ; CLOCK ;
|
| 1458 |
|
|
+-----------+------------+--------+--------+------------+-----------------+
|
| 1459 |
|
|
|
| 1460 |
|
|
|
| 1461 |
|
|
+-----------------------------------------------------------------------+
|
| 1462 |
|
|
; Clock to Output Times ;
|
| 1463 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1464 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1465 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1466 |
|
|
; DBG_TX ; CLOCK ; 7.165 ; 7.071 ; Rise ; CLOCK ;
|
| 1467 |
|
|
; PAOUT[*] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;
|
| 1468 |
|
|
; PAOUT[0] ; CLOCK ; 7.699 ; 7.560 ; Rise ; CLOCK ;
|
| 1469 |
|
|
; PAOUT[1] ; CLOCK ; 7.832 ; 7.656 ; Rise ; CLOCK ;
|
| 1470 |
|
|
; PAOUT[2] ; CLOCK ; 7.578 ; 7.452 ; Rise ; CLOCK ;
|
| 1471 |
|
|
; PAOUT[3] ; CLOCK ; 7.472 ; 7.354 ; Rise ; CLOCK ;
|
| 1472 |
|
|
; PAOUT[4] ; CLOCK ; 9.070 ; 9.000 ; Rise ; CLOCK ;
|
| 1473 |
|
|
; PAOUT[5] ; CLOCK ; 7.332 ; 7.221 ; Rise ; CLOCK ;
|
| 1474 |
|
|
; PAOUT[6] ; CLOCK ; 7.464 ; 7.309 ; Rise ; CLOCK ;
|
| 1475 |
|
|
; PAOUT[7] ; CLOCK ; 7.445 ; 7.306 ; Rise ; CLOCK ;
|
| 1476 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1477 |
|
|
|
| 1478 |
|
|
|
| 1479 |
|
|
+-----------------------------------------------------------------------+
|
| 1480 |
|
|
; Minimum Clock to Output Times ;
|
| 1481 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1482 |
|
|
; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
|
| 1483 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1484 |
|
|
; DBG_TX ; CLOCK ; 3.247 ; 3.343 ; Rise ; CLOCK ;
|
| 1485 |
|
|
; PAOUT[*] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;
|
| 1486 |
|
|
; PAOUT[0] ; CLOCK ; 3.450 ; 3.572 ; Rise ; CLOCK ;
|
| 1487 |
|
|
; PAOUT[1] ; CLOCK ; 3.521 ; 3.630 ; Rise ; CLOCK ;
|
| 1488 |
|
|
; PAOUT[2] ; CLOCK ; 3.408 ; 3.522 ; Rise ; CLOCK ;
|
| 1489 |
|
|
; PAOUT[3] ; CLOCK ; 3.372 ; 3.482 ; Rise ; CLOCK ;
|
| 1490 |
|
|
; PAOUT[4] ; CLOCK ; 4.341 ; 4.500 ; Rise ; CLOCK ;
|
| 1491 |
|
|
; PAOUT[5] ; CLOCK ; 3.312 ; 3.386 ; Rise ; CLOCK ;
|
| 1492 |
|
|
; PAOUT[6] ; CLOCK ; 3.336 ; 3.431 ; Rise ; CLOCK ;
|
| 1493 |
|
|
; PAOUT[7] ; CLOCK ; 3.352 ; 3.441 ; Rise ; CLOCK ;
|
| 1494 |
|
|
+-----------+------------+-------+-------+------------+-----------------+
|
| 1495 |
|
|
|
| 1496 |
|
|
|
| 1497 |
|
|
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1498 |
|
|
; Board Trace Model Assignments ;
|
| 1499 |
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
|
| 1500 |
|
|
; Pin ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ;
|
| 1501 |
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
|
| 1502 |
|
|
; DBG_TX ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1503 |
|
|
; PAOUT[7] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1504 |
|
|
; PAOUT[6] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1505 |
|
|
; PAOUT[5] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1506 |
|
|
; PAOUT[4] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1507 |
|
|
; PAOUT[3] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1508 |
|
|
; PAOUT[2] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1509 |
|
|
; PAOUT[1] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1510 |
|
|
; PAOUT[0] ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1511 |
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1512 |
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 in ; 0 H/in ; 0 F/in ; short ; - ; open ; open ; open ; 0 in ; 0 H/in ; 0 F/in ; short ; open ; open ; open ; 0 V ; - ;
|
| 1513 |
|
|
+---------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+
|
| 1514 |
|
|
|
| 1515 |
|
|
|
| 1516 |
|
|
+----------------------------------------------------------------------------+
|
| 1517 |
|
|
; Input Transition Times ;
|
| 1518 |
|
|
+-------------------------+--------------+-----------------+-----------------+
|
| 1519 |
|
|
; Pin ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
|
| 1520 |
|
|
+-------------------------+--------------+-----------------+-----------------+
|
| 1521 |
|
|
; CLOCK ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1522 |
|
|
; RESET ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1523 |
|
|
; DBG_RX ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1524 |
|
|
; ~ALTERA_ASDO_DATA1~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1525 |
|
|
; ~ALTERA_FLASH_nCE_nCSO~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1526 |
|
|
; ~ALTERA_DATA0~ ; 2.5 V ; 2000 ps ; 2000 ps ;
|
| 1527 |
|
|
+-------------------------+--------------+-----------------+-----------------+
|
| 1528 |
|
|
|
| 1529 |
|
|
|
| 1530 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1531 |
|
|
; Slow Corner Signal Integrity Metrics ;
|
| 1532 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1533 |
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
| 1534 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1535 |
|
|
; DBG_TX ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;
|
| 1536 |
|
|
; PAOUT[7] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;
|
| 1537 |
|
|
; PAOUT[6] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;
|
| 1538 |
|
|
; PAOUT[5] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.35 V ; -0.00735 V ; 0.126 V ; 0.011 V ; 4.7e-010 s ; 4.63e-010 s ; Yes ; Yes ;
|
| 1539 |
|
|
; PAOUT[4] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.33 V ; -0.00219 V ; 0.108 V ; 0.043 V ; 3.76e-009 s ; 3.48e-009 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.33 V ; -0.00219 V ; 0.108 V ; 0.043 V ; 3.76e-009 s ; 3.48e-009 s ; Yes ; Yes ;
|
| 1540 |
|
|
; PAOUT[3] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;
|
| 1541 |
|
|
; PAOUT[2] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;
|
| 1542 |
|
|
; PAOUT[1] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;
|
| 1543 |
|
|
; PAOUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ; 2.32 V ; 1.91e-007 V ; 2.34 V ; -0.00803 V ; 0.14 V ; 0.045 V ; 6.89e-010 s ; 6.56e-010 s ; Yes ; Yes ;
|
| 1544 |
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 1.53e-007 V ; 2.35 V ; -0.00333 V ; 0.096 V ; 0.006 V ; 4.5e-010 s ; 3.85e-010 s ; Yes ; Yes ; 2.32 V ; 1.53e-007 V ; 2.35 V ; -0.00333 V ; 0.096 V ; 0.006 V ; 4.5e-010 s ; 3.85e-010 s ; Yes ; Yes ;
|
| 1545 |
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.32 V ; 2.51e-007 V ; 2.34 V ; -0.00726 V ; 0.108 V ; 0.026 V ; 6.58e-010 s ; 8.2e-010 s ; Yes ; Yes ; 2.32 V ; 2.51e-007 V ; 2.34 V ; -0.00726 V ; 0.108 V ; 0.026 V ; 6.58e-010 s ; 8.2e-010 s ; Yes ; Yes ;
|
| 1546 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1547 |
|
|
|
| 1548 |
|
|
|
| 1549 |
|
|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
| 1550 |
|
|
; Fast Corner Signal Integrity Metrics ;
|
| 1551 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1552 |
|
|
; Pin ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
|
| 1553 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1554 |
|
|
; DBG_TX ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;
|
| 1555 |
|
|
; PAOUT[7] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;
|
| 1556 |
|
|
; PAOUT[6] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;
|
| 1557 |
|
|
; PAOUT[5] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ; 2.62 V ; 2.7e-008 V ; 2.72 V ; -0.0401 V ; 0.163 V ; 0.091 V ; 2.71e-010 s ; 2.61e-010 s ; Yes ; Yes ;
|
| 1558 |
|
|
; PAOUT[4] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.64 V ; -0.0118 V ; 0.201 V ; 0.173 V ; 2.38e-009 s ; 2.19e-009 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.64 V ; -0.0118 V ; 0.201 V ; 0.173 V ; 2.38e-009 s ; 2.19e-009 s ; No ; Yes ;
|
| 1559 |
|
|
; PAOUT[3] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;
|
| 1560 |
|
|
; PAOUT[2] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;
|
| 1561 |
|
|
; PAOUT[1] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;
|
| 1562 |
|
|
; PAOUT[0] ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ; 2.62 V ; 2.7e-008 V ; 2.71 V ; -0.0352 V ; 0.147 V ; 0.066 V ; 4.51e-010 s ; 4.15e-010 s ; No ; Yes ;
|
| 1563 |
|
|
; ~ALTERA_DCLK~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 2.2e-008 V ; 2.74 V ; -0.061 V ; 0.159 V ; 0.078 V ; 2.7e-010 s ; 2.2e-010 s ; No ; Yes ; 2.62 V ; 2.2e-008 V ; 2.74 V ; -0.061 V ; 0.159 V ; 0.078 V ; 2.7e-010 s ; 2.2e-010 s ; No ; Yes ;
|
| 1564 |
|
|
; ~ALTERA_nCEO~ ; 2.5 V ; 0 s ; 0 s ; 2.62 V ; 3.52e-008 V ; 2.7 V ; -0.012 V ; 0.274 V ; 0.034 V ; 3.18e-010 s ; 4.96e-010 s ; No ; Yes ; 2.62 V ; 3.52e-008 V ; 2.7 V ; -0.012 V ; 0.274 V ; 0.034 V ; 3.18e-010 s ; 4.96e-010 s ; No ; Yes ;
|
| 1565 |
|
|
+---------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
|
| 1566 |
|
|
|
| 1567 |
|
|
|
| 1568 |
|
|
+-----------------------------------------------------------------------+
|
| 1569 |
|
|
; Setup Transfers ;
|
| 1570 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1571 |
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
| 1572 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1573 |
|
|
; CLOCK ; CLOCK ; > 2147483647 ; 15094538 ; 339 ; 0 ;
|
| 1574 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1575 |
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
| 1576 |
|
|
|
| 1577 |
|
|
|
| 1578 |
|
|
+-----------------------------------------------------------------------+
|
| 1579 |
|
|
; Hold Transfers ;
|
| 1580 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1581 |
|
|
; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
|
| 1582 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1583 |
|
|
; CLOCK ; CLOCK ; > 2147483647 ; 15094538 ; 339 ; 0 ;
|
| 1584 |
|
|
+------------+----------+--------------+----------+----------+----------+
|
| 1585 |
|
|
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
|
| 1586 |
|
|
|
| 1587 |
|
|
|
| 1588 |
|
|
---------------
|
| 1589 |
|
|
; Report TCCS ;
|
| 1590 |
|
|
---------------
|
| 1591 |
|
|
No dedicated SERDES Transmitter circuitry present in device or used in design
|
| 1592 |
|
|
|
| 1593 |
|
|
|
| 1594 |
|
|
---------------
|
| 1595 |
|
|
; Report RSKM ;
|
| 1596 |
|
|
---------------
|
| 1597 |
|
|
No dedicated SERDES Receiver circuitry present in device or used in design
|
| 1598 |
|
|
|
| 1599 |
|
|
|
| 1600 |
|
|
+------------------------------------------------+
|
| 1601 |
|
|
; Unconstrained Paths ;
|
| 1602 |
|
|
+---------------------------------+-------+------+
|
| 1603 |
|
|
; Property ; Setup ; Hold ;
|
| 1604 |
|
|
+---------------------------------+-------+------+
|
| 1605 |
|
|
; Illegal Clocks ; 0 ; 0 ;
|
| 1606 |
|
|
; Unconstrained Clocks ; 0 ; 0 ;
|
| 1607 |
|
|
; Unconstrained Input Ports ; 2 ; 2 ;
|
| 1608 |
|
|
; Unconstrained Input Port Paths ; 494 ; 494 ;
|
| 1609 |
|
|
; Unconstrained Output Ports ; 9 ; 9 ;
|
| 1610 |
|
|
; Unconstrained Output Port Paths ; 9 ; 9 ;
|
| 1611 |
|
|
+---------------------------------+-------+------+
|
| 1612 |
|
|
|
| 1613 |
|
|
|
| 1614 |
|
|
+------------------------------------+
|
| 1615 |
|
|
; TimeQuest Timing Analyzer Messages ;
|
| 1616 |
|
|
+------------------------------------+
|
| 1617 |
|
|
Info: *******************************************************************
|
| 1618 |
|
|
Info: Running Quartus II TimeQuest Timing Analyzer
|
| 1619 |
|
|
Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition
|
| 1620 |
|
|
Info: Processing started: Fri Nov 11 10:25:00 2016
|
| 1621 |
|
|
Info: Command: quartus_sta FPz8 -c FPz8_Cyclone_IV
|
| 1622 |
|
|
Info: qsta_default_script.tcl version: #1
|
| 1623 |
|
|
Info: Core supply voltage is 1.2V
|
| 1624 |
|
|
Info: Low junction temperature is 0 degrees C
|
| 1625 |
|
|
Info: High junction temperature is 85 degrees C
|
| 1626 |
|
|
Info: Reading SDC File: 'FPz8_Cyclone_IV.out.sdc'
|
| 1627 |
|
|
Info: Deriving Clocks
|
| 1628 |
|
|
Info: create_clock -period 1.000 -name CLOCK CLOCK
|
| 1629 |
|
|
Info: Clock uncertainty calculation is delayed until the next update_timing_netlist call
|
| 1630 |
|
|
Info: Deriving Clock Uncertainty
|
| 1631 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1632 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1633 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1634 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1635 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1636 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1637 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1638 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1639 |
|
|
Info: Analyzing Slow 1200mV 85C Model
|
| 1640 |
|
|
Critical Warning: Timing requirements not met
|
| 1641 |
|
|
Info: Worst-case setup slack is -26.441
|
| 1642 |
|
|
Info: Slack End Point TNS Clock
|
| 1643 |
|
|
Info: ========= ============= =====================
|
| 1644 |
|
|
Info: -26.441 -8505.086 CLOCK
|
| 1645 |
|
|
Info: Worst-case hold slack is 0.432
|
| 1646 |
|
|
Info: Slack End Point TNS Clock
|
| 1647 |
|
|
Info: ========= ============= =====================
|
| 1648 |
|
|
Info: 0.432 0.000 CLOCK
|
| 1649 |
|
|
Info: No Recovery paths to report
|
| 1650 |
|
|
Info: No Removal paths to report
|
| 1651 |
|
|
Info: Worst-case minimum pulse width slack is -3.201
|
| 1652 |
|
|
Info: Slack End Point TNS Clock
|
| 1653 |
|
|
Info: ========= ============= =====================
|
| 1654 |
|
|
Info: -3.201 -910.432 CLOCK
|
| 1655 |
|
|
Info: Analyzing Slow 1200mV 0C Model
|
| 1656 |
|
|
Info: Started post-fitting delay annotation
|
| 1657 |
|
|
Warning: Timing characteristics of device EP4CE6E22C8 are preliminary
|
| 1658 |
|
|
Info: Delay annotation completed successfully
|
| 1659 |
|
|
Info: Deriving Clock Uncertainty
|
| 1660 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1661 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1662 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1663 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1664 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1665 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1666 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1667 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1668 |
|
|
Critical Warning: Timing requirements not met
|
| 1669 |
|
|
Info: Worst-case setup slack is -24.794
|
| 1670 |
|
|
Info: Slack End Point TNS Clock
|
| 1671 |
|
|
Info: ========= ============= =====================
|
| 1672 |
|
|
Info: -24.794 -7986.414 CLOCK
|
| 1673 |
|
|
Info: Worst-case hold slack is 0.380
|
| 1674 |
|
|
Info: Slack End Point TNS Clock
|
| 1675 |
|
|
Info: ========= ============= =====================
|
| 1676 |
|
|
Info: 0.380 0.000 CLOCK
|
| 1677 |
|
|
Info: No Recovery paths to report
|
| 1678 |
|
|
Info: No Removal paths to report
|
| 1679 |
|
|
Info: Worst-case minimum pulse width slack is -3.201
|
| 1680 |
|
|
Info: Slack End Point TNS Clock
|
| 1681 |
|
|
Info: ========= ============= =====================
|
| 1682 |
|
|
Info: -3.201 -910.432 CLOCK
|
| 1683 |
|
|
Info: Analyzing Fast 1200mV 0C Model
|
| 1684 |
|
|
Info: Started post-fitting delay annotation
|
| 1685 |
|
|
Warning: Timing characteristics of device EP4CE6E22C8 are preliminary
|
| 1686 |
|
|
Info: Delay annotation completed successfully
|
| 1687 |
|
|
Info: Deriving Clock Uncertainty
|
| 1688 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1689 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1690 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -setup 0.020
|
| 1691 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -setup 0.020
|
| 1692 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1693 |
|
|
Info: set_clock_uncertainty -rise_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1694 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -rise_to [get_clocks {CLOCK}] -hold 0.020
|
| 1695 |
|
|
Info: set_clock_uncertainty -fall_from [get_clocks {CLOCK}] -fall_to [get_clocks {CLOCK}] -hold 0.020
|
| 1696 |
|
|
Critical Warning: Timing requirements not met
|
| 1697 |
|
|
Info: Worst-case setup slack is -10.913
|
| 1698 |
|
|
Info: Slack End Point TNS Clock
|
| 1699 |
|
|
Info: ========= ============= =====================
|
| 1700 |
|
|
Info: -10.913 -3387.206 CLOCK
|
| 1701 |
|
|
Info: Worst-case hold slack is 0.166
|
| 1702 |
|
|
Info: Slack End Point TNS Clock
|
| 1703 |
|
|
Info: ========= ============= =====================
|
| 1704 |
|
|
Info: 0.166 0.000 CLOCK
|
| 1705 |
|
|
Info: No Recovery paths to report
|
| 1706 |
|
|
Info: No Removal paths to report
|
| 1707 |
|
|
Info: Worst-case minimum pulse width slack is -3.000
|
| 1708 |
|
|
Info: Slack End Point TNS Clock
|
| 1709 |
|
|
Info: ========= ============= =====================
|
| 1710 |
|
|
Info: -3.000 -587.993 CLOCK
|
| 1711 |
|
|
Info: Design is not fully constrained for setup requirements
|
| 1712 |
|
|
Info: Design is not fully constrained for hold requirements
|
| 1713 |
|
|
Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 5 warnings
|
| 1714 |
|
|
Info: Peak virtual memory: 258 megabytes
|
| 1715 |
|
|
Info: Processing ended: Fri Nov 11 10:25:14 2016
|
| 1716 |
|
|
Info: Elapsed time: 00:00:14
|
| 1717 |
|
|
Info: Total CPU time (on all processors): 00:00:11
|
| 1718 |
|
|
|
| 1719 |
|
|
|
