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[/] [System09/] [trunk/] [rtl/] [VHDL/] [vdu8.vhd] - Blame information for rev 99

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1 99 davidgb
--===========================================================================--
2
--                                                                           --
3
--  vdu8.vhd - Synthesizable Colour Video Display Unit for System09          --
4
--                                                                           --
5
--===========================================================================--
6
--
7
--  File name      : vdu8.vhd
8
--
9
--  Purpose        : Implements a text based Colour Video Display Unit for System09
10
--                   Supports 2KByte Text buffer and 2KByte Attribute memory
11
--                   Displays 80 characters across by 25 character rows
12
--                   Characters are 8 pixels across x 16 lines down.
13
--                   Character attribute bita for foreground and backgrond colour
14
--                   1 bit for each Blue Green and Red signal
15
--                   Supports 2 x 8 chunky graphics character mode.
16
--                   Uses Generic arguments for setting the video synchronization timing.
17
--                  
18
--  Dependencies   : ieee.Std_Logic_1164
19
--                   ieee.std_logic_unsigned
20
--                   ieee.std_logic_arith
21
--                   ieee.numeric_std
22
--
23
--  Uses           : ram_2k (ram2k_b16.vhd)             2KByte Character & Attribute buffer
24
--                   char_rom (char_rom2k_b16.vhd)      2KByte Character Generator ROM 
25
--
26
--  Author         : John E. Kent
27
--
28
--  Email          : dilbert57@opencores.org      
29
--
30
--  Web            : http://opencores.org/project,system09
31
--
32
--  Description    : Display Timing:
33
--                       800 pixels / line
34
--                       446 lines / frame
35
--                       None interlaced
36
--                       25MHz pixel clock implies 
37
--                       31.25 KHz line rate
38
--                       70.067 Hz frame rate   
39
--                       Timing settable by generics.
40
--
41
--                   Display Size:
42
--                       80 characters across
43
--                       25 characters down.
44
--
45
--                   Character Size:
46
--                        8 horizontal pixels across
47
--                       16 vertical scan lines down (2 scan lines/row)
48
--
49
--                   Registers:
50
--                   Base + 0 ASCII character register
51
--                            Writing to this register writes an 8 bit byte 
52
--                            into the text buffer at the specified cursor position
53
--                            Text Mode: ASCII Character (0 to 127)
54
--                            Chunky Graphics Mode: B0 B1 (0 to 255)
55
--                                                  B2 B3
56
--                                                  B4 B5
57
--                                                  B6 B7
58
--                   Base + 1 Attibute bit (0 to 255)
59
--                            Writing to the register writes an 8 bit byte 
60
--                            into the attribute buffer at the specified cursor position
61
--                            B7 - 0 => Text Mode / 1 => Chunky Graphics Mode
62
--                            B6 - 1 => Character Background Blue
63
--                            B5 - 1 => Character Background Green
64
--                            B4 - 1 => Character Background Red
65
--                            B3 - 1 => Character Background & Foreground Alternates
66
--                            B2 - 1 => Character Foreground Blue
67
--                            B1 - 1 => Character Foreground Green
68
--                            B0 - 1 => Character Foreground Red
69
--                   Base + 2 Cursor Horizontal Position (0 to 79)
70
--                   Base + 3 Cusror Vertical Position (0 to 24)
71
--                   Base + 4 Vertical Scroll Offset (0 to 24)
72
--                            Scrolls the display up by the specified number of character rows
73
--
74
--  Video Timing :
75
--
76
--  Horizontal 800 Pixels/ 25MHz Pixel Clock = 32usec Line period = 31.25 KHz Line Frequency
77
--  /--------------------------\_____________/---------------\______________/
78
--      640 Pixels Display       16 Pixel FP    96 Pixel HS     48 Pixel BP
79
--    
80
--      VGA_CLK_FREQ           : integer := 25000000; -- HZ
81
--           VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us (0.94us)
82
--           VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us (3.77us)
83
--           VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us (1.89us)
84
--           VGA_PIX_PER_CHAR       : integer := 8;  -- PIXELS 0.32us
85
--           VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
86
--
87
--  Vertical 446 Lines * 32 usec Line rate = 14.272ms Frame Period = 70.07Hz Frame frequency  
88
--  /---------------------------\____________/---------------\______________/
89
--      400 Line Display          10 Line FP     2 Line VS      34 Line BP
90
--
91
--           VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
92
--           VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
93
--           VGA_VER_BACK_PORCH     : integer := 34; -- LINES 1.088ms
94
--           VGA_LIN_PER_CHAR       : integer := 16; -- LINES 0.512ms
95
--           VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
96
--
97
--  Copyright (C) 2003 - 2010 John Kent
98
--
99
--  This program is free software: you can redistribute it and/or modify
100
--  it under the terms of the GNU General Public License as published by
101
--  the Free Software Foundation, either version 3 of the License, or
102
--  (at your option) any later version.
103
--
104
--  This program is distributed in the hope that it will be useful,
105
--  but WITHOUT ANY WARRANTY; without even the implied warranty of
106
--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
107
--  GNU General Public License for more details.
108
--
109
--  You should have received a copy of the GNU General Public License
110
--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
111
--
112
--===========================================================================--
113
--                                                                           --
114
--                              Revision  History                            --
115
--                                                                           --
116
--===========================================================================--
117
--
118
-- Version Author      Date        Changes
119
--
120
-- 0.1     John Kent   2004-09-03  Initial release
121
--
122
-- 0.2     Bert Cuzeau 2007-01-16  Modified by for compliance and code cleanliness
123
--                                 The effort is not over.
124
--                                 There are still signal initialized, which is BAD.
125
--
126
-- 0.3     John Kent   2007-02-07  Added generics for VGA Timing
127
--
128
-- 0.4     John Kent   2010-07-03  Added GPL notice. 
129
--                                 Updated description.
130
--                                 Rearranged Video Timing
131
--
132
 
133
Library IEEE;
134
  use IEEE.std_logic_1164.all;
135
  use IEEE.numeric_std.all;
136
Library unisim;
137
  use unisim.vcomponents.all;
138
 
139
Entity vdu8 is
140
  generic(
141
        VGA_CLK_FREQ           : integer := 25000000; -- HZ
142
             VGA_HOR_CHARS          : integer := 80; -- CHARACTERS 25.6us
143
             VGA_HOR_CHAR_PIXELS    : integer := 8;  -- PIXELS 0.32us
144
             VGA_HOR_FRONT_PORCH    : integer := 16; -- PIXELS 0.64us
145
             VGA_HOR_SYNC           : integer := 96; -- PIXELS 3.84us
146
             VGA_HOR_BACK_PORCH     : integer := 48; -- PIXELS 1.92us
147
             VGA_VER_CHARS          : integer := 25; -- CHARACTERS 12.8ms
148
             VGA_VER_CHAR_LINES     : integer := 16; -- LINES 0.512ms
149
             VGA_VER_FRONT_PORCH    : integer := 10; -- LINES 0.320ms
150
             VGA_VER_SYNC           : integer := 2;  -- LINES 0.064ms
151
             VGA_VER_BACK_PORCH     : integer := 34  -- LINES 1.088ms
152
  );
153
  port(
154
    -- control register interface
155
    vdu_clk      : in  std_logic;       -- 12.5/25 MHz CPU Clock
156
    vdu_rst      : in  std_logic;
157
    vdu_cs       : in  std_logic;
158
    vdu_rw       : in  std_logic;
159
    vdu_addr     : in  std_logic_vector(2 downto 0);
160
    vdu_data_in  : in  std_logic_vector(7 downto 0);
161
    vdu_data_out : out std_logic_vector(7 downto 0);
162
 
163
    -- vga port connections
164
    vga_clk      : in  std_logic;       -- 25MHz clock
165
    vga_red_o    : out std_logic;
166
    vga_green_o  : out std_logic;
167
    vga_blue_o   : out std_logic;
168
    vga_hsync_o  : out std_logic;
169
    vga_vsync_o  : out std_logic
170
    );
171
end vdu8;
172
 
173
Architecture RTL of vdu8 is
174
  --
175
  -- Synchronisation constants
176
  --
177
  -- Displayed Characters per row
178
  constant HOR_DISP_CHR : integer := VGA_HOR_CHARS;
179
  -- Last horizontal pixel displayed
180
  constant HOR_DISP_END : integer := (HOR_DISP_CHR * VGA_HOR_CHAR_PIXELS) - 1;
181
  -- Start of horizontal synch pulse
182
  constant HOR_SYNC_BEG : integer := HOR_DISP_END + VGA_HOR_FRONT_PORCH;
183
  -- End of Horizontal Synch pulse
184
  constant HOR_SYNC_END : integer := HOR_SYNC_BEG + VGA_HOR_SYNC;
185
  -- Last pixel in scan line
186
  constant HOR_SCAN_END : integer := HOR_SYNC_END + VGA_HOR_BACK_PORCH;
187
 
188
  -- Displayed Characters per Column
189
  constant VER_DISP_CHR : integer := VGA_VER_CHARS;
190
  -- last row displayed
191
  constant VER_DISP_END : integer := (VER_DISP_CHR * VGA_VER_CHAR_LINES) - 1;
192
  -- start of vertical synch pulse
193
  constant VER_SYNC_BEG : integer := VER_DISP_END + VGA_VER_FRONT_PORCH;
194
  -- end of vertical synch pulse
195
  constant VER_SYNC_END : integer := VER_SYNC_BEG + VGA_VER_SYNC;
196
  -- Last scan row in the frame
197
  constant VER_SCAN_END : integer := VER_SYNC_END + VGA_VER_BACK_PORCH;
198
 
199
  signal horiz_sync    : std_logic := '1';
200
  signal vert_sync     : std_logic := '1';
201
  signal cursor_on_v   : std_logic;
202
  signal cursor_on_h   : std_logic;
203
  signal video_on_v    : std_logic := '0';
204
  signal video_on_h    : std_logic := '0';
205
  signal h_count       : std_logic_vector(9 downto 0) := (others=>'0');
206
  signal v_count       : std_logic_vector(8 downto 0) := (others=>'0');  -- 0 to VER_SCAN_END
207
  signal blink_count   : std_logic_vector(22 downto 0):= (others=>'1');
208
  --
209
  -- Character generator ROM
210
  --
211
  signal char_addr     : std_logic_vector(10 downto 0);
212
  signal char_data_out : std_logic_vector(7 downto 0);
213
 
214
  --
215
  -- Control Registers
216
  --
217
  signal reg_character : std_logic_vector(7 downto 0);
218
  signal reg_colour    : std_logic_vector(7 downto 0);
219
  signal reg_hcursor   : std_logic_vector(6 downto 0);   -- 80 columns
220
  signal reg_vcursor   : std_logic_vector(4 downto 0);   -- 25 rows
221
  signal reg_voffset   : std_logic_vector(4 downto 0);   -- 25 rows
222
  --
223
  -- Video Shift register
224
  --
225
  signal vga_shift     : std_logic_vector(7 downto 0);
226
  signal vga_fg_colour : std_logic_vector(2 downto 0);
227
  signal vga_bg_colour : std_logic_vector(2 downto 0);
228
  signal cursor_on     : std_logic;
229
  signal cursor_on1    : std_logic;
230
  signal video_on      : std_logic := '0';
231
  signal video_on1     : std_logic := '0';
232
  signal video_on2     : std_logic := '0';
233
  --
234
  -- vga character ram access bus
235
  --
236
  signal col_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
237
  signal row_addr      : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 -1)
238
  signal col1_addr     : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
239
  signal row1_addr     : unsigned(5 downto 0)         := (others=>'0'); -- 0 to 49 (25 * 2 - 1)
240
  signal hor_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 79
241
  signal ver_addr      : std_logic_vector(6 downto 0) := (others=>'0'); -- 0 to 124
242
  signal vga0_cs       : std_logic;
243
  signal vga0_rw       : std_logic;
244
  signal vga1_cs       : std_logic;
245
  signal vga1_rw       : std_logic;
246
  signal vga2_cs       : std_logic;
247
  signal vga2_rw       : std_logic;
248
  signal vga_cs        : std_logic;
249
  signal vga_rw        : std_logic;
250
  signal vga_addr      : std_logic_vector(10 downto 0) := (others=>'0');  -- 2K byte character buffer
251
  signal vga_data_out  : std_logic_vector(7 downto 0);
252
  signal attr_data_out : std_logic_vector(7 downto 0);
253
  --
254
  -- Character write handshake signals
255
  --
256
  signal req_write     : std_logic;     -- request character write
257
  signal ack_write     : std_logic;
258
 
259
  --
260
  -- Block Ram Character gen
261
  --
262
  component char_rom
263
    port (
264
      clk      : in  std_logic;
265
      rst      : in  std_logic;
266
      cs       : in  std_logic;
267
      rw       : in  std_logic;
268
      addr     : in  std_logic_vector (10 downto 0);
269
      data_in  : in std_logic_vector (7 downto 0);
270
      data_out : out std_logic_vector (7 downto 0)
271
      );
272
  end component;
273
 
274
  component ram_2k
275
    port (
276
      clk      : in  std_logic;
277
      rst      : in  std_logic;
278
      cs       : in  std_logic;
279
      rw       : in  std_logic;
280
      addr     : in  std_logic_vector (10 downto 0);
281
      data_in  : in  std_logic_vector (7 downto 0);
282
      data_out : out std_logic_vector (7 downto 0)
283
      );
284
  end component;
285
 
286
begin
287
 
288
--
289
-- instantiate Character generator ROM
290
--
291
vdu_char_rom : char_rom port map(
292
        clk      => vga_clk,
293
        rst      => vdu_rst,
294
        cs       => '1',
295
        rw       => '1',
296
        addr     => char_addr,
297
        data_in  => "00000000",
298
        data_out => char_data_out
299
    );
300
 
301
--
302
-- Character buffer RAM
303
--
304
char_buff_ram : ram_2k port map(
305
    clk      => vga_clk,
306
    rst      => vdu_rst,
307
    cs       => vga_cs,
308
    rw       => vga_rw,
309
    addr     => vga_addr,
310
    data_in  => reg_character,
311
    data_out => vga_data_out
312
    );
313
 
314
--
315
-- Attribute buffer RAM
316
--
317
attr_buff_ram : ram_2k port map(
318
    clk      => vga_clk,
319
    rst      => vdu_rst,
320
    cs       => vga_cs,
321
    rw       => vga_rw,
322
    addr     => vga_addr,
323
    data_in  => reg_colour,
324
    data_out => attr_data_out
325
    );
326
 
327
--
328
-- CPU Write interface
329
--
330
  vga_cpu_write : process(vdu_clk, vdu_rst)
331
  begin
332
    if vdu_rst = '1' then
333
      reg_character <= "00000000";
334
      reg_colour    <= "00000111";
335
      reg_hcursor   <= "0000000";
336
      reg_vcursor   <= "00000";
337
      reg_voffset   <= "00000";
338
      req_write     <= '0';
339
 
340
    elsif vdu_clk'event and vdu_clk = '0' then
341
      if (vdu_cs = '1') and (vdu_rw = '0') then
342
        case vdu_addr is
343
          when "000" =>
344
            reg_character <= vdu_data_in;
345
            req_write     <= '1';
346
          when "001" =>
347
            reg_colour    <= vdu_data_in;
348
          when "010" =>
349
            reg_hcursor   <= vdu_data_in(6 downto 0);
350
          when "011" =>
351
            reg_vcursor   <= vdu_data_in(4 downto 0);
352
          when others =>
353
            reg_voffset   <= vdu_data_in(4 downto 0);
354
        end case;
355
      else
356
 
357
        if (req_write = '1') and (ack_write = '1') then
358
          req_write <= '0';
359
        else
360
          req_write <= req_write;
361
        end if;
362
 
363
      end if;
364
    end if;
365
  end process;
366
--
367
-- CPU Read interface
368
--
369
  vga_cpu_read : process(vdu_addr, vdu_cs,
370
                          reg_character, reg_colour,
371
                          reg_hcursor, reg_vcursor, reg_voffset)
372
  begin
373
    case vdu_addr is
374
      when "000" =>
375
        vdu_data_out <= reg_character;
376
      when "001" =>
377
        vdu_data_out <= reg_colour;
378
      when "010" =>
379
        vdu_data_out <= "0" & reg_hcursor;
380
      when "011" =>
381
        vdu_data_out <= "000" & reg_vcursor;
382
      when others =>
383
        vdu_data_out <= "000" & reg_voffset;
384
    end case;
385
  end process;
386
 
387
--
388
-- Video memory access
389
--
390
  vga_addr_proc : process(vga_clk, vdu_rst)
391
  begin
392
 
393
    if vdu_rst = '1' then
394
      vga0_cs   <= '0';
395
      vga0_rw   <= '1';
396
      row_addr  <= "000000";
397
      col_addr  <= "0000000";
398
      --
399
      vga1_cs   <= '0';
400
      vga1_rw   <= '1';
401
      row1_addr <= "000000";
402
      col1_addr <= "0000000";
403
      --
404
      vga2_cs   <= '0';
405
      vga2_rw   <= '1';
406
      ver_addr  <= "0000000";
407
      hor_addr  <= "0000000";
408
      --
409
      vga_cs    <= '0';
410
      vga_rw    <= '1';
411
      vga_addr  <= "00000000000";
412
 
413
    elsif vga_clk'event and vga_clk = '0' then
414
      --
415
      -- on h_count = 0 initiate character write.
416
      -- all other cycles are reads.
417
      --
418
      case h_count(2 downto 0) is
419
        when "000" =>                   -- pipeline character write
420
          vga0_cs  <= req_write;
421
          vga0_rw  <= '0';
422
          col_addr <= reg_hcursor(6 downto 0);
423
          row_addr <= unsigned("0" & reg_vcursor(4 downto 0)) + unsigned("0" & reg_voffset(4 downto 0));
424
        when others =>                  -- other 6 cycles free
425
          vga0_cs  <= '1';
426
          vga0_rw  <= '1';
427
          col_addr <= h_count(9 downto 3);
428
          row_addr <= unsigned("0" & v_count(8 downto 4)) + unsigned("0" & reg_voffset(4 downto 0));
429
      end case;
430
      --
431
      -- on vga_clk + 1 round off row address
432
      --
433
      vga1_cs <= vga0_cs;
434
      vga1_rw <= vga0_rw;
435
      if row_addr < VER_DISP_CHR then
436
        row1_addr <= row_addr;
437
      else
438
        row1_addr <= row_addr - VER_DISP_CHR;
439
      end if;
440
      col1_addr <= col_addr;
441
      --
442
      -- on vga_clk + 2 calculate vertical address
443
      --
444
      vga2_cs   <= vga1_cs;
445
      vga2_rw   <= vga1_rw;
446
      ver_addr  <= std_logic_vector(unsigned("00" & row1_addr(4 downto 0)) + unsigned(row1_addr(4 downto 0) & "00"));
447
      hor_addr  <= col1_addr;
448
      --
449
      -- on vga_clk + 3 calculate memory address
450
      --
451
      vga_cs    <= vga2_cs;
452
      vga_rw    <= vga2_rw;
453
      vga_addr  <= std_logic_vector(unsigned("0000" & hor_addr) + unsigned(ver_addr & "0000"));
454
    end if;
455
  end process;
456
--
457
-- Video shift register
458
--
459
  vga_shift_proc : process( vga_clk, vdu_rst)
460
  begin
461
    if vdu_rst = '1' then
462
      ack_write     <= '0';
463
      video_on2     <= '0';
464
      video_on      <= '0';
465
      cursor_on     <= '0';
466
      vga_bg_colour <= "000";
467
      vga_fg_colour <= "111";
468
      vga_shift     <= "00000000";
469
      vga_red_o     <= '0';
470
      vga_green_o   <= '0';
471
      vga_blue_o    <= '0';
472
      -- Put all video signals through DFFs to elminate any delays that cause a blurry image
473
 
474
    elsif vga_clk'event and vga_clk = '0' then
475
      -- Character Data valid on 1 count
476
      if h_count(2 downto 0) = "000" then
477
        if (req_write = '1') and (ack_write = '0') then
478
          ack_write <= '1';
479
        elsif (req_write = '0') and (ack_write = '1') then
480
          ack_write <= '0';
481
        else
482
          ack_write <= ack_write;
483
        end if;
484
        video_on2     <= video_on1;
485
        video_on      <= video_on2;
486
        cursor_on     <= (cursor_on1 or attr_data_out(3)) and blink_count(22);
487
        vga_fg_colour <= attr_data_out(2 downto 0);
488
        vga_bg_colour <= attr_data_out(6 downto 4);
489
        if attr_data_out(7) = '0' then
490
          vga_shift <= char_data_out;
491
        else
492
          case v_count(3 downto 2) is
493
            when "00" =>
494
              vga_shift(7 downto 4) <= vga_data_out(0) & vga_data_out(0) & vga_data_out(0) & vga_data_out(0);
495
              vga_shift(3 downto 0) <= vga_data_out(1) & vga_data_out(1) & vga_data_out(1) & vga_data_out(1);
496
            when "01" =>
497
              vga_shift(7 downto 4) <= vga_data_out(2) & vga_data_out(2) & vga_data_out(2) & vga_data_out(2);
498
              vga_shift(3 downto 0) <= vga_data_out(3) & vga_data_out(3) & vga_data_out(3) & vga_data_out(3);
499
            when "10" =>
500
              vga_shift(7 downto 4) <= vga_data_out(4) & vga_data_out(4) & vga_data_out(4) & vga_data_out(4);
501
              vga_shift(3 downto 0) <= vga_data_out(5) & vga_data_out(5) & vga_data_out(5) & vga_data_out(5);
502
            when others =>
503
              vga_shift(7 downto 4) <= vga_data_out(6) & vga_data_out(6) & vga_data_out(6) & vga_data_out(6);
504
              vga_shift(3 downto 0) <= vga_data_out(7) & vga_data_out(7) & vga_data_out(7) & vga_data_out(7);
505
          end case;
506
        end if;
507
      else
508
        vga_shift <= vga_shift(6 downto 0) & '0';
509
      end if;
510
 
511
      --
512
      -- Colour mask is
513
      --  7  6  5  4  3  2  1  0
514
      --  X BG BB BR  X FG FB FR
515
      --
516
      if vga_shift(7) = (not cursor_on) then
517
        vga_red_o   <= video_on and vga_fg_colour(0);
518
        vga_green_o <= video_on and vga_fg_colour(1);
519
        vga_blue_o  <= video_on and vga_fg_colour(2);
520
      else
521
        vga_red_o   <= video_on and vga_bg_colour(0);
522
        vga_green_o <= video_on and vga_bg_colour(1);
523
        vga_blue_o  <= video_on and vga_bg_colour(2);
524
      end if;
525
    end if;
526
  end process;
527
 
528
 
529
--
530
-- Sync generator & timing process
531
-- Generate Horizontal and Vertical Timing Signals for Video Signal
532
--
533
  vga_sync : process(vga_clk)
534
  begin
535
    if vga_clk'event and vga_clk = '0' then
536
      --
537
      -- H_count counts pixels (640 + extra time for sync signals)
538
      --
539
      --  Horiz_sync  -----------------------------__________--------
540
      --  H_count       0                640      659       755    799
541
      --
542
      if unsigned(h_count) = HOR_SCAN_END then
543
        h_count <= (others=>'0');
544
      else
545
        h_count <= std_logic_vector(unsigned(h_count) + 1);
546
      end if;
547
--
548
-- Generate Horizontal Sync Signal using H_count
549
--
550
      if unsigned(h_count) = HOR_SYNC_BEG then
551
        horiz_sync <= '0';
552
      elsif unsigned(h_count) = HOR_SYNC_END then
553
        horiz_sync <= '1';
554
      else
555
        horiz_sync <= horiz_sync;
556
      end if;
557
--
558
-- V_count counts rows of pixels
559
-- 400 lines + extra time for sync signals
560
-- 25 rows * 16 scan lines
561
--
562
--  Vert_sync      ---------------------------------_______------------
563
--  V_count         0                       400    413     414        444
564
--
565
      if (unsigned(v_count) = VER_SCAN_END) and (unsigned(h_count) = HOR_SCAN_END) then
566
        v_count <= "000000000";
567
      elsif unsigned(h_count) = HOR_SYNC_END then
568
        v_count <= std_logic_vector(unsigned(v_count) + 1);
569
      end if;
570
--
571
-- Generate Vertical Sync Signal using V_count
572
--
573
      if unsigned(v_count) = VER_SYNC_BEG then
574
        vert_sync <= '0';
575
      elsif unsigned(v_count) = VER_SYNC_END then
576
        vert_sync <= '1';
577
      else
578
        vert_sync <= vert_sync;
579
      end if;
580
 
581
-- Generate Video on Screen Signals for Pixel Data
582
      if unsigned(h_count) = HOR_SCAN_END then
583
        video_on_h <= '1';
584
      elsif unsigned(h_count) = HOR_DISP_END then
585
        video_on_h <= '0';
586
      else
587
        video_on_h <= video_on_h;
588
      end if;
589
 
590
      if unsigned(v_count) = VER_SCAN_END then
591
        video_on_v <= '1';
592
      elsif unsigned(v_count) = VER_DISP_END then
593
        video_on_v <= '0';
594
      else
595
        video_on_v <= video_on_v;
596
      end if;
597
 
598
 
599
      if h_count(9 downto 3) = reg_hcursor(6 downto 0) then
600
        cursor_on_h <= '1';
601
      else
602
        cursor_on_h <= '0';
603
      end if;
604
 
605
      if (v_count(8 downto 4) = reg_vcursor(4 downto 0)) then
606
        cursor_on_v <= '1';
607
      else
608
        cursor_on_v <= '0';
609
      end if;
610
 
611
      -- cursor_on is only active when on selected character
612
      blink_count <= std_logic_vector(unsigned(blink_count) + 1);
613
    end if;
614
 
615
  end process;
616
 
617
  -- video_on is high only when RGB data is displayed
618
  vga_hsync_o <= horiz_sync;
619
  vga_vsync_o <= vert_sync;
620
  video_on1   <= video_on_H and video_on_V;
621
  cursor_on1  <= cursor_on_h and cursor_on_v;
622
 
623
--
624
-- Here to look up character ROM
625
-- This will take one clock cycle
626
-- and should be performed on h_count = "111"
627
--
628
  char_addr(10 downto 4) <= vga_data_out(6 downto 0);
629
  char_addr(3 downto 0)  <= v_count(3 downto 0);
630
 
631
end RTL;

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