URL https://opencores.org/ocsvn/a-z80/a-z80/trunk

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [alu/] [alu_flags.v] - Blame information for rev 14

Go to most recent revision | Details | Compare with Previous | View Log


// Copyright (C) 1991-2013 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic 
// functions, and any output files from any of the foregoing 
// (including device programming or simulation files), and any 
// associated documentation or information are expressly subject 
// to the terms and conditions of the Altera Program License 
// Subscription Agreement, Altera MegaCore Function License 
// Agreement, or other applicable license agreement, including, 
// without limitation, that your use is for the sole purpose of 
// programming logic devices manufactured by Altera and sold by 
// Altera or its authorized distributors.  Please refer to the 
// applicable agreement for further details.
 
// PROGRAM              "Quartus II 64-Bit"
// VERSION              "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"
// CREATED              "Fri Dec 09 21:55:51 2016"
 
module alu_flags(
        ctl_flags_oe,
        ctl_flags_bus,
        ctl_flags_alu,
        alu_sf_out,
        alu_yf_out,
        alu_xf_out,
        ctl_flags_nf_set,
        alu_zero,
        shift_cf_out,
        alu_core_cf_out,
        daa_cf_out,
        ctl_flags_cf_set,
        ctl_flags_cf_cpl,
        pf_sel,
        ctl_flags_cf_we,
        ctl_flags_sz_we,
        ctl_flags_xy_we,
        ctl_flags_hf_we,
        ctl_flags_pf_we,
        ctl_flags_nf_we,
        ctl_flags_cf2_we,
        ctl_flags_hf_cpl,
        ctl_flags_use_cf2,
        ctl_flags_hf2_we,
        ctl_flags_nf_clr,
        ctl_alu_zero_16bit,
        clk,
        ctl_flags_cf2_sel_shift,
        ctl_flags_cf2_sel_daa,
        hold_clk_wait,
        flags_sf,
        flags_zf,
        flags_hf,
        flags_pf,
        flags_cf,
        flags_nf,
        flags_cf_latch,
        flags_hf2,
        db
);
 
 
input wire      ctl_flags_oe;
input wire      ctl_flags_bus;
input wire      ctl_flags_alu;
input wire      alu_sf_out;
input wire      alu_yf_out;
input wire      alu_xf_out;
input wire      ctl_flags_nf_set;
input wire      alu_zero;
input wire      shift_cf_out;
input wire      alu_core_cf_out;
input wire      daa_cf_out;
input wire      ctl_flags_cf_set;
input wire      ctl_flags_cf_cpl;
input wire      pf_sel;
input wire      ctl_flags_cf_we;
input wire      ctl_flags_sz_we;
input wire      ctl_flags_xy_we;
input wire      ctl_flags_hf_we;
input wire      ctl_flags_pf_we;
input wire      ctl_flags_nf_we;
input wire      ctl_flags_cf2_we;
input wire      ctl_flags_hf_cpl;
input wire      ctl_flags_use_cf2;
input wire      ctl_flags_hf2_we;
input wire      ctl_flags_nf_clr;
input wire      ctl_alu_zero_16bit;
input wire      clk;
input wire      ctl_flags_cf2_sel_shift;
input wire      ctl_flags_cf2_sel_daa;
input wire      hold_clk_wait;
output wire     flags_sf;
output wire     flags_zf;
output wire     flags_hf;
output wire     flags_pf;
output wire     flags_cf;
output wire     flags_nf;
output wire     flags_cf_latch;
output reg      flags_hf2;
inout wire      [7:0] db;
 
reg     flags_xf;
reg     flags_yf;
wire    [1:0] sel;
reg     DFFE_inst_latch_hf;
wire    SYNTHESIZED_WIRE_0;
wire    SYNTHESIZED_WIRE_1;
wire    SYNTHESIZED_WIRE_2;
wire    SYNTHESIZED_WIRE_3;
wire    SYNTHESIZED_WIRE_4;
wire    SYNTHESIZED_WIRE_5;
wire    SYNTHESIZED_WIRE_6;
wire    SYNTHESIZED_WIRE_7;
reg     SYNTHESIZED_WIRE_41;
wire    SYNTHESIZED_WIRE_42;
wire    SYNTHESIZED_WIRE_9;
wire    SYNTHESIZED_WIRE_11;
wire    SYNTHESIZED_WIRE_12;
wire    SYNTHESIZED_WIRE_13;
wire    SYNTHESIZED_WIRE_14;
wire    SYNTHESIZED_WIRE_15;
wire    SYNTHESIZED_WIRE_16;
wire    SYNTHESIZED_WIRE_17;
wire    SYNTHESIZED_WIRE_18;
wire    SYNTHESIZED_WIRE_19;
wire    SYNTHESIZED_WIRE_20;
wire    SYNTHESIZED_WIRE_21;
wire    SYNTHESIZED_WIRE_22;
wire    SYNTHESIZED_WIRE_23;
wire    SYNTHESIZED_WIRE_24;
reg     DFFE_inst_latch_sf;
wire    SYNTHESIZED_WIRE_25;
reg     DFFE_inst_latch_pf;
reg     DFFE_inst_latch_nf;
wire    SYNTHESIZED_WIRE_26;
wire    SYNTHESIZED_WIRE_27;
wire    SYNTHESIZED_WIRE_28;
wire    SYNTHESIZED_WIRE_29;
wire    SYNTHESIZED_WIRE_30;
wire    SYNTHESIZED_WIRE_31;
wire    SYNTHESIZED_WIRE_43;
wire    SYNTHESIZED_WIRE_34;
wire    SYNTHESIZED_WIRE_35;
wire    SYNTHESIZED_WIRE_36;
wire    SYNTHESIZED_WIRE_37;
wire    SYNTHESIZED_WIRE_38;
wire    SYNTHESIZED_WIRE_39;
reg     DFFE_inst_latch_cf;
reg     DFFE_inst_latch_cf2;
wire    SYNTHESIZED_WIRE_40;
 
assign  flags_sf = DFFE_inst_latch_sf;
assign  flags_zf = SYNTHESIZED_WIRE_41;
assign  flags_hf = SYNTHESIZED_WIRE_25;
assign  flags_pf = DFFE_inst_latch_pf;
assign  flags_cf = SYNTHESIZED_WIRE_26;
assign  flags_nf = DFFE_inst_latch_nf;
assign  flags_cf_latch = DFFE_inst_latch_cf;
assign  SYNTHESIZED_WIRE_40 = 0;
 
 
 
assign  SYNTHESIZED_WIRE_12 = db[7] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_19 = alu_xf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_22 = db[2] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_21 = pf_sel & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_25 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;
 
assign  SYNTHESIZED_WIRE_24 = db[0] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_23 = ctl_flags_alu & alu_core_cf_out;
 
assign  SYNTHESIZED_WIRE_9 =  ~ctl_flags_cf2_we;
 
assign  SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;
 
assign  SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_11 = alu_sf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_5 = ctl_flags_nf_set | SYNTHESIZED_WIRE_1 | SYNTHESIZED_WIRE_2;
 
assign  SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
 
 
assign  SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;
 
assign  SYNTHESIZED_WIRE_6 =  ~ctl_flags_nf_clr;
 
assign  SYNTHESIZED_WIRE_7 =  ~ctl_alu_zero_16bit;
 
assign  SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 | SYNTHESIZED_WIRE_41;
 
assign  SYNTHESIZED_WIRE_42 =  ~hold_clk_wait;
 
assign  SYNTHESIZED_WIRE_29 = ctl_flags_cf_we & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_9;
 
assign  SYNTHESIZED_WIRE_31 = ctl_flags_cf2_we & SYNTHESIZED_WIRE_42;
 
assign  SYNTHESIZED_WIRE_14 = db[6] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_11 | SYNTHESIZED_WIRE_12;
 
assign  SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_13 | SYNTHESIZED_WIRE_14;
 
assign  SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_15 | SYNTHESIZED_WIRE_16;
 
assign  SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_17 | SYNTHESIZED_WIRE_18;
 
assign  SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_19 | SYNTHESIZED_WIRE_20;
 
assign  SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_21 | SYNTHESIZED_WIRE_22;
 
assign  SYNTHESIZED_WIRE_13 = alu_zero & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_28 = SYNTHESIZED_WIRE_23 | SYNTHESIZED_WIRE_24;
 
assign  db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;
 
assign  SYNTHESIZED_WIRE_16 = db[5] & ctl_flags_bus;
 
assign  db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_41 : 1'bz;
 
assign  db[5] = ctl_flags_oe ? flags_yf : 1'bz;
 
assign  db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_25 : 1'bz;
 
assign  db[3] = ctl_flags_oe ? flags_xf : 1'bz;
 
assign  db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;
 
assign  db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;
 
assign  db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_26 : 1'bz;
 
assign  SYNTHESIZED_WIRE_15 = alu_yf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_0 = ctl_flags_cf_set | SYNTHESIZED_WIRE_27;
 
assign  SYNTHESIZED_WIRE_18 = db[4] & ctl_flags_bus;
 
assign  SYNTHESIZED_WIRE_17 = alu_core_cf_out & ctl_flags_alu;
 
assign  SYNTHESIZED_WIRE_20 = db[3] & ctl_flags_bus;
 
 
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_29)
        begin
        DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_28;
        end
end
 
 
always@(posedge clk)
begin
if (SYNTHESIZED_WIRE_31)
        begin
        DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_30;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_hf_we)
        begin
        DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_43;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_hf2_we)
        begin
        flags_hf2 <= SYNTHESIZED_WIRE_43;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_nf_we)
        begin
        DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_34;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_pf_we)
        begin
        DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_35;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_sz_we)
        begin
        DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_36;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_xy_we)
        begin
        flags_xf <= SYNTHESIZED_WIRE_37;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_xy_we)
        begin
        flags_yf <= SYNTHESIZED_WIRE_38;
        end
end
 
 
always@(posedge clk)
begin
if (ctl_flags_sz_we)
        begin
        SYNTHESIZED_WIRE_41 <= SYNTHESIZED_WIRE_39;
        end
end
 
 
alu_mux_2       b2v_inst_mux_cf(
        .in0(DFFE_inst_latch_cf),
        .in1(DFFE_inst_latch_cf2),
        .sel1(ctl_flags_use_cf2),
        .out(SYNTHESIZED_WIRE_27));
 
 
alu_mux_4       b2v_inst_mux_cf2(
        .in0(alu_core_cf_out),
        .in1(shift_cf_out),
        .in2(daa_cf_out),
        .in3(SYNTHESIZED_WIRE_40),
        .sel(sel),
        .out(SYNTHESIZED_WIRE_30));
 
assign  sel[0] = ctl_flags_cf2_sel_shift;
assign  sel[1] = ctl_flags_cf2_sel_daa;
 
endmodule

Line No.	Rev	Author	Line
1	3	gdevic	`// Copyright (C) 1991-2013 Altera Corporation`
2			`// Your use of Altera Corporation's design tools, logic functions`
3			`// and other software and tools, and its AMPP partner logic`
4			`// functions, and any output files from any of the foregoing`
5			`// (including device programming or simulation files), and any`
6			`// associated documentation or information are expressly subject`
7			`// to the terms and conditions of the Altera Program License`
8			`// Subscription Agreement, Altera MegaCore Function License`
9			`// Agreement, or other applicable license agreement, including,`
10			`// without limitation, that your use is for the sole purpose of`
11			`// programming logic devices manufactured by Altera and sold by`
12			`// Altera or its authorized distributors. Please refer to the`
13			`// applicable agreement for further details.`
14
15			`// PROGRAM "Quartus II 64-Bit"`
16			`// VERSION "Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition"`
17	14	gdevic	`// CREATED "Fri Dec 09 21:55:51 2016"`
18	3	gdevic
19			`module alu_flags(`
20			`ctl_flags_oe,`
21			`ctl_flags_bus,`
22			`ctl_flags_alu,`
23			`alu_sf_out,`
24			`alu_yf_out,`
25			`alu_xf_out,`
26			`ctl_flags_nf_set,`
27			`alu_zero,`
28			`shift_cf_out,`
29			`alu_core_cf_out,`
30			`daa_cf_out,`
31			`ctl_flags_cf_set,`
32			`ctl_flags_cf_cpl,`
33			`pf_sel,`
34			`ctl_flags_cf_we,`
35			`ctl_flags_sz_we,`
36			`ctl_flags_xy_we,`
37			`ctl_flags_hf_we,`
38			`ctl_flags_pf_we,`
39			`ctl_flags_nf_we,`
40			`ctl_flags_cf2_we,`
41			`ctl_flags_hf_cpl,`
42			`ctl_flags_use_cf2,`
43			`ctl_flags_hf2_we,`
44			`ctl_flags_nf_clr,`
45			`ctl_alu_zero_16bit,`
46			`clk,`
47	8	gdevic	`ctl_flags_cf2_sel_shift,`
48			`ctl_flags_cf2_sel_daa,`
49	14	gdevic	`hold_clk_wait,`
50	3	gdevic	`flags_sf,`
51			`flags_zf,`
52			`flags_hf,`
53			`flags_pf,`
54			`flags_cf,`
55			`flags_nf,`
56			`flags_cf_latch,`
57			`flags_hf2,`
58			`db`
59			`);`
60
61
62			`input wire ctl_flags_oe;`
63			`input wire ctl_flags_bus;`
64			`input wire ctl_flags_alu;`
65			`input wire alu_sf_out;`
66			`input wire alu_yf_out;`
67			`input wire alu_xf_out;`
68			`input wire ctl_flags_nf_set;`
69			`input wire alu_zero;`
70			`input wire shift_cf_out;`
71			`input wire alu_core_cf_out;`
72			`input wire daa_cf_out;`
73			`input wire ctl_flags_cf_set;`
74			`input wire ctl_flags_cf_cpl;`
75			`input wire pf_sel;`
76			`input wire ctl_flags_cf_we;`
77			`input wire ctl_flags_sz_we;`
78			`input wire ctl_flags_xy_we;`
79			`input wire ctl_flags_hf_we;`
80			`input wire ctl_flags_pf_we;`
81			`input wire ctl_flags_nf_we;`
82			`input wire ctl_flags_cf2_we;`
83			`input wire ctl_flags_hf_cpl;`
84			`input wire ctl_flags_use_cf2;`
85			`input wire ctl_flags_hf2_we;`
86			`input wire ctl_flags_nf_clr;`
87			`input wire ctl_alu_zero_16bit;`
88			`input wire clk;`
89	8	gdevic	`input wire ctl_flags_cf2_sel_shift;`
90			`input wire ctl_flags_cf2_sel_daa;`
91	14	gdevic	`input wire hold_clk_wait;`
92	3	gdevic	`output wire flags_sf;`
93			`output wire flags_zf;`
94			`output wire flags_hf;`
95			`output wire flags_pf;`
96			`output wire flags_cf;`
97			`output wire flags_nf;`
98			`output wire flags_cf_latch;`
99			`output reg flags_hf2;`
100			`inout wire [7:0] db;`
101
102			`reg flags_xf;`
103			`reg flags_yf;`
104	8	gdevic	`wire [1:0] sel;`
105	14	gdevic	`reg DFFE_inst_latch_hf;`
106	3	gdevic	`wire SYNTHESIZED_WIRE_0;`
107			`wire SYNTHESIZED_WIRE_1;`
108			`wire SYNTHESIZED_WIRE_2;`
109			`wire SYNTHESIZED_WIRE_3;`
110			`wire SYNTHESIZED_WIRE_4;`
111			`wire SYNTHESIZED_WIRE_5;`
112			`wire SYNTHESIZED_WIRE_6;`
113			`wire SYNTHESIZED_WIRE_7;`
114	14	gdevic	`reg SYNTHESIZED_WIRE_41;`
115			`wire SYNTHESIZED_WIRE_42;`
116	3	gdevic	`wire SYNTHESIZED_WIRE_9;`
117			`wire SYNTHESIZED_WIRE_11;`
118			`wire SYNTHESIZED_WIRE_12;`
119			`wire SYNTHESIZED_WIRE_13;`
120			`wire SYNTHESIZED_WIRE_14;`
121			`wire SYNTHESIZED_WIRE_15;`
122			`wire SYNTHESIZED_WIRE_16;`
123			`wire SYNTHESIZED_WIRE_17;`
124			`wire SYNTHESIZED_WIRE_18;`
125			`wire SYNTHESIZED_WIRE_19;`
126			`wire SYNTHESIZED_WIRE_20;`
127			`wire SYNTHESIZED_WIRE_21;`
128			`wire SYNTHESIZED_WIRE_22;`
129	14	gdevic	`wire SYNTHESIZED_WIRE_23;`
130			`wire SYNTHESIZED_WIRE_24;`
131	3	gdevic	`reg DFFE_inst_latch_sf;`
132	14	gdevic	`wire SYNTHESIZED_WIRE_25;`
133	3	gdevic	`reg DFFE_inst_latch_pf;`
134			`reg DFFE_inst_latch_nf;`
135			`wire SYNTHESIZED_WIRE_26;`
136			`wire SYNTHESIZED_WIRE_27;`
137			`wire SYNTHESIZED_WIRE_28;`
138	14	gdevic	`wire SYNTHESIZED_WIRE_29;`
139			`wire SYNTHESIZED_WIRE_30;`
140	3	gdevic	`wire SYNTHESIZED_WIRE_31;`
141	14	gdevic	`wire SYNTHESIZED_WIRE_43;`
142	3	gdevic	`wire SYNTHESIZED_WIRE_34;`
143			`wire SYNTHESIZED_WIRE_35;`
144			`wire SYNTHESIZED_WIRE_36;`
145	14	gdevic	`wire SYNTHESIZED_WIRE_37;`
146			`wire SYNTHESIZED_WIRE_38;`
147			`wire SYNTHESIZED_WIRE_39;`
148	3	gdevic	`reg DFFE_inst_latch_cf;`
149			`reg DFFE_inst_latch_cf2;`
150	14	gdevic	`wire SYNTHESIZED_WIRE_40;`
151	3	gdevic
152			`assign flags_sf = DFFE_inst_latch_sf;`
153	14	gdevic	`assign flags_zf = SYNTHESIZED_WIRE_41;`
154			`assign flags_hf = SYNTHESIZED_WIRE_25;`
155	3	gdevic	`assign flags_pf = DFFE_inst_latch_pf;`
156	14	gdevic	`assign flags_cf = SYNTHESIZED_WIRE_26;`
157	3	gdevic	`assign flags_nf = DFFE_inst_latch_nf;`
158			`assign flags_cf_latch = DFFE_inst_latch_cf;`
159	14	gdevic	`assign SYNTHESIZED_WIRE_40 = 0;`
160	3	gdevic
161
162
163	14	gdevic	`assign SYNTHESIZED_WIRE_12 = db[7] & ctl_flags_bus;`
164	3	gdevic
165	14	gdevic	`assign SYNTHESIZED_WIRE_19 = alu_xf_out & ctl_flags_alu;`
166	3	gdevic
167	14	gdevic	`assign SYNTHESIZED_WIRE_22 = db[2] & ctl_flags_bus;`
168	3	gdevic
169	14	gdevic	`assign SYNTHESIZED_WIRE_21 = pf_sel & ctl_flags_alu;`
170	3	gdevic
171	14	gdevic	`assign SYNTHESIZED_WIRE_2 = db[1] & ctl_flags_bus;`
172	3	gdevic
173	14	gdevic	`assign SYNTHESIZED_WIRE_25 = DFFE_inst_latch_hf ^ ctl_flags_hf_cpl;`
174	3	gdevic
175	14	gdevic	`assign SYNTHESIZED_WIRE_24 = db[0] & ctl_flags_bus;`
176	3	gdevic
177	14	gdevic	`assign SYNTHESIZED_WIRE_23 = ctl_flags_alu & alu_core_cf_out;`
178	3	gdevic
179	14	gdevic	`assign SYNTHESIZED_WIRE_9 = ~ctl_flags_cf2_we;`
180	3	gdevic
181	14	gdevic	`assign SYNTHESIZED_WIRE_26 = SYNTHESIZED_WIRE_0 ^ ctl_flags_cf_cpl;`
182	3	gdevic
183	14	gdevic	`assign SYNTHESIZED_WIRE_1 = alu_sf_out & ctl_flags_alu;`
184	3	gdevic
185	14	gdevic	`assign SYNTHESIZED_WIRE_11 = alu_sf_out & ctl_flags_alu;`
186	3	gdevic
187	14	gdevic	`assign SYNTHESIZED_WIRE_5 = ctl_flags_nf_set \| SYNTHESIZED_WIRE_1 \| SYNTHESIZED_WIRE_2;`
188	3	gdevic
189	14	gdevic	`assign SYNTHESIZED_WIRE_39 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;`
190	3	gdevic
191
192	14	gdevic	`assign SYNTHESIZED_WIRE_34 = SYNTHESIZED_WIRE_5 & SYNTHESIZED_WIRE_6;`
193	3	gdevic
194	14	gdevic	`assign SYNTHESIZED_WIRE_6 = ~ctl_flags_nf_clr;`
195	3	gdevic
196	14	gdevic	`assign SYNTHESIZED_WIRE_7 = ~ctl_alu_zero_16bit;`
197	3	gdevic
198	14	gdevic	`assign SYNTHESIZED_WIRE_4 = SYNTHESIZED_WIRE_7 \| SYNTHESIZED_WIRE_41;`
199	3	gdevic
200	14	gdevic	`assign SYNTHESIZED_WIRE_42 = ~hold_clk_wait;`
201	3	gdevic
202	14	gdevic	`assign SYNTHESIZED_WIRE_29 = ctl_flags_cf_we & SYNTHESIZED_WIRE_42 & SYNTHESIZED_WIRE_9;`
203	3	gdevic
204	14	gdevic	`assign SYNTHESIZED_WIRE_31 = ctl_flags_cf2_we & SYNTHESIZED_WIRE_42;`
205	3	gdevic
206	14	gdevic	`assign SYNTHESIZED_WIRE_14 = db[6] & ctl_flags_bus;`
207	3	gdevic
208	14	gdevic	`assign SYNTHESIZED_WIRE_36 = SYNTHESIZED_WIRE_11 \| SYNTHESIZED_WIRE_12;`
209	3	gdevic
210	14	gdevic	`assign SYNTHESIZED_WIRE_3 = SYNTHESIZED_WIRE_13 \| SYNTHESIZED_WIRE_14;`
211	3	gdevic
212	14	gdevic	`assign SYNTHESIZED_WIRE_38 = SYNTHESIZED_WIRE_15 \| SYNTHESIZED_WIRE_16;`
213	3	gdevic
214	14	gdevic	`assign SYNTHESIZED_WIRE_43 = SYNTHESIZED_WIRE_17 \| SYNTHESIZED_WIRE_18;`
215	3	gdevic
216	14	gdevic	`assign SYNTHESIZED_WIRE_37 = SYNTHESIZED_WIRE_19 \| SYNTHESIZED_WIRE_20;`
217	3	gdevic
218	14	gdevic	`assign SYNTHESIZED_WIRE_35 = SYNTHESIZED_WIRE_21 \| SYNTHESIZED_WIRE_22;`
219	3	gdevic
220	14	gdevic	`assign SYNTHESIZED_WIRE_13 = alu_zero & ctl_flags_alu;`
221
222			`assign SYNTHESIZED_WIRE_28 = SYNTHESIZED_WIRE_23 \| SYNTHESIZED_WIRE_24;`
223
224	3	gdevic	`assign db[7] = ctl_flags_oe ? DFFE_inst_latch_sf : 1'bz;`
225
226	14	gdevic	`assign SYNTHESIZED_WIRE_16 = db[5] & ctl_flags_bus;`
227	3	gdevic
228	14	gdevic	`assign db[6] = ctl_flags_oe ? SYNTHESIZED_WIRE_41 : 1'bz;`
229	3	gdevic
230			`assign db[5] = ctl_flags_oe ? flags_yf : 1'bz;`
231
232	14	gdevic	`assign db[4] = ctl_flags_oe ? SYNTHESIZED_WIRE_25 : 1'bz;`
233	3	gdevic
234			`assign db[3] = ctl_flags_oe ? flags_xf : 1'bz;`
235
236			`assign db[2] = ctl_flags_oe ? DFFE_inst_latch_pf : 1'bz;`
237
238			`assign db[1] = ctl_flags_oe ? DFFE_inst_latch_nf : 1'bz;`
239
240	14	gdevic	`assign db[0] = ctl_flags_oe ? SYNTHESIZED_WIRE_26 : 1'bz;`
241	3	gdevic
242	14	gdevic	`assign SYNTHESIZED_WIRE_15 = alu_yf_out & ctl_flags_alu;`
243	3	gdevic
244	14	gdevic	`assign SYNTHESIZED_WIRE_0 = ctl_flags_cf_set \| SYNTHESIZED_WIRE_27;`
245	3	gdevic
246	14	gdevic	`assign SYNTHESIZED_WIRE_18 = db[4] & ctl_flags_bus;`
247	3	gdevic
248	14	gdevic	`assign SYNTHESIZED_WIRE_17 = alu_core_cf_out & ctl_flags_alu;`
249	3	gdevic
250	14	gdevic	`assign SYNTHESIZED_WIRE_20 = db[3] & ctl_flags_bus;`
251	3	gdevic
252
253			`always@(posedge clk)`
254			`begin`
255	14	gdevic	`if (SYNTHESIZED_WIRE_29)`
256	3	gdevic	`begin`
257	14	gdevic	`DFFE_inst_latch_cf <= SYNTHESIZED_WIRE_28;`
258	3	gdevic	`end`
259			`end`
260
261
262			`always@(posedge clk)`
263			`begin`
264	14	gdevic	`if (SYNTHESIZED_WIRE_31)`
265	3	gdevic	`begin`
266	14	gdevic	`DFFE_inst_latch_cf2 <= SYNTHESIZED_WIRE_30;`
267	3	gdevic	`end`
268			`end`
269
270
271			`always@(posedge clk)`
272			`begin`
273			`if (ctl_flags_hf_we)`
274			`begin`
275	14	gdevic	`DFFE_inst_latch_hf <= SYNTHESIZED_WIRE_43;`
276	3	gdevic	`end`
277			`end`
278
279
280			`always@(posedge clk)`
281			`begin`
282			`if (ctl_flags_hf2_we)`
283			`begin`
284	14	gdevic	`flags_hf2 <= SYNTHESIZED_WIRE_43;`
285	3	gdevic	`end`
286			`end`
287
288
289			`always@(posedge clk)`
290			`begin`
291			`if (ctl_flags_nf_we)`
292			`begin`
293	14	gdevic	`DFFE_inst_latch_nf <= SYNTHESIZED_WIRE_34;`
294	3	gdevic	`end`
295			`end`
296
297
298			`always@(posedge clk)`
299			`begin`
300			`if (ctl_flags_pf_we)`
301			`begin`
302	14	gdevic	`DFFE_inst_latch_pf <= SYNTHESIZED_WIRE_35;`
303	3	gdevic	`end`
304			`end`
305
306
307			`always@(posedge clk)`
308			`begin`
309			`if (ctl_flags_sz_we)`
310			`begin`
311	14	gdevic	`DFFE_inst_latch_sf <= SYNTHESIZED_WIRE_36;`
312	3	gdevic	`end`
313			`end`
314
315
316			`always@(posedge clk)`
317			`begin`
318			`if (ctl_flags_xy_we)`
319			`begin`
320	14	gdevic	`flags_xf <= SYNTHESIZED_WIRE_37;`
321	3	gdevic	`end`
322			`end`
323
324
325			`always@(posedge clk)`
326			`begin`
327			`if (ctl_flags_xy_we)`
328			`begin`
329	14	gdevic	`flags_yf <= SYNTHESIZED_WIRE_38;`
330	3	gdevic	`end`
331			`end`
332
333
334			`always@(posedge clk)`
335			`begin`
336			`if (ctl_flags_sz_we)`
337			`begin`
338	14	gdevic	`SYNTHESIZED_WIRE_41 <= SYNTHESIZED_WIRE_39;`
339	3	gdevic	`end`
340			`end`
341
342
343			`alu_mux_2 b2v_inst_mux_cf(`
344			`.in0(DFFE_inst_latch_cf),`
345			`.in1(DFFE_inst_latch_cf2),`
346			`.sel1(ctl_flags_use_cf2),`
347	14	gdevic	`.out(SYNTHESIZED_WIRE_27));`
348	3	gdevic
349
350			`alu_mux_4 b2v_inst_mux_cf2(`
351			`.in0(alu_core_cf_out),`
352			`.in1(shift_cf_out),`
353			`.in2(daa_cf_out),`
354	14	gdevic	`.in3(SYNTHESIZED_WIRE_40),`
355	8	gdevic	`.sel(sel),`
356	14	gdevic	`.out(SYNTHESIZED_WIRE_30));`
357	3	gdevic
358	8	gdevic	`assign sel[0] = ctl_flags_cf2_sel_shift;`
359			`assign sel[1] = ctl_flags_cf2_sel_daa;`
360	3	gdevic
361			`endmodule`

Browse

Tools

Subversion Repositories a-z80

[/] [a-z80/] [trunk/] [cpu/] [alu/] [alu_flags.v] - Blame information for rev 14