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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_defines.v] - Blame information for rev 42

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_defines.v                                              ////
////                                                              ////
////                                                              ////
////  This file is part of the Advanced Debug Interface.          ////
////                                                              ////
////  Author(s):                                                  ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 - 2010 Authors                            ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
// Length of the MODULE ID register
`define DBG_TOP_MODULE_ID_LENGTH        2
 
// How many modules can be supported by the module id length
`define     DBG_TOP_MAX_MODULES           4
 
// Chains
`define DBG_TOP_WISHBONE_DEBUG_MODULE  2'h0
`define DBG_TOP_CPU0_DEBUG_MODULE      2'h1
`define DBG_TOP_CPU1_DEBUG_MODULE      2'h2
`define DBG_TOP_JSP_DEBUG_MODULE       2'h3
 
// Length of data
`define DBG_TOP_MODULE_DATA_LEN  53
 
 
// If WISHBONE sub-module is supported uncomment the following line
`define DBG_WISHBONE_SUPPORTED
 
// If CPU_0 sub-module is supported uncomment the following line
`define DBG_CPU0_SUPPORTED
 
// If CPU_1 sub-module is supported uncomment the following line
//`define DBG_CPU1_SUPPORTED
 
// To include the JTAG Serial Port (JSP), uncomment the following line
`define DBG_JSP_SUPPORTED
 
// Define this if you intend to use the JSP in a system with multiple
// devices on the JTAG chain
`define ADBG_JSP_SUPPORT_MULTI
 
// If this is defined, status bits will be skipped on burst
// reads and writes to improve download speeds.
`define ADBG_USE_HISPEED

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_defines.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the Advanced Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	32	nyawn	`//// Copyright (C) 2008 - 2010 Authors ////`
16	3	nyawn	`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39
40	42	nyawn
41	3	nyawn	`// Length of the MODULE ID register`
42			`define DBG_TOP_MODULE_ID_LENGTH 2
43
44			`// How many modules can be supported by the module id length`
45			`define DBG_TOP_MAX_MODULES 4
46
47			`// Chains`
48			`define DBG_TOP_WISHBONE_DEBUG_MODULE 2'h0
49			`define DBG_TOP_CPU0_DEBUG_MODULE 2'h1
50			`define DBG_TOP_CPU1_DEBUG_MODULE 2'h2
51	42	nyawn	`define DBG_TOP_JSP_DEBUG_MODULE 2'h3
52	3	nyawn
53			`// Length of data`
54			`define DBG_TOP_MODULE_DATA_LEN 53
55
56
57	42	nyawn	`// If WISHBONE sub-module is supported uncomment the following line`
58	3	nyawn	`define DBG_WISHBONE_SUPPORTED
59
60	42	nyawn	`// If CPU_0 sub-module is supported uncomment the following line`
61	3	nyawn	`define DBG_CPU0_SUPPORTED
62
63	42	nyawn	`// If CPU_1 sub-module is supported uncomment the following line`
64	3	nyawn	//`define DBG_CPU1_SUPPORTED
65
66	42	nyawn	`// To include the JTAG Serial Port (JSP), uncomment the following line`
67			`define DBG_JSP_SUPPORTED
68
69			`// Define this if you intend to use the JSP in a system with multiple`
70			`// devices on the JTAG chain`
71			`define ADBG_JSP_SUPPORT_MULTI
72
73	32	nyawn	`// If this is defined, status bits will be skipped on burst`
74	42	nyawn	`// reads and writes to improve download speeds.`
75	32	nyawn	`define ADBG_USE_HISPEED

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_defines.v] - Blame information for rev 42