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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_jsp_module.v                                           ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Advanced Debug Interface.      ////
////                                                              ////
////  Author(s):                                                  ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2010       Authors                             ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "adbg_defines.v"
 
// Module interface
module adbg_jsp_module (
                         // JTAG signals
                         tck_i,
                         module_tdo_o,
                         tdi_i,
 
                         // TAP states
                         capture_dr_i,
                         shift_dr_i,
                         update_dr_i,
 
                         data_register_i,  // the data register is at top level, shared between all modules
                         module_select_i,
                         top_inhibit_o,
                         rst_i,
 
                         // WISHBONE common signals
                         wb_clk_i, wb_rst_i,
 
                         // WISHBONE slave interface
                         wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,
                         wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o
                         );
 
   // JTAG signals
   input         tck_i;
   output        module_tdo_o;
   input         tdi_i;  // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle
 
   // TAP states
   input         capture_dr_i;
   input         shift_dr_i;
   input         update_dr_i;
 
   input [52:0]  data_register_i;
   input         module_select_i;
   output        top_inhibit_o;
   input         rst_i;
 
   // WISHBONE slave interface
   input         wb_clk_i;
   input         wb_rst_i;
   input  [31:0] wb_adr_i;
   output [31:0] wb_dat_o;
   input  [31:0] wb_dat_i;
   input         wb_cyc_i;
   input         wb_stb_i;
   input   [3:0] wb_sel_i;
   input         wb_we_i;
   output        wb_ack_o;
   input         wb_cab_i;
   output        wb_err_o;
   input   [2:0] wb_cti_i;
   input   [1:0] wb_bte_i;
   output        int_o;
 
   // Declare inputs / outputs as wires / registers
   wire          module_tdo_o;
   wire          top_inhibit_o;
 
   // NOTE:  For the rest of this file, "input" and the "in" direction refer to bytes being transferred
   // from the PC, through the JTAG, and into the BIU FIFO.  The "output" direction refers to data being
   // transferred from the BIU FIFO, through the JTAG to the PC.
 
   // The read and write bit counts are separated to allow for JTAG chains with multiple devices.
   // The read bit count starts right away (after a single throwaway bit), but the write count
   // waits to receive a '1' start bit.
 
   // Registers to hold state etc.
   reg [3:0]      read_bit_count;            // How many bits have been shifted out
   reg [3:0]   write_bit_count;      // How many bits have been shifted in
   reg [3:0]      input_word_count;     // space (bytes) remaining in input FIFO (from JTAG)
   reg [3:0]     output_word_count;    // bytes remaining in output FIFO (to JTAG)
   reg [3:0]      user_word_count;     // bytes user intends to send from PC
   reg [7:0]      data_out_shift_reg;  // parallel-load output shift register
 
 
   // Control signals for the various counters / registers / state machines
   reg           rd_bit_ct_en;         // enable bit counter
   reg           rd_bit_ct_rst;        // reset (zero) bit count register
   reg           wr_bit_ct_en;         // enable bit counter
   reg           wr_bit_ct_rst;        // reset (zero) bit count register   
   reg           in_word_ct_sel;       // Selects data for byte counter.  0 = data_register_i, 1 = decremented byte count
   reg           out_word_ct_sel;       // Selects data for byte counter.  0 = data_register_i, 1 = decremented byte count
   reg           in_word_ct_en;     // Enable input byte counter register
   reg           out_word_ct_en;    // Enable output byte count register
   reg           user_word_ct_en;   // Enable user byte count registere
   reg           user_word_ct_sel;  // selects data for user byte counter.  0 = user data, 1 = decremented byte count
   reg           out_reg_ld_en;     // Enable parallel load of data_out_shift_reg
   reg           out_reg_shift_en;  // Enable shift of data_out_shift_reg
   reg           out_reg_data_sel;  // 0 = BIU data, 1 = byte count data (also from BIU)
   reg           biu_rd_strobe;      // Indicates that the bus unit should ACK the last read operation + start another
   reg           biu_wr_strobe;   // Indicates BIU should latch input + begin a write operation
 
 
   // Status signals
   wire          in_word_count_zero;   // true when input byte counter is zero
   wire          out_word_count_zero;   // true when output byte counter is zero
   wire          user_word_count_zero; // true when user byte counter is zero
   wire          rd_bit_count_max;     // true when bit counter is equal to current word size
   wire          wr_bit_count_max;     // true when bit counter is equal to current word size
 
   // Intermediate signals
   wire [3:0]     data_to_in_word_counter;  // output of the mux in front of the input byte counter reg
   wire [3:0]     data_to_out_word_counter;  // output of the mux in front of the output byte counter reg
   wire [3:0]     data_to_user_word_counter;  // output of mux in front of user word counter
   wire [3:0]     decremented_in_word_count;
   wire [3:0]     decremented_out_word_count;
   wire [3:0]     decremented_user_word_count;
   wire [3:0]     count_data_in;         // from data_register_i
   wire [7:0]     data_to_biu;           // from data_register_i
   wire [7:0]     data_from_biu;         // to data_out_shift_register
   wire [3:0]     biu_space_available;
   wire [3:0]     biu_bytes_available;
   wire [7:0]     count_data_from_biu;   // combined space avail / bytes avail
   wire [7:0]     out_reg_data;           // parallel input to the output shift register
 
 
   /////////////////////////////////////////////////
   // Combinatorial assignments
 
   assign count_data_from_biu = {biu_bytes_available, biu_space_available};
   assign count_data_in = {tdi_i, data_register_i[52:50]};  // Second nibble of user data
   assign data_to_biu = {tdi_i,data_register_i[52:46]};
   assign top_inhibit_o = 1'b0;
 
   //////////////////////////////////////
   // Input bit counter
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)             write_bit_count <= 4'h0;
        else if(wr_bit_ct_rst)   write_bit_count <= 4'h0;
        else if(wr_bit_ct_en)    write_bit_count <= write_bit_count + 4'h1;
     end
 
   assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;
 
   //////////////////////////////////////
   // Output bit counter
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)             read_bit_count <= 4'h0;
        else if(rd_bit_ct_rst)   read_bit_count <= 4'h0;
        else if(rd_bit_ct_en)    read_bit_count <= read_bit_count + 4'h1;
     end
 
   assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;
 
   ////////////////////////////////////////
   // Input word counter
 
   assign data_to_in_word_counter = (in_word_ct_sel) ?  decremented_in_word_count : biu_space_available;
   assign decremented_in_word_count = input_word_count - 4'h1;
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)
          input_word_count <= 4'h0;
        else if(in_word_ct_en)
          input_word_count <= data_to_in_word_counter;
     end
 
   assign in_word_count_zero = (input_word_count == 4'h0);
 
   ////////////////////////////////////////
   // Output word counter
 
   assign data_to_out_word_counter = (out_word_ct_sel) ?  decremented_out_word_count : biu_bytes_available;
   assign decremented_out_word_count = output_word_count - 4'h1;
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)
          output_word_count <= 4'h0;
        else if(out_word_ct_en)
          output_word_count <= data_to_out_word_counter;
     end
 
   assign out_word_count_zero = (output_word_count == 4'h0);
 
   ////////////////////////////////////////
   // User word counter
 
   assign data_to_user_word_counter = (user_word_ct_sel) ?  decremented_user_word_count : count_data_in;
   assign decremented_user_word_count = user_word_count - 4'h1;
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)                 user_word_count <= 4'h0;
        else if(user_word_ct_en)  user_word_count <= data_to_user_word_counter;
     end
 
   assign user_word_count_zero = (user_word_count == 4'h0);
 
   /////////////////////////////////////////////////////
   // Output register and TDO output MUX
 
   assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;
 
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i) data_out_shift_reg <= 8'h0;
        else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;
        else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};
     end
 
   assign module_tdo_o = data_out_shift_reg[0];
 
   ////////////////////////////////////////
   // Bus Interface Unit (to JTAG / WB UART)
   // It is assumed that the BIU has internal registers, and will
   // latch write data (and ack read data) on rising clock edge 
   // when strobe is asserted
 
   adbg_jsp_biu jsp_biu_i (
                           // Debug interface signals
                           .tck_i           (tck_i),
                           .rst_i           (rst_i),
                           .data_i          (data_to_biu),
                           .data_o          (data_from_biu),
                           .bytes_available_o (biu_bytes_available),
                           .bytes_free_o    (biu_space_available),
                           .rd_strobe_i     (biu_rd_strobe),
                           .wr_strobe_i     (biu_wr_strobe),
 
                           // Wishbone slave signals
                           .wb_clk_i        (wb_clk_i),
                           .wb_rst_i        (wb_rst_i),
                           .wb_adr_i        (wb_adr_i),
                           .wb_dat_o        (wb_dat_o),
                           .wb_dat_i        (wb_dat_i),
                           .wb_cyc_i        (wb_cyc_i),
                           .wb_stb_i        (wb_stb_i),
                           .wb_sel_i        (wb_sel_i),
                           .wb_we_i         (wb_we_i),
                           .wb_ack_o        (wb_ack_o),
                           .wb_cab_i        (wb_cab_i),
                           .wb_err_o        (wb_err_o),
                           .wb_cti_i        (wb_cti_i),
                           .wb_bte_i        (wb_bte_i),
                           .int_o           (int_o)
                           );
 
 
   ////////////////////////////////////////
   // Input Control FSM
 
   // Definition of machine state values.
   // Don't worry too much about the state encoding, the synthesis tool
   // will probably re-encode it anyway.
 
`define STATE_wr_idle     3'h0
`define STATE_wr_wait     3'h1
`define STATE_wr_counts   3'h2
`define STATE_wr_xfer     3'h3
 
   reg [2:0] wr_module_state;       // FSM state
   reg [2:0] wr_module_next_state;  // combinatorial signal, not actually a register
 
 
   // sequential part of the FSM
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)
          wr_module_state <= `STATE_wr_idle;
        else
          wr_module_state <= wr_module_next_state;
     end
 
 
   // Determination of next state; purely combinatorial
   always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i
             or shift_dr_i or wr_bit_count_max or tdi_i)
     begin
        case(wr_module_state)
          `STATE_wr_idle:
            begin
`ifdef ADBG_JSP_SUPPORT_MULTI
               if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
`else
               if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
`endif
               else wr_module_next_state <= `STATE_wr_idle;
            end
           `STATE_wr_wait:
           begin
                 if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
                  else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts;  // got start bit
               else wr_module_next_state <= `STATE_wr_wait;
           end
          `STATE_wr_counts:
            begin
               if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
               else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
               else wr_module_next_state <= `STATE_wr_counts;
            end
 
          `STATE_wr_xfer:
            begin
               if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
               else wr_module_next_state <= `STATE_wr_xfer;
            end
 
          default: wr_module_next_state <= `STATE_wr_idle;  // shouldn't actually happen...
        endcase
     end
 
 
   // Outputs of state machine, pure combinatorial
   always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
             or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count
             or decremented_out_word_count or user_word_count_zero)
     begin
        // Default everything to 0, keeps the case statement simple
        wr_bit_ct_en <= 1'b0;         // enable bit counter
        wr_bit_ct_rst <= 1'b0;        // reset (zero) bit count register
        in_word_ct_sel <= 1'b0;       // Selects data for byte counter.  0 = data_register_i, 1 = decremented byte count
        user_word_ct_sel <= 1'b0;  // selects data for user byte counter, 0 = user data, 1 = decremented count
        in_word_ct_en <= 1'b0;     // Enable input byte counter register
        user_word_ct_en <= 1'b0;   // enable user byte count register
        biu_wr_strobe <= 1'b0;    // Indicates BIU should latch input + begin a write operation
 
        case(wr_module_state)
          `STATE_wr_idle:
            begin
               in_word_ct_sel <= 1'b0;
 
               // Going to transfer; enable count registers and output register
               if(wr_module_next_state != `STATE_wr_idle) begin
                  wr_bit_ct_rst <= 1'b1;
                  in_word_ct_en <= 1'b1;
               end
            end
 
          // This state is only used when support for multi-device JTAG chains is enabled.
          `STATE_wr_wait:
            begin
               wr_bit_ct_en <= 1'b0;  // Don't do anything, just wait for the start bit.
            end
 
          `STATE_wr_counts:
            begin
               if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
                  wr_bit_ct_en <= 1'b1;
                  user_word_ct_sel <= 1'b0;
 
                  if(wr_bit_count_max) begin
                     wr_bit_ct_rst <= 1'b1;
                     user_word_ct_en <= 1'b1;
                  end
               end
            end
 
          `STATE_wr_xfer:
            begin
               if(shift_dr_i) begin  // Don't do anything in PAUSE or EXIT states
                  wr_bit_ct_en <= 1'b1;
                  in_word_ct_sel <= 1'b1;
                  user_word_ct_sel <= 1'b1;
 
                  if(wr_bit_count_max) begin  // Start biu transactions, if word counts allow
                     wr_bit_ct_rst <= 1'b1;
 
                     if(!(in_word_count_zero || user_word_count_zero)) begin
                        biu_wr_strobe <= 1'b1;
                        in_word_ct_en <= 1'b1;
                        user_word_ct_en <= 1'b1;
                     end
 
                  end
               end
            end
 
          default: ;
        endcase
     end
 
   ////////////////////////////////////////
   // Output Control FSM
 
   // Definition of machine state values.
   // Don't worry too much about the state encoding, the synthesis tool
   // will probably re-encode it anyway.
 
`define STATE_rd_idle     4'h0
`define STATE_rd_counts   4'h1
`define STATE_rd_rdack   4'h2
`define STATE_rd_xfer  4'h3
 
// We do not send the equivalent of a 'start bit' (like the one the input FSM
// waits for when support for multi-device JTAG chains is enabled).  Since the
// input and output are going to be offset anyway, why bother...
 
   reg [2:0] rd_module_state;       // FSM state
   reg [2:0] rd_module_next_state;  // combinatorial signal, not actually a register
 
 
   // sequential part of the FSM
   always @ (posedge tck_i or posedge rst_i)
     begin
        if(rst_i)
          rd_module_state <= `STATE_rd_idle;
        else
          rd_module_state <= rd_module_next_state;
     end
 
 
   // Determination of next state; purely combinatorial
   always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)
     begin
        case(rd_module_state)
          `STATE_rd_idle:
            begin
               if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
               else rd_module_next_state <= `STATE_rd_idle;
            end
          `STATE_rd_counts:
            begin
               if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
               else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
               else rd_module_next_state <= `STATE_rd_counts;
            end
          `STATE_rd_rdack:
            begin
               if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
               else rd_module_next_state <= `STATE_rd_xfer;
            end
          `STATE_rd_xfer:
            begin
               if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
               else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
               else rd_module_next_state <= `STATE_rd_xfer;
            end
 
          default: rd_module_next_state <= `STATE_rd_idle;  // shouldn't actually happen...
        endcase
     end
 
 
   // Outputs of state machine, pure combinatorial
   always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i
             or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count
             or decremented_out_word_count)
     begin
        // Default everything to 0, keeps the case statement simple
        rd_bit_ct_en <= 1'b0;         // enable bit counter
        rd_bit_ct_rst <= 1'b0;        // reset (zero) bit count register
        out_word_ct_sel <= 1'b0;       // Selects data for byte counter.  0 = data_register_i, 1 = decremented byte count
        out_word_ct_en <= 1'b0;    // Enable output byte count register
        out_reg_ld_en <= 1'b0;     // Enable parallel load of data_out_shift_reg
        out_reg_shift_en <= 1'b0;  // Enable shift of data_out_shift_reg
        out_reg_data_sel <= 1'b0;  // 0 = BIU data, 1 = byte count data (also from BIU)
        biu_rd_strobe <= 1'b0;     // Indicates that the bus unit should ACK the last read operation + start another
 
        case(rd_module_state)
          `STATE_rd_idle:
            begin
               out_reg_data_sel <= 1'b1;
               out_word_ct_sel <= 1'b0;
 
               // Going to transfer; enable count registers and output register
               if(rd_module_next_state != `STATE_rd_idle) begin
                  out_reg_ld_en <= 1'b1;
                  rd_bit_ct_rst <= 1'b1;
                  out_word_ct_en <= 1'b1;
               end
            end
 
          `STATE_rd_counts:
            begin
               if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...
                  rd_bit_ct_en <= 1'b1;
                  out_reg_shift_en <= 1'b1;
 
                  if(rd_bit_count_max) begin
                     rd_bit_ct_rst <= 1'b1;
 
                     // Latch the next output word, but don't ack until STATE_rd_rdack
                     if(!out_word_count_zero) begin
                        out_reg_ld_en <= 1'b1;
                        out_reg_shift_en <= 1'b0;
                     end
                  end
               end
            end
 
          `STATE_rd_rdack:
            begin
               if(shift_dr_i) begin  // Don't do anything in PAUSE or EXIT states
                  rd_bit_ct_en <= 1'b1;
                  out_reg_shift_en <= 1'b1;
                  out_reg_data_sel <= 1'b0;
 
                  // Never have to worry about bit_count_max here.
 
                  if(!out_word_count_zero) begin
                     biu_rd_strobe <= 1'b1;
                  end
               end
            end
 
          `STATE_rd_xfer:
            begin
               if(shift_dr_i) begin  // Don't do anything in PAUSE or EXIT states
                  rd_bit_ct_en <= 1'b1;
                  out_word_ct_sel <= 1'b1;
                  out_reg_shift_en <= 1'b1;
                  out_reg_data_sel <= 1'b0;
 
                  if(rd_bit_count_max) begin  // Start biu transaction, if word count allows
                     rd_bit_ct_rst <= 1'b1;
 
                     // Don't ack the read byte here, we do it in STATE_rdack
                     if(!out_word_count_zero) begin
                        out_reg_ld_en <= 1'b1;
                        out_reg_shift_en <= 1'b0;
                        out_word_ct_en <= 1'b1;
                     end
                  end
               end
            end
 
          default: ;
        endcase
     end
 
 
endmodule
 

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[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_jsp_module.v] - Blame information for rev 51

Line No.	Rev	Author	Line
1	42	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_jsp_module.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Advanced Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15			`//// Copyright (C) 2010 Authors ////`
16			`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39
40
41			`include "adbg_defines.v"
42
43			`// Module interface`
44			`module adbg_jsp_module (`
45			`// JTAG signals`
46			`tck_i,`
47			`module_tdo_o,`
48			`tdi_i,`
49
50			`// TAP states`
51			`capture_dr_i,`
52			`shift_dr_i,`
53			`update_dr_i,`
54
55			`data_register_i, // the data register is at top level, shared between all modules`
56			`module_select_i,`
57			`top_inhibit_o,`
58			`rst_i,`
59
60			`// WISHBONE common signals`
61			`wb_clk_i, wb_rst_i,`
62
63			`// WISHBONE slave interface`
64			`wb_adr_i, wb_dat_o, wb_dat_i, wb_cyc_i, wb_stb_i, wb_sel_i,`
65			`wb_we_i, wb_ack_o, wb_cab_i, wb_err_o, wb_cti_i, wb_bte_i, int_o`
66			`);`
67
68			`// JTAG signals`
69			`input tck_i;`
70			`output module_tdo_o;`
71			`input tdi_i; // This is only used by the CRC module - data_register_i[MSB] is delayed a cycle`
72
73			`// TAP states`
74			`input capture_dr_i;`
75			`input shift_dr_i;`
76			`input update_dr_i;`
77
78			`input [52:0] data_register_i;`
79			`input module_select_i;`
80			`output top_inhibit_o;`
81			`input rst_i;`
82
83			`// WISHBONE slave interface`
84			`input wb_clk_i;`
85			`input wb_rst_i;`
86			`input [31:0] wb_adr_i;`
87			`output [31:0] wb_dat_o;`
88			`input [31:0] wb_dat_i;`
89			`input wb_cyc_i;`
90			`input wb_stb_i;`
91			`input [3:0] wb_sel_i;`
92			`input wb_we_i;`
93			`output wb_ack_o;`
94			`input wb_cab_i;`
95			`output wb_err_o;`
96			`input [2:0] wb_cti_i;`
97			`input [1:0] wb_bte_i;`
98			`output int_o;`
99
100			`// Declare inputs / outputs as wires / registers`
101			`wire module_tdo_o;`
102			`wire top_inhibit_o;`
103
104			`// NOTE: For the rest of this file, "input" and the "in" direction refer to bytes being transferred`
105			`// from the PC, through the JTAG, and into the BIU FIFO. The "output" direction refers to data being`
106			`// transferred from the BIU FIFO, through the JTAG to the PC.`
107
108			`// The read and write bit counts are separated to allow for JTAG chains with multiple devices.`
109			`// The read bit count starts right away (after a single throwaway bit), but the write count`
110			`// waits to receive a '1' start bit.`
111
112			`// Registers to hold state etc.`
113			`reg [3:0] read_bit_count; // How many bits have been shifted out`
114			`reg [3:0] write_bit_count; // How many bits have been shifted in`
115			`reg [3:0] input_word_count; // space (bytes) remaining in input FIFO (from JTAG)`
116			`reg [3:0] output_word_count; // bytes remaining in output FIFO (to JTAG)`
117			`reg [3:0] user_word_count; // bytes user intends to send from PC`
118			`reg [7:0] data_out_shift_reg; // parallel-load output shift register`
119
120
121			`// Control signals for the various counters / registers / state machines`
122			`reg rd_bit_ct_en; // enable bit counter`
123			`reg rd_bit_ct_rst; // reset (zero) bit count register`
124			`reg wr_bit_ct_en; // enable bit counter`
125			`reg wr_bit_ct_rst; // reset (zero) bit count register`
126			`reg in_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`
127			`reg out_word_ct_sel; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`
128			`reg in_word_ct_en; // Enable input byte counter register`
129			`reg out_word_ct_en; // Enable output byte count register`
130			`reg user_word_ct_en; // Enable user byte count registere`
131			`reg user_word_ct_sel; // selects data for user byte counter. 0 = user data, 1 = decremented byte count`
132			`reg out_reg_ld_en; // Enable parallel load of data_out_shift_reg`
133			`reg out_reg_shift_en; // Enable shift of data_out_shift_reg`
134			`reg out_reg_data_sel; // 0 = BIU data, 1 = byte count data (also from BIU)`
135			`reg biu_rd_strobe; // Indicates that the bus unit should ACK the last read operation + start another`
136			`reg biu_wr_strobe; // Indicates BIU should latch input + begin a write operation`
137
138
139			`// Status signals`
140			`wire in_word_count_zero; // true when input byte counter is zero`
141			`wire out_word_count_zero; // true when output byte counter is zero`
142			`wire user_word_count_zero; // true when user byte counter is zero`
143			`wire rd_bit_count_max; // true when bit counter is equal to current word size`
144			`wire wr_bit_count_max; // true when bit counter is equal to current word size`
145
146			`// Intermediate signals`
147			`wire [3:0] data_to_in_word_counter; // output of the mux in front of the input byte counter reg`
148			`wire [3:0] data_to_out_word_counter; // output of the mux in front of the output byte counter reg`
149			`wire [3:0] data_to_user_word_counter; // output of mux in front of user word counter`
150			`wire [3:0] decremented_in_word_count;`
151			`wire [3:0] decremented_out_word_count;`
152			`wire [3:0] decremented_user_word_count;`
153			`wire [3:0] count_data_in; // from data_register_i`
154			`wire [7:0] data_to_biu; // from data_register_i`
155			`wire [7:0] data_from_biu; // to data_out_shift_register`
156			`wire [3:0] biu_space_available;`
157			`wire [3:0] biu_bytes_available;`
158			`wire [7:0] count_data_from_biu; // combined space avail / bytes avail`
159			`wire [7:0] out_reg_data; // parallel input to the output shift register`
160
161
162			`/////////////////////////////////////////////////`
163			`// Combinatorial assignments`
164
165			`assign count_data_from_biu = {biu_bytes_available, biu_space_available};`
166			`assign count_data_in = {tdi_i, data_register_i[52:50]}; // Second nibble of user data`
167			`assign data_to_biu = {tdi_i,data_register_i[52:46]};`
168			`assign top_inhibit_o = 1'b0;`
169
170			`//////////////////////////////////////`
171			`// Input bit counter`
172
173			`always @ (posedge tck_i or posedge rst_i)`
174			`begin`
175			`if(rst_i) write_bit_count <= 4'h0;`
176			`else if(wr_bit_ct_rst) write_bit_count <= 4'h0;`
177			`else if(wr_bit_ct_en) write_bit_count <= write_bit_count + 4'h1;`
178			`end`
179
180			`assign wr_bit_count_max = (write_bit_count == 4'h7) ? 1'b1 : 1'b0;`
181
182			`//////////////////////////////////////`
183			`// Output bit counter`
184
185			`always @ (posedge tck_i or posedge rst_i)`
186			`begin`
187			`if(rst_i) read_bit_count <= 4'h0;`
188			`else if(rd_bit_ct_rst) read_bit_count <= 4'h0;`
189			`else if(rd_bit_ct_en) read_bit_count <= read_bit_count + 4'h1;`
190			`end`
191
192			`assign rd_bit_count_max = (read_bit_count == 4'h7) ? 1'b1 : 1'b0;`
193
194			`////////////////////////////////////////`
195			`// Input word counter`
196
197			`assign data_to_in_word_counter = (in_word_ct_sel) ? decremented_in_word_count : biu_space_available;`
198			`assign decremented_in_word_count = input_word_count - 4'h1;`
199
200			`always @ (posedge tck_i or posedge rst_i)`
201			`begin`
202			`if(rst_i)`
203			`input_word_count <= 4'h0;`
204			`else if(in_word_ct_en)`
205			`input_word_count <= data_to_in_word_counter;`
206			`end`
207
208			`assign in_word_count_zero = (input_word_count == 4'h0);`
209
210			`////////////////////////////////////////`
211			`// Output word counter`
212
213			`assign data_to_out_word_counter = (out_word_ct_sel) ? decremented_out_word_count : biu_bytes_available;`
214			`assign decremented_out_word_count = output_word_count - 4'h1;`
215
216			`always @ (posedge tck_i or posedge rst_i)`
217			`begin`
218			`if(rst_i)`
219			`output_word_count <= 4'h0;`
220			`else if(out_word_ct_en)`
221			`output_word_count <= data_to_out_word_counter;`
222			`end`
223
224			`assign out_word_count_zero = (output_word_count == 4'h0);`
225
226			`////////////////////////////////////////`
227			`// User word counter`
228
229			`assign data_to_user_word_counter = (user_word_ct_sel) ? decremented_user_word_count : count_data_in;`
230			`assign decremented_user_word_count = user_word_count - 4'h1;`
231
232			`always @ (posedge tck_i or posedge rst_i)`
233			`begin`
234			`if(rst_i) user_word_count <= 4'h0;`
235			`else if(user_word_ct_en) user_word_count <= data_to_user_word_counter;`
236			`end`
237
238			`assign user_word_count_zero = (user_word_count == 4'h0);`
239
240			`/////////////////////////////////////////////////////`
241			`// Output register and TDO output MUX`
242
243			`assign out_reg_data = (out_reg_data_sel) ? count_data_from_biu : data_from_biu;`
244
245			`always @ (posedge tck_i or posedge rst_i)`
246			`begin`
247			`if(rst_i) data_out_shift_reg <= 8'h0;`
248			`else if(out_reg_ld_en) data_out_shift_reg <= out_reg_data;`
249			`else if(out_reg_shift_en) data_out_shift_reg <= {1'b0, data_out_shift_reg[7:1]};`
250			`end`
251
252			`assign module_tdo_o = data_out_shift_reg[0];`
253
254			`////////////////////////////////////////`
255			`// Bus Interface Unit (to JTAG / WB UART)`
256			`// It is assumed that the BIU has internal registers, and will`
257			`// latch write data (and ack read data) on rising clock edge`
258			`// when strobe is asserted`
259
260			`adbg_jsp_biu jsp_biu_i (`
261			`// Debug interface signals`
262			`.tck_i (tck_i),`
263			`.rst_i (rst_i),`
264			`.data_i (data_to_biu),`
265			`.data_o (data_from_biu),`
266			`.bytes_available_o (biu_bytes_available),`
267			`.bytes_free_o (biu_space_available),`
268			`.rd_strobe_i (biu_rd_strobe),`
269			`.wr_strobe_i (biu_wr_strobe),`
270
271			`// Wishbone slave signals`
272			`.wb_clk_i (wb_clk_i),`
273			`.wb_rst_i (wb_rst_i),`
274			`.wb_adr_i (wb_adr_i),`
275			`.wb_dat_o (wb_dat_o),`
276			`.wb_dat_i (wb_dat_i),`
277			`.wb_cyc_i (wb_cyc_i),`
278			`.wb_stb_i (wb_stb_i),`
279			`.wb_sel_i (wb_sel_i),`
280			`.wb_we_i (wb_we_i),`
281			`.wb_ack_o (wb_ack_o),`
282			`.wb_cab_i (wb_cab_i),`
283			`.wb_err_o (wb_err_o),`
284			`.wb_cti_i (wb_cti_i),`
285			`.wb_bte_i (wb_bte_i),`
286			`.int_o (int_o)`
287			`);`
288
289
290			`////////////////////////////////////////`
291			`// Input Control FSM`
292
293			`// Definition of machine state values.`
294			`// Don't worry too much about the state encoding, the synthesis tool`
295			`// will probably re-encode it anyway.`
296
297			`define STATE_wr_idle 3'h0
298			`define STATE_wr_wait 3'h1
299			`define STATE_wr_counts 3'h2
300			`define STATE_wr_xfer 3'h3
301
302			`reg [2:0] wr_module_state; // FSM state`
303			`reg [2:0] wr_module_next_state; // combinatorial signal, not actually a register`
304
305
306			`// sequential part of the FSM`
307			`always @ (posedge tck_i or posedge rst_i)`
308			`begin`
309			`if(rst_i)`
310			wr_module_state <= `STATE_wr_idle;
311			`else`
312			`wr_module_state <= wr_module_next_state;`
313			`end`
314
315
316			`// Determination of next state; purely combinatorial`
317			`always @ (wr_module_state or module_select_i or update_dr_i or capture_dr_i`
318			`or shift_dr_i or wr_bit_count_max or tdi_i)`
319			`begin`
320			`case(wr_module_state)`
321			`STATE_wr_idle:
322			`begin`
323			`ifdef ADBG_JSP_SUPPORT_MULTI
324			if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_wait;
325			`else
326			if(module_select_i && capture_dr_i) wr_module_next_state <= `STATE_wr_counts;
327			`endif
328			else wr_module_next_state <= `STATE_wr_idle;
329			`end`
330			`STATE_wr_wait:
331			`begin`
332			if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
333			else if(module_select_i && tdi_i) wr_module_next_state <= `STATE_wr_counts; // got start bit
334			else wr_module_next_state <= `STATE_wr_wait;
335			`end`
336			`STATE_wr_counts:
337			`begin`
338			if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
339			else if(wr_bit_count_max) wr_module_next_state <= `STATE_wr_xfer;
340			else wr_module_next_state <= `STATE_wr_counts;
341			`end`
342
343			`STATE_wr_xfer:
344			`begin`
345			if(update_dr_i) wr_module_next_state <= `STATE_wr_idle;
346			else wr_module_next_state <= `STATE_wr_xfer;
347			`end`
348
349			default: wr_module_next_state <= `STATE_wr_idle; // shouldn't actually happen...
350			`endcase`
351			`end`
352
353
354			`// Outputs of state machine, pure combinatorial`
355			`always @ (wr_module_state or wr_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i`
356			`or in_word_count_zero or out_word_count_zero or wr_bit_count_max or decremented_in_word_count`
357	51	nyawn	`or decremented_out_word_count or user_word_count_zero)`
358	42	nyawn	`begin`
359			`// Default everything to 0, keeps the case statement simple`
360			`wr_bit_ct_en <= 1'b0; // enable bit counter`
361			`wr_bit_ct_rst <= 1'b0; // reset (zero) bit count register`
362			`in_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`
363			`user_word_ct_sel <= 1'b0; // selects data for user byte counter, 0 = user data, 1 = decremented count`
364			`in_word_ct_en <= 1'b0; // Enable input byte counter register`
365			`user_word_ct_en <= 1'b0; // enable user byte count register`
366			`biu_wr_strobe <= 1'b0; // Indicates BIU should latch input + begin a write operation`
367
368			`case(wr_module_state)`
369			`STATE_wr_idle:
370			`begin`
371			`in_word_ct_sel <= 1'b0;`
372
373			`// Going to transfer; enable count registers and output register`
374			if(wr_module_next_state != `STATE_wr_idle) begin
375			`wr_bit_ct_rst <= 1'b1;`
376			`in_word_ct_en <= 1'b1;`
377			`end`
378			`end`
379
380			`// This state is only used when support for multi-device JTAG chains is enabled.`
381			`STATE_wr_wait:
382			`begin`
383			`wr_bit_ct_en <= 1'b0; // Don't do anything, just wait for the start bit.`
384			`end`
385
386			`STATE_wr_counts:
387			`begin`
388			`if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...`
389			`wr_bit_ct_en <= 1'b1;`
390			`user_word_ct_sel <= 1'b0;`
391
392			`if(wr_bit_count_max) begin`
393			`wr_bit_ct_rst <= 1'b1;`
394			`user_word_ct_en <= 1'b1;`
395			`end`
396			`end`
397			`end`
398
399			`STATE_wr_xfer:
400			`begin`
401			`if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states`
402			`wr_bit_ct_en <= 1'b1;`
403			`in_word_ct_sel <= 1'b1;`
404			`user_word_ct_sel <= 1'b1;`
405
406			`if(wr_bit_count_max) begin // Start biu transactions, if word counts allow`
407			`wr_bit_ct_rst <= 1'b1;`
408
409			`if(!(in_word_count_zero \|\| user_word_count_zero)) begin`
410			`biu_wr_strobe <= 1'b1;`
411			`in_word_ct_en <= 1'b1;`
412			`user_word_ct_en <= 1'b1;`
413			`end`
414
415			`end`
416			`end`
417			`end`
418
419			`default: ;`
420			`endcase`
421			`end`
422
423			`////////////////////////////////////////`
424			`// Output Control FSM`
425
426			`// Definition of machine state values.`
427			`// Don't worry too much about the state encoding, the synthesis tool`
428			`// will probably re-encode it anyway.`
429
430			`define STATE_rd_idle 4'h0
431			`define STATE_rd_counts 4'h1
432			`define STATE_rd_rdack 4'h2
433			`define STATE_rd_xfer 4'h3
434
435			`// We do not send the equivalent of a 'start bit' (like the one the input FSM`
436			`// waits for when support for multi-device JTAG chains is enabled). Since the`
437			`// input and output are going to be offset anyway, why bother...`
438
439			`reg [2:0] rd_module_state; // FSM state`
440			`reg [2:0] rd_module_next_state; // combinatorial signal, not actually a register`
441
442
443			`// sequential part of the FSM`
444			`always @ (posedge tck_i or posedge rst_i)`
445			`begin`
446			`if(rst_i)`
447			rd_module_state <= `STATE_rd_idle;
448			`else`
449			`rd_module_state <= rd_module_next_state;`
450			`end`
451
452
453			`// Determination of next state; purely combinatorial`
454			`always @ (rd_module_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i or rd_bit_count_max)`
455			`begin`
456			`case(rd_module_state)`
457			`STATE_rd_idle:
458			`begin`
459			if(module_select_i && capture_dr_i) rd_module_next_state <= `STATE_rd_counts;
460			else rd_module_next_state <= `STATE_rd_idle;
461			`end`
462			`STATE_rd_counts:
463			`begin`
464			if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
465			else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
466			else rd_module_next_state <= `STATE_rd_counts;
467			`end`
468			`STATE_rd_rdack:
469			`begin`
470			if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
471			else rd_module_next_state <= `STATE_rd_xfer;
472			`end`
473			`STATE_rd_xfer:
474			`begin`
475			if(update_dr_i) rd_module_next_state <= `STATE_rd_idle;
476			else if(rd_bit_count_max) rd_module_next_state <= `STATE_rd_rdack;
477			else rd_module_next_state <= `STATE_rd_xfer;
478			`end`
479
480			default: rd_module_next_state <= `STATE_rd_idle; // shouldn't actually happen...
481			`endcase`
482			`end`
483
484
485			`// Outputs of state machine, pure combinatorial`
486			`always @ (rd_module_state or rd_module_next_state or module_select_i or update_dr_i or capture_dr_i or shift_dr_i`
487			`or in_word_count_zero or out_word_count_zero or rd_bit_count_max or decremented_in_word_count`
488			`or decremented_out_word_count)`
489			`begin`
490			`// Default everything to 0, keeps the case statement simple`
491			`rd_bit_ct_en <= 1'b0; // enable bit counter`
492			`rd_bit_ct_rst <= 1'b0; // reset (zero) bit count register`
493			`out_word_ct_sel <= 1'b0; // Selects data for byte counter. 0 = data_register_i, 1 = decremented byte count`
494			`out_word_ct_en <= 1'b0; // Enable output byte count register`
495			`out_reg_ld_en <= 1'b0; // Enable parallel load of data_out_shift_reg`
496			`out_reg_shift_en <= 1'b0; // Enable shift of data_out_shift_reg`
497			`out_reg_data_sel <= 1'b0; // 0 = BIU data, 1 = byte count data (also from BIU)`
498			`biu_rd_strobe <= 1'b0; // Indicates that the bus unit should ACK the last read operation + start another`
499
500			`case(rd_module_state)`
501			`STATE_rd_idle:
502			`begin`
503			`out_reg_data_sel <= 1'b1;`
504			`out_word_ct_sel <= 1'b0;`
505
506			`// Going to transfer; enable count registers and output register`
507			if(rd_module_next_state != `STATE_rd_idle) begin
508			`out_reg_ld_en <= 1'b1;`
509			`rd_bit_ct_rst <= 1'b1;`
510			`out_word_ct_en <= 1'b1;`
511			`end`
512			`end`
513
514			`STATE_rd_counts:
515			`begin`
516			`if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states...`
517			`rd_bit_ct_en <= 1'b1;`
518			`out_reg_shift_en <= 1'b1;`
519
520			`if(rd_bit_count_max) begin`
521			`rd_bit_ct_rst <= 1'b1;`
522
523			`// Latch the next output word, but don't ack until STATE_rd_rdack`
524			`if(!out_word_count_zero) begin`
525			`out_reg_ld_en <= 1'b1;`
526			`out_reg_shift_en <= 1'b0;`
527			`end`
528			`end`
529			`end`
530			`end`
531
532			`STATE_rd_rdack:
533			`begin`
534			`if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states`
535			`rd_bit_ct_en <= 1'b1;`
536			`out_reg_shift_en <= 1'b1;`
537			`out_reg_data_sel <= 1'b0;`
538
539			`// Never have to worry about bit_count_max here.`
540
541			`if(!out_word_count_zero) begin`
542			`biu_rd_strobe <= 1'b1;`
543			`end`
544			`end`
545			`end`
546
547			`STATE_rd_xfer:
548			`begin`
549			`if(shift_dr_i) begin // Don't do anything in PAUSE or EXIT states`
550			`rd_bit_ct_en <= 1'b1;`
551			`out_word_ct_sel <= 1'b1;`
552			`out_reg_shift_en <= 1'b1;`
553			`out_reg_data_sel <= 1'b0;`
554
555			`if(rd_bit_count_max) begin // Start biu transaction, if word count allows`
556			`rd_bit_ct_rst <= 1'b1;`
557
558			`// Don't ack the read byte here, we do it in STATE_rdack`
559			`if(!out_word_count_zero) begin`
560			`out_reg_ld_en <= 1'b1;`
561			`out_reg_shift_en <= 1'b0;`
562			`out_word_ct_en <= 1'b1;`
563			`end`
564			`end`
565			`end`
566			`end`
567
568			`default: ;`
569			`endcase`
570			`end`
571
572
573			`endmodule`
574