URL https://opencores.org/ocsvn/adv_debug_sys/adv_debug_sys/trunk

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_top.v] - Blame information for rev 42

Details | Compare with Previous | View Log


//////////////////////////////////////////////////////////////////////
////                                                              ////
////  adbg_top.v                                                  ////
////                                                              ////
////                                                              ////
////  This file is part of the SoC Advanced Debug Interface.      ////
////                                                              ////
////  Author(s):                                                  ////
////       Nathan Yawn (nathan.yawn@opencores.org)                ////
////                                                              ////
////                                                              ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008-2010 Authors                              ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
 
`include "adbg_defines.v"
 
 
// Top module
module adbg_top(
                // JTAG signals
                tck_i,
                tdi_i,
                tdo_o,
                rst_i,
 
 
                // TAP states
                shift_dr_i,
                pause_dr_i,
                update_dr_i,
                capture_dr_i,
 
                // Instructions
                debug_select_i
 
 
                `ifdef DBG_WISHBONE_SUPPORTED
                // WISHBONE common signals
                ,
                wb_clk_i,
                wb_rst_i,
 
                // WISHBONE master interface
                wb_adr_o,
                wb_dat_o,
                wb_dat_i,
                wb_cyc_o,
                wb_stb_o,
                wb_sel_o,
                wb_we_o,
                wb_ack_i,
                wb_cab_o,
                wb_err_i,
                wb_cti_o,
                wb_bte_o
                `endif
 
                `ifdef DBG_CPU0_SUPPORTED
                // CPU signals
                ,
                cpu0_clk_i,
                cpu0_addr_o,
                cpu0_data_i,
                cpu0_data_o,
                cpu0_bp_i,
                cpu0_stall_o,
                cpu0_stb_o,
                cpu0_we_o,
                cpu0_ack_i,
                cpu0_rst_o
                `endif
 
                `ifdef DBG_CPU1_SUPPORTED
                // CPU signals
                ,
                cpu1_clk_i,
                cpu1_addr_o,
                cpu1_data_i,
                cpu1_data_o,
                cpu1_bp_i,
                cpu1_stall_o,
                cpu1_stb_o,
                cpu1_we_o,
                cpu1_ack_i,
                cpu1_rst_o
                `endif
 
                `ifdef DBG_JSP_SUPPORTED
                ,
                `ifndef DBG_WISHBONE_SUPPORTED
                wb_clk_i,
                wb_rst_i,
                `endif
 
                // WISHBONE target interface
                wb_jsp_adr_i,
                wb_jsp_dat_o,
                wb_jsp_dat_i,
                wb_jsp_cyc_i,
                wb_jsp_stb_i,
                wb_jsp_sel_i,
                wb_jsp_we_i,
                wb_jsp_ack_o,
                wb_jsp_cab_i,
                wb_jsp_err_o,
                wb_jsp_cti_i,
                wb_jsp_bte_i,
                int_o
                `endif
 
                );
 
 
   // JTAG signals
   input   tck_i;
   input   tdi_i;
   output  tdo_o;
   input   rst_i;
 
   // TAP states
   input   shift_dr_i;
   input   pause_dr_i;
   input   update_dr_i;
   input   capture_dr_i;
 
   // Module select from TAP
   input   debug_select_i;
 
`ifdef DBG_WISHBONE_SUPPORTED
   input   wb_clk_i;
   input   wb_rst_i;
   output [31:0] wb_adr_o;
   output [31:0] wb_dat_o;
   input [31:0]  wb_dat_i;
   output        wb_cyc_o;
   output        wb_stb_o;
   output [3:0]  wb_sel_o;
   output        wb_we_o;
   input         wb_ack_i;
   output        wb_cab_o;
   input         wb_err_i;
   output [2:0]  wb_cti_o;
   output [1:0]  wb_bte_o;
`endif
 
`ifdef DBG_CPU0_SUPPORTED
   // CPU signals
   input         cpu0_clk_i;
   output [31:0] cpu0_addr_o;
   input [31:0]  cpu0_data_i;
   output [31:0] cpu0_data_o;
   input         cpu0_bp_i;
   output        cpu0_stall_o;
   output        cpu0_stb_o;
   output        cpu0_we_o;
   input         cpu0_ack_i;
   output        cpu0_rst_o;
`endif
 
`ifdef DBG_CPU1_SUPPORTED
   input         cpu1_clk_i;
   output [31:0] cpu1_addr_o;
   input [31:0]  cpu1_data_i;
   output [31:0] cpu1_data_o;
   input         cpu1_bp_i;
   output        cpu1_stall_o;
   output        cpu1_stb_o;
   output        cpu1_we_o;
   input         cpu1_ack_i;
   output        cpu1_rst_o;
`endif
 
`ifdef DBG_JSP_SUPPORTED
   `ifndef DBG_WISHBONE_SUPPORTED
   input   wb_clk_i;
   input   wb_rst_i;
   `endif
   input [31:0]  wb_jsp_adr_i;
   output [31:0] wb_jsp_dat_o;
   input [31:0]  wb_jsp_dat_i;
   input         wb_jsp_cyc_i;
   input         wb_jsp_stb_i;
   input [3:0]   wb_jsp_sel_i;
   input         wb_jsp_we_i;
   output        wb_jsp_ack_o;
   input         wb_jsp_cab_i;
   output        wb_jsp_err_o;
   input [2:0]   wb_jsp_cti_i;
   input [1:0]   wb_jsp_bte_i;
   output        int_o;
`endif
 
   reg           tdo_o;
   wire          tdo_wb;
   wire          tdo_cpu0;
   wire          tdo_cpu1;
   wire          tdo_jsp;
 
   // Registers
   reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg;  // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
   //reg output_shift_reg;  // Just 1 bit for status (valid module selected)
   reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg;   // Module selection register
 
 
   // Control signals
   wire                                 select_cmd;  // True when the command (registered at Update_DR) is for top level/module selection
   wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in;    // The part of the input_shift_register to be used as the module select data
   reg [(`DBG_TOP_MAX_MODULES - 1) : 0]       module_selects;  // Select signals for the individual modules
   wire                                       select_inhibit;  // OR of inhibit signals from sub-modules, prevents latching of a new module ID
   wire [3:0]                                  module_inhibit;  // signals to allow submodules to prevent top level from latching new module ID
 
   ///////////////////////////////////////
   // Combinatorial assignments
 
assign select_cmd = input_shift_reg[52];
assign module_id_in = input_shift_reg[51:50];
 
//////////////////////////////////////////////////////////
// Module select register and select signals
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    module_id_reg <= 2'b0;
  else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit)       // Chain select
    module_id_reg <= module_id_in;
end
 
 
always @ (module_id_reg)
begin
        module_selects <= `DBG_TOP_MODULE_ID_LENGTH'h0;
        module_selects[module_id_reg] <= 1'b1;
end
 
///////////////////////////////////////////////
// Data input shift register
 
always @ (posedge tck_i or posedge rst_i)
begin
  if (rst_i)
    input_shift_reg <= 53'h0;
  else if(debug_select_i && shift_dr_i)
    input_shift_reg <= {tdi_i, input_shift_reg[52:1]};
end
 
 
//////////////////////////////////////////////
// Debug module instantiations
 
`ifdef DBG_WISHBONE_SUPPORTED
// Connecting wishbone module
adbg_wb_module i_dbg_wb (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_wb),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
                  .top_inhibit_o     (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // WISHBONE common signals
                  .wb_clk_i         (wb_clk_i),
 
                  // WISHBONE master interface
                  .wb_adr_o         (wb_adr_o),
                  .wb_dat_o         (wb_dat_o),
                  .wb_dat_i         (wb_dat_i),
                  .wb_cyc_o         (wb_cyc_o),
                  .wb_stb_o         (wb_stb_o),
                  .wb_sel_o         (wb_sel_o),
                  .wb_we_o          (wb_we_o),
                  .wb_ack_i         (wb_ack_i),
                  .wb_cab_o         (wb_cab_o),
                  .wb_err_i         (wb_err_i),
                  .wb_cti_o         (wb_cti_o),
                  .wb_bte_o         (wb_bte_o)
            );
`else
assign tdo_wb = 1'b0;
assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
`endif
 
 
 
`ifdef DBG_CPU0_SUPPORTED
adbg_or1k_module i_dbg_cpu_or1k (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_cpu0),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
                  .top_inhibit_o     (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // CPU signals
                  .cpu_clk_i        (cpu0_clk_i),
                  .cpu_addr_o       (cpu0_addr_o),
                  .cpu_data_i       (cpu0_data_i),
                  .cpu_data_o       (cpu0_data_o),
                  .cpu_bp_i         (cpu0_bp_i),
                  .cpu_stall_o      (cpu0_stall_o),
                  .cpu_stb_o        (cpu0_stb_o),
                  .cpu_we_o         (cpu0_we_o),
                  .cpu_ack_i        (cpu0_ack_i),
                  .cpu_rst_o        (cpu0_rst_o)
              );
`else
assign tdo_cpu0 = 1'b0;
assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
`endif  //  DBG_CPU0_SUPPORTED
 
 
 
`ifdef DBG_CPU1_SUPPORTED
// Connecting cpu module
adbg_or1k_module i_dbg_cpu_2 (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_cpu1),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
                  .top_inhibit_o    (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // CPU signals
                  .cpu_clk_i        (cpu1_clk_i),
                  .cpu_addr_o       (cpu1_addr_o),
                  .cpu_data_i       (cpu1_data_i),
                  .cpu_data_o       (cpu1_data_o),
                  .cpu_bp_i         (cpu1_bp_i),
                  .cpu_stall_o      (cpu1_stall_o),
                  .cpu_stb_o        (cpu1_stb_o),
                  .cpu_we_o         (cpu1_we_o),
                  .cpu_ack_i        (cpu1_ack_i),
                  .cpu_rst_o        (cpu1_rst_o)
              );
`else
assign tdo_cpu1 = 1'b0;
assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
`endif
 
`ifdef DBG_JSP_SUPPORTED
adbg_jsp_module i_dbg_jsp (
                  // JTAG signals
                  .tck_i            (tck_i),
                  .module_tdo_o     (tdo_jsp),
                  .tdi_i            (tdi_i),
 
                  // TAP states
                  .capture_dr_i     (capture_dr_i),
                  .shift_dr_i       (shift_dr_i),
                  .update_dr_i      (update_dr_i),
 
                  .data_register_i  (input_shift_reg),
                  .module_select_i  (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
                  .top_inhibit_o     (module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE]),
                  .rst_i            (rst_i),
 
                  // WISHBONE common signals
                  .wb_clk_i         (wb_clk_i),
                  .wb_rst_i         (wb_rst_i),
 
                  // WISHBONE master interface
                  .wb_adr_i         (wb_jsp_adr_i),
                  .wb_dat_o         (wb_jsp_dat_o),
                  .wb_dat_i         (wb_jsp_dat_i),
                  .wb_cyc_i         (wb_jsp_cyc_i),
                  .wb_stb_i         (wb_jsp_stb_i),
                  .wb_sel_i         (wb_jsp_sel_i),
                  .wb_we_i          (wb_jsp_we_i),
                  .wb_ack_o         (wb_jsp_ack_o),
                  .wb_cab_i         (wb_jsp_cab_i),
                  .wb_err_o         (wb_jsp_err_o),
                  .wb_cti_i         (wb_jsp_cti_i),
                  .wb_bte_i         (wb_jsp_bte_i),
                  .int_o            (int_o)
            );
 
`else
   assign tdo_jsp = 1'b0;
   assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
`endif
 
assign select_inhibit = |module_inhibit;
 
/////////////////////////////////////////////////
// TDO output MUX
 
always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)
begin
   case (module_id_reg)
     `DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
     `DBG_TOP_CPU0_DEBUG_MODULE:     tdo_o <= tdo_cpu0;
     `DBG_TOP_CPU1_DEBUG_MODULE:     tdo_o <= tdo_cpu1;
     `DBG_TOP_JSP_DEBUG_MODULE:      tdo_o <= tdo_jsp;
       default:                        tdo_o <= 1'b0;
   endcase
end
 
 
endmodule

Line No.	Rev	Author	Line
1	3	nyawn	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// adbg_top.v ////`
4			`//// ////`
5			`//// ////`
6			`//// This file is part of the SoC Advanced Debug Interface. ////`
7			`//// ////`
8			`//// Author(s): ////`
9			`//// Nathan Yawn (nathan.yawn@opencores.org) ////`
10			`//// ////`
11			`//// ////`
12			`//// ////`
13			`//////////////////////////////////////////////////////////////////////`
14			`//// ////`
15	32	nyawn	`//// Copyright (C) 2008-2010 Authors ////`
16	3	nyawn	`//// ////`
17			`//// This source file may be used and distributed without ////`
18			`//// restriction provided that this copyright statement is not ////`
19			`//// removed from the file and that any derivative work contains ////`
20			`//// the original copyright notice and the associated disclaimer. ////`
21			`//// ////`
22			`//// This source file is free software; you can redistribute it ////`
23			`//// and/or modify it under the terms of the GNU Lesser General ////`
24			`//// Public License as published by the Free Software Foundation; ////`
25			`//// either version 2.1 of the License, or (at your option) any ////`
26			`//// later version. ////`
27			`//// ////`
28			`//// This source is distributed in the hope that it will be ////`
29			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
30			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
31			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
32			`//// details. ////`
33			`//// ////`
34			`//// You should have received a copy of the GNU Lesser General ////`
35			`//// Public License along with this source; if not, download it ////`
36			`//// from http://www.opencores.org/lgpl.shtml ////`
37			`//// ////`
38			`//////////////////////////////////////////////////////////////////////`
39
40
41			`include "adbg_defines.v"
42
43
44			`// Top module`
45			`module adbg_top(`
46			`// JTAG signals`
47			`tck_i,`
48			`tdi_i,`
49			`tdo_o,`
50			`rst_i,`
51
52
53			`// TAP states`
54			`shift_dr_i,`
55			`pause_dr_i,`
56			`update_dr_i,`
57			`capture_dr_i,`
58
59			`// Instructions`
60			`debug_select_i`
61
62
63			`ifdef DBG_WISHBONE_SUPPORTED
64			`// WISHBONE common signals`
65			`,`
66			`wb_clk_i,`
67	42	nyawn	`wb_rst_i,`
68
69	3	nyawn	`// WISHBONE master interface`
70			`wb_adr_o,`
71			`wb_dat_o,`
72			`wb_dat_i,`
73			`wb_cyc_o,`
74			`wb_stb_o,`
75			`wb_sel_o,`
76			`wb_we_o,`
77			`wb_ack_i,`
78			`wb_cab_o,`
79			`wb_err_i,`
80			`wb_cti_o,`
81			`wb_bte_o`
82			`endif
83
84			`ifdef DBG_CPU0_SUPPORTED
85			`// CPU signals`
86			`,`
87			`cpu0_clk_i,`
88			`cpu0_addr_o,`
89			`cpu0_data_i,`
90			`cpu0_data_o,`
91			`cpu0_bp_i,`
92			`cpu0_stall_o,`
93			`cpu0_stb_o,`
94			`cpu0_we_o,`
95			`cpu0_ack_i,`
96			`cpu0_rst_o`
97			`endif
98
99			`ifdef DBG_CPU1_SUPPORTED
100			`// CPU signals`
101			`,`
102			`cpu1_clk_i,`
103			`cpu1_addr_o,`
104			`cpu1_data_i,`
105			`cpu1_data_o,`
106			`cpu1_bp_i,`
107			`cpu1_stall_o,`
108			`cpu1_stb_o,`
109			`cpu1_we_o,`
110			`cpu1_ack_i,`
111			`cpu1_rst_o`
112			`endif
113	42	nyawn
114			`ifdef DBG_JSP_SUPPORTED
115			`,`
116			`ifndef DBG_WISHBONE_SUPPORTED
117			`wb_clk_i,`
118			`wb_rst_i,`
119			`endif
120
121			`// WISHBONE target interface`
122			`wb_jsp_adr_i,`
123			`wb_jsp_dat_o,`
124			`wb_jsp_dat_i,`
125			`wb_jsp_cyc_i,`
126			`wb_jsp_stb_i,`
127			`wb_jsp_sel_i,`
128			`wb_jsp_we_i,`
129			`wb_jsp_ack_o,`
130			`wb_jsp_cab_i,`
131			`wb_jsp_err_o,`
132			`wb_jsp_cti_i,`
133			`wb_jsp_bte_i,`
134			`int_o`
135			`endif
136
137	3	nyawn	`);`
138
139
140			`// JTAG signals`
141			`input tck_i;`
142			`input tdi_i;`
143			`output tdo_o;`
144			`input rst_i;`
145
146			`// TAP states`
147			`input shift_dr_i;`
148			`input pause_dr_i;`
149			`input update_dr_i;`
150			`input capture_dr_i;`
151
152			`// Module select from TAP`
153			`input debug_select_i;`
154
155	42	nyawn	`ifdef DBG_WISHBONE_SUPPORTED
156	3	nyawn	`input wb_clk_i;`
157	42	nyawn	`input wb_rst_i;`
158	3	nyawn	`output [31:0] wb_adr_o;`
159			`output [31:0] wb_dat_o;`
160			`input [31:0] wb_dat_i;`
161			`output wb_cyc_o;`
162			`output wb_stb_o;`
163			`output [3:0] wb_sel_o;`
164			`output wb_we_o;`
165			`input wb_ack_i;`
166			`output wb_cab_o;`
167			`input wb_err_i;`
168			`output [2:0] wb_cti_o;`
169			`output [1:0] wb_bte_o;`
170	42	nyawn	`endif
171	3	nyawn
172	42	nyawn	`ifdef DBG_CPU0_SUPPORTED
173	3	nyawn	`// CPU signals`
174			`input cpu0_clk_i;`
175			`output [31:0] cpu0_addr_o;`
176			`input [31:0] cpu0_data_i;`
177			`output [31:0] cpu0_data_o;`
178			`input cpu0_bp_i;`
179			`output cpu0_stall_o;`
180			`output cpu0_stb_o;`
181			`output cpu0_we_o;`
182			`input cpu0_ack_i;`
183			`output cpu0_rst_o;`
184	42	nyawn	`endif
185	3	nyawn
186	42	nyawn	`ifdef DBG_CPU1_SUPPORTED
187	3	nyawn	`input cpu1_clk_i;`
188			`output [31:0] cpu1_addr_o;`
189			`input [31:0] cpu1_data_i;`
190			`output [31:0] cpu1_data_o;`
191			`input cpu1_bp_i;`
192			`output cpu1_stall_o;`
193			`output cpu1_stb_o;`
194			`output cpu1_we_o;`
195			`input cpu1_ack_i;`
196			`output cpu1_rst_o;`
197	42	nyawn	`endif
198	3	nyawn
199	42	nyawn	`ifdef DBG_JSP_SUPPORTED
200			`ifndef DBG_WISHBONE_SUPPORTED
201			`input wb_clk_i;`
202			`input wb_rst_i;`
203			`endif
204			`input [31:0] wb_jsp_adr_i;`
205			`output [31:0] wb_jsp_dat_o;`
206			`input [31:0] wb_jsp_dat_i;`
207			`input wb_jsp_cyc_i;`
208			`input wb_jsp_stb_i;`
209			`input [3:0] wb_jsp_sel_i;`
210			`input wb_jsp_we_i;`
211			`output wb_jsp_ack_o;`
212			`input wb_jsp_cab_i;`
213			`output wb_jsp_err_o;`
214			`input [2:0] wb_jsp_cti_i;`
215			`input [1:0] wb_jsp_bte_i;`
216			`output int_o;`
217			`endif
218
219	3	nyawn	`reg tdo_o;`
220			`wire tdo_wb;`
221			`wire tdo_cpu0;`
222			`wire tdo_cpu1;`
223	42	nyawn	`wire tdo_jsp;`
224	3	nyawn
225			`// Registers`
226			reg [`DBG_TOP_MODULE_DATA_LEN-1:0] input_shift_reg; // 1 bit sel/cmd, 4 bit opcode, 32 bit address, 16 bit length = 53 bits
227			`//reg output_shift_reg; // Just 1 bit for status (valid module selected)`
228			reg [`DBG_TOP_MODULE_ID_LENGTH -1:0] module_id_reg; // Module selection register
229
230
231			`// Control signals`
232			`wire select_cmd; // True when the command (registered at Update_DR) is for top level/module selection`
233			wire [(`DBG_TOP_MODULE_ID_LENGTH - 1) : 0] module_id_in; // The part of the input_shift_register to be used as the module select data
234			reg [(`DBG_TOP_MAX_MODULES - 1) : 0] module_selects; // Select signals for the individual modules
235			`wire select_inhibit; // OR of inhibit signals from sub-modules, prevents latching of a new module ID`
236	42	nyawn	`wire [3:0] module_inhibit; // signals to allow submodules to prevent top level from latching new module ID`
237	3	nyawn
238			`///////////////////////////////////////`
239			`// Combinatorial assignments`
240
241			`assign select_cmd = input_shift_reg[52];`
242			`assign module_id_in = input_shift_reg[51:50];`
243
244			`//////////////////////////////////////////////////////////`
245			`// Module select register and select signals`
246
247			`always @ (posedge tck_i or posedge rst_i)`
248			`begin`
249			`if (rst_i)`
250			`module_id_reg <= 2'b0;`
251			`else if(debug_select_i && select_cmd && update_dr_i && !select_inhibit) // Chain select`
252			`module_id_reg <= module_id_in;`
253			`end`
254
255
256			`always @ (module_id_reg)`
257			`begin`
258			module_selects <= `DBG_TOP_MODULE_ID_LENGTH'h0;
259			`module_selects[module_id_reg] <= 1'b1;`
260			`end`
261
262			`///////////////////////////////////////////////`
263			`// Data input shift register`
264
265			`always @ (posedge tck_i or posedge rst_i)`
266			`begin`
267			`if (rst_i)`
268			`input_shift_reg <= 53'h0;`
269			`else if(debug_select_i && shift_dr_i)`
270			`input_shift_reg <= {tdi_i, input_shift_reg[52:1]};`
271			`end`
272
273
274			`//////////////////////////////////////////////`
275			`// Debug module instantiations`
276
277			`ifdef DBG_WISHBONE_SUPPORTED
278			`// Connecting wishbone module`
279			`adbg_wb_module i_dbg_wb (`
280			`// JTAG signals`
281			`.tck_i (tck_i),`
282			`.module_tdo_o (tdo_wb),`
283			`.tdi_i (tdi_i),`
284
285			`// TAP states`
286			`.capture_dr_i (capture_dr_i),`
287			`.shift_dr_i (shift_dr_i),`
288			`.update_dr_i (update_dr_i),`
289
290			`.data_register_i (input_shift_reg),`
291			.module_select_i (module_selects[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
292			.top_inhibit_o (module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE]),
293			`.rst_i (rst_i),`
294
295			`// WISHBONE common signals`
296			`.wb_clk_i (wb_clk_i),`
297
298			`// WISHBONE master interface`
299			`.wb_adr_o (wb_adr_o),`
300			`.wb_dat_o (wb_dat_o),`
301			`.wb_dat_i (wb_dat_i),`
302			`.wb_cyc_o (wb_cyc_o),`
303			`.wb_stb_o (wb_stb_o),`
304			`.wb_sel_o (wb_sel_o),`
305			`.wb_we_o (wb_we_o),`
306			`.wb_ack_i (wb_ack_i),`
307			`.wb_cab_o (wb_cab_o),`
308			`.wb_err_i (wb_err_i),`
309			`.wb_cti_o (wb_cti_o),`
310			`.wb_bte_o (wb_bte_o)`
311			`);`
312			`else
313			`assign tdo_wb = 1'b0;`
314			assign module_inhibit[`DBG_TOP_WISHBONE_DEBUG_MODULE] = 1'b0;
315			`endif
316
317
318
319			`ifdef DBG_CPU0_SUPPORTED
320			`adbg_or1k_module i_dbg_cpu_or1k (`
321			`// JTAG signals`
322			`.tck_i (tck_i),`
323			`.module_tdo_o (tdo_cpu0),`
324			`.tdi_i (tdi_i),`
325
326			`// TAP states`
327			`.capture_dr_i (capture_dr_i),`
328			`.shift_dr_i (shift_dr_i),`
329			`.update_dr_i (update_dr_i),`
330
331			`.data_register_i (input_shift_reg),`
332			.module_select_i (module_selects[`DBG_TOP_CPU0_DEBUG_MODULE]),
333			.top_inhibit_o (module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE]),
334			`.rst_i (rst_i),`
335
336			`// CPU signals`
337			`.cpu_clk_i (cpu0_clk_i),`
338			`.cpu_addr_o (cpu0_addr_o),`
339			`.cpu_data_i (cpu0_data_i),`
340			`.cpu_data_o (cpu0_data_o),`
341			`.cpu_bp_i (cpu0_bp_i),`
342			`.cpu_stall_o (cpu0_stall_o),`
343			`.cpu_stb_o (cpu0_stb_o),`
344			`.cpu_we_o (cpu0_we_o),`
345			`.cpu_ack_i (cpu0_ack_i),`
346			`.cpu_rst_o (cpu0_rst_o)`
347			`);`
348			`else
349			`assign tdo_cpu0 = 1'b0;`
350			assign module_inhibit[`DBG_TOP_CPU0_DEBUG_MODULE] = 1'b0;
351			`endif // DBG_CPU0_SUPPORTED
352
353
354
355			`ifdef DBG_CPU1_SUPPORTED
356			`// Connecting cpu module`
357	42	nyawn	`adbg_or1k_module i_dbg_cpu_2 (`
358	3	nyawn	`// JTAG signals`
359			`.tck_i (tck_i),`
360			`.module_tdo_o (tdo_cpu1),`
361			`.tdi_i (tdi_i),`
362
363			`// TAP states`
364			`.capture_dr_i (capture_dr_i),`
365			`.shift_dr_i (shift_dr_i),`
366			`.update_dr_i (update_dr_i),`
367
368			`.data_register_i (input_shift_reg),`
369			.module_select_i (module_selects[`DBG_TOP_CPU1_DEBUG_MODULE]),
370			.top_inhibit_o (module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE]),
371			`.rst_i (rst_i),`
372
373			`// CPU signals`
374			`.cpu_clk_i (cpu1_clk_i),`
375			`.cpu_addr_o (cpu1_addr_o),`
376			`.cpu_data_i (cpu1_data_i),`
377			`.cpu_data_o (cpu1_data_o),`
378			`.cpu_bp_i (cpu1_bp_i),`
379			`.cpu_stall_o (cpu1_stall_o),`
380			`.cpu_stb_o (cpu1_stb_o),`
381			`.cpu_we_o (cpu1_we_o),`
382			`.cpu_ack_i (cpu1_ack_i),`
383			`.cpu_rst_o (cpu1_rst_o)`
384			`);`
385			`else
386			`assign tdo_cpu1 = 1'b0;`
387			assign module_inhibit[`DBG_TOP_CPU1_DEBUG_MODULE] = 1'b0;
388			`endif
389
390	42	nyawn	`ifdef DBG_JSP_SUPPORTED
391			`adbg_jsp_module i_dbg_jsp (`
392			`// JTAG signals`
393			`.tck_i (tck_i),`
394			`.module_tdo_o (tdo_jsp),`
395			`.tdi_i (tdi_i),`
396
397			`// TAP states`
398			`.capture_dr_i (capture_dr_i),`
399			`.shift_dr_i (shift_dr_i),`
400			`.update_dr_i (update_dr_i),`
401
402			`.data_register_i (input_shift_reg),`
403			.module_select_i (module_selects[`DBG_TOP_JSP_DEBUG_MODULE]),
404			.top_inhibit_o (module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE]),
405			`.rst_i (rst_i),`
406
407			`// WISHBONE common signals`
408			`.wb_clk_i (wb_clk_i),`
409			`.wb_rst_i (wb_rst_i),`
410
411			`// WISHBONE master interface`
412			`.wb_adr_i (wb_jsp_adr_i),`
413			`.wb_dat_o (wb_jsp_dat_o),`
414			`.wb_dat_i (wb_jsp_dat_i),`
415			`.wb_cyc_i (wb_jsp_cyc_i),`
416			`.wb_stb_i (wb_jsp_stb_i),`
417			`.wb_sel_i (wb_jsp_sel_i),`
418			`.wb_we_i (wb_jsp_we_i),`
419			`.wb_ack_o (wb_jsp_ack_o),`
420			`.wb_cab_i (wb_jsp_cab_i),`
421			`.wb_err_o (wb_jsp_err_o),`
422			`.wb_cti_i (wb_jsp_cti_i),`
423			`.wb_bte_i (wb_jsp_bte_i),`
424			`.int_o (int_o)`
425			`);`
426
427			`else
428			`assign tdo_jsp = 1'b0;`
429			assign module_inhibit[`DBG_TOP_JSP_DEBUG_MODULE] = 1'b0;
430			`endif
431
432	3	nyawn	`assign select_inhibit = \|module_inhibit;`
433
434			`/////////////////////////////////////////////////`
435			`// TDO output MUX`
436
437	42	nyawn	`always @ (module_id_reg or tdo_wb or tdo_cpu0 or tdo_cpu1 or tdo_jsp)`
438	3	nyawn	`begin`
439	42	nyawn	`case (module_id_reg)`
440			`DBG_TOP_WISHBONE_DEBUG_MODULE: tdo_o <= tdo_wb;
441			`DBG_TOP_CPU0_DEBUG_MODULE: tdo_o <= tdo_cpu0;
442			`DBG_TOP_CPU1_DEBUG_MODULE: tdo_o <= tdo_cpu1;
443			`DBG_TOP_JSP_DEBUG_MODULE: tdo_o <= tdo_jsp;
444			`default: tdo_o <= 1'b0;`
445			`endcase`
446	3	nyawn	`end`
447
448
449			`endmodule`

Browse

Tools

Subversion Repositories adv_debug_sys

[/] [adv_debug_sys/] [trunk/] [Hardware/] [adv_dbg_if/] [rtl/] [verilog/] [adbg_top.v] - Blame information for rev 42